nvidia-tegra-modules.git/include/linux/tegra-mce.h, branch rtss22-ae NVIDIA's kernel modules to support tegra chips (used in Jetson boards) t19x: l3 cache: move setting l3 cache ways in mce driver 2018-03-14T10:57:22+00:00 Puneet Saxena puneets@nvidia.com 2018-02-28T09:48:40+00:00 2063235d244098855a2db10679bd59e41ec42c80 Tegra mce driver manages all the NVG requests to MCE. An important purpose of this driver is to ensure that nvg accesses do not have conflict and only one thread is accessing these requests. Calls set and read interfaces from tegra-mce driver to set and read L3 cache ways. Bug 2069803 Change-Id: I695a80a17cac28e8247c05d42c1938cb6536be29 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1670158 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Tegra mce driver manages all the NVG requests to MCE.
An important purpose of this driver is to ensure that
nvg accesses do not have conflict and only one thread
is accessing these requests.

Calls set and read interfaces from tegra-mce driver to
set and read L3 cache ways.

Bug 2069803

Change-Id: I695a80a17cac28e8247c05d42c1938cb6536be29
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1670158
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
tegra: mce: update cstats to use 64 bits 2018-03-03T06:09:56+00:00 Krishna Sitaraman ksitaraman@nvidia.com 2018-03-01T21:22:17+00:00 9d6dc3911392f50c7294566707770208022a8716 NVG c-stats interface provides 64 bit data, but the current implementation on uses 32 bits leaving out important high order bits. This patch updates the api in tegra mce driver to pass all 64bits through the api. Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Change-Id: Ic98f9eb48b299069b50603b45349f5b7d08fe2aa Reviewed-on: https://git-master.nvidia.com/r/1667020 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
NVG c-stats interface provides 64 bit data, but the current
implementation on uses 32 bits leaving out important high order
bits. This patch updates the api in tegra mce driver to pass
all 64bits through the api.

Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Change-Id: Ic98f9eb48b299069b50603b45349f5b7d08fe2aa
Reviewed-on: https://git-master.nvidia.com/r/1667020
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
tegra: mce: add scf dda register interface 2018-01-20T00:19:55+00:00 Chetan Kumar chetankumarn@nvidia.com 2018-01-15T18:40:58+00:00 0c54e2afbd06aec00b57773686bb288195249d24 Add interface to access DDA control registers through NVG protocol, which is used by the LA/PTSA driver. Bug 1755290 JIRA: TMM-104 Change-Id: I3c76bfd65b34496289044fc29f66f553e620add3 Signed-off-by: Chetan Kumar <chetankumarn@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640625 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Add interface to access DDA control registers through NVG protocol,
which is used by the LA/PTSA driver.

Bug 1755290

JIRA: TMM-104

Change-Id: I3c76bfd65b34496289044fc29f66f553e620add3
Signed-off-by: Chetan Kumar <chetankumarn@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640625
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
platform: tegra: Reconstruct mce and cache drivers 2017-12-05T17:13:14+00:00 Nicolin Chen nicolinc@nvidia.com 2017-11-22T07:48:15+00:00 aee032f3dda0a8c87e4b9608354acd8390a836e6 The tegra-mce driver was designed for T18x only and being selected based on CONFIG_ARCH_TEGRA_18x_SOC. But Kernel 4.9 uses a unified defconfig file which means CONFIG_ARCH_TEGRA_18x_SOC is enabled on platforms like T21x as well. The same thing happends to the system with CONFIG_ARCH_TEGRA_19x_SOC as well. This creates a problem that: with previous kernel version the mce driver was not expected to be compiled while now it's compiled and its functions are being called by other drivers without caring if it's fine to execute them or not. Althouth there are some code being added to the functions based on the SoC ID so as to make them be NOP functions for older platforms like T21x, this approach is not only tedious because every exported function would need an ID check, but also doesn't fix all issues. The cache functions defined in the tegra-mce driver are using the same names of those default functions in the arch/arm64/mm/cache.S file, which means, once the tegra-mce driver gets compiled, these mce cache functions will override the default ones. On a platform like T21x, it is supposed to call those default functions but now they gets NOP functions instead. So this patch reconstructs the whole mce and cache drivers: 1) Changes tegra-mce driver to be a core driver that runs on all platforms and defines corresponding function pointers for the running platform: Abstracts similar functions in this file and diversifies them in other separate files (eg. tegra18x-mce and tegra19x-mce); Shares its header file with other user drivers. 2) Adds a new tegra18x-mce by moving T18x specific functions out of the core tegra-mce driver. Renames t19x_mce to tegra19x-mce. Allows both of SoC specific drivers and their header files to be shared and accessed by tegra-mce core driver only. 3) Adds tegra_ prefixed cache functions by calling different cache functions based on SoC ID, instead of overriding default ones. 4) Falls back to default arm64 VA cache functions for T19x instead of calling T18x roc functions, since it does not make sense to call T18x cache functions on a T19x platform. 5) Raises WARN_ON() if cache flush/clean fails. 6) Fix retry issue in t19x cache functions as retry would be -1 after the original WARN_ONCE(retry-- == 0). Bug 200363383 Bug 2017226 Change-Id: I67344ee48cc4faebef91fb7f8cf3b0bd3d4a7cec Signed-off-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1603072 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com> Tested-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
The tegra-mce driver was designed for T18x only and being selected
based on CONFIG_ARCH_TEGRA_18x_SOC. But Kernel 4.9 uses a unified
defconfig file which means CONFIG_ARCH_TEGRA_18x_SOC is enabled on
platforms like T21x as well. The same thing happends to the system
with CONFIG_ARCH_TEGRA_19x_SOC as well.

This creates a problem that: with previous kernel version the mce
driver was not expected to be compiled while now it's compiled and
its functions are being called by other drivers without caring if
it's fine to execute them or not.

Althouth there are some code being added to the functions based on
the SoC ID so as to make them be NOP functions for older platforms
like T21x, this approach is not only tedious because every exported
function would need an ID check, but also doesn't fix all issues.

The cache functions defined in the tegra-mce driver are using the
same names of those default functions in the arch/arm64/mm/cache.S
file, which means, once the tegra-mce driver gets compiled, these
mce cache functions will override the default ones. On a platform
like T21x, it is supposed to call those default functions but now
they gets NOP functions instead.

So this patch reconstructs the whole mce and cache drivers:
1) Changes tegra-mce driver to be a core driver that runs on all
   platforms and defines corresponding function pointers for the
   running platform: Abstracts similar functions in this file and
   diversifies them in other separate files (eg. tegra18x-mce and
   tegra19x-mce); Shares its header file with other user drivers.
2) Adds a new tegra18x-mce by moving T18x specific functions out
   of the core tegra-mce driver. Renames t19x_mce to tegra19x-mce.
   Allows both of SoC specific drivers and their header files to
   be shared and accessed by tegra-mce core driver only.
3) Adds tegra_ prefixed cache functions by calling different cache
   functions based on SoC ID, instead of overriding default ones.
4) Falls back to default arm64 VA cache functions for T19x instead
   of calling T18x roc functions, since it does not make sense to
   call T18x cache functions on a T19x platform.
5) Raises WARN_ON() if cache flush/clean fails.
6) Fix retry issue in t19x cache functions as retry would be -1
   after the original WARN_ONCE(retry-- == 0).

Bug 200363383
Bug 2017226

Change-Id: I67344ee48cc4faebef91fb7f8cf3b0bd3d4a7cec
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1603072
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
t18x: mce: Allow overriding cache ops using function pointers 2017-06-17T06:24:16+00:00 Sri Krishna chowdary schowdary@nvidia.com 2017-06-13T11:59:48+00:00 d4256f35a09af3c25d4889c4d00e578489d44969 Cache maintenance operations needs to be overridden based on the kind of platform. Static overriding can't help in such cases. So, use function pointers instead. Continue using existing interfaces if function pointers are not used to override the cache operations. Bug 1939440 Change-Id: Ia053460679247a3663c2d5b799463b7971fc9a24 Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com> Reviewed-on: http://git-master/r/1503021 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> 
Cache maintenance operations needs to be overridden based on
the kind of platform. Static overriding can't help in such
cases. So, use function pointers instead.

Continue using existing interfaces if function pointers are
not used to override the cache operations.

Bug 1939440

Change-Id: Ia053460679247a3663c2d5b799463b7971fc9a24
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/1503021
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
t18x: cpuidle: fix api namespace problem 2017-01-10T03:54:03+00:00 Krishna Sitaraman ksitaraman@nvidia.com 2017-01-04T21:40:41+00:00 da8fca43617b59b37385793175c5d2ae3b025a6a This change updates the mce apis used by the cpuidle driver to be chip specific instead of generic names. This allows for the kernel to support multiple SoCs without a namespace clash avoiding need for different compile time options. Change-Id: I89e9667e5363fc9fdd6f42d015d99f26743cbe09 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/1280454 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
This change updates the mce apis used by the cpuidle driver to be
chip specific instead of generic names. This allows for the kernel
to support multiple SoCs without a namespace clash avoiding need
for different compile time options.

Change-Id: I89e9667e5363fc9fdd6f42d015d99f26743cbe09
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/1280454
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
t186: ari: remove unsupported power states 2016-08-16T17:05:15+00:00 Krishna Sitaraman ksitaraman@nvidia.com 2016-08-03T00:58:05+00:00 1d40dcef6c9e8af8c93f3e9e4913f54fd28a9154 This patch removes references to defeatured or unsupported power states and any programming done for them. Change-Id: Ib8cc7dbec30e94fe10a4bbe062d20f93aa1feb66 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/1196375 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
This patch removes references to defeatured or unsupported
power states and any programming done for them.

Change-Id: Ib8cc7dbec30e94fe10a4bbe062d20f93aa1feb66
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/1196375
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
tegra: mce: wrapper for the PerfMon ARI calls 2016-06-11T05:36:41+00:00 Noah Imam nimam@nvidia.com 2016-05-16T21:00:04+00:00 b1bc8e677a198ffe6d04d802ec63679f889f1d70 Change-Id: I175eaa2520afbf9edbe45b5725bcab81837ceab6 Signed-off-by: Noah Imam <nimam@nvidia.com> Reviewed-on: http://git-master/r/1148506 Reviewed-by: Yifei Wan <ywan@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> 
Change-Id: I175eaa2520afbf9edbe45b5725bcab81837ceab6
Signed-off-by: Noah Imam <nimam@nvidia.com>
Reviewed-on: http://git-master/r/1148506
Reviewed-by: Yifei Wan <ywan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
t18x: Add ARI call to enable LATIC 2016-02-17T17:57:49+00:00 Guy Sotomayor gsotomayor@nvidia.com 2016-02-12T21:46:13+00:00 7b5e81a88d0c95d8ed10b3f578dc393e7bcbf9d2 Added a call to allow for the enabling of LATIC. LATIC can also be enabled through the use of a debugfs entry. LATIC allows some MINI ISMs to be read in the CCPLEX. The ISMs are used for various measurements relevant to particular locations in Silicon. They are small counters which can be polled to determine how fast a particular location in the Silicon is. Bug 1727050 Change-Id: I2cf8e86951e26617a93f58acc1c2f7246a22c7b9 Signed-off-by: Guy Sotomayor <gsotomayor@nvidia.com> Reviewed-on: http://git-master/r/1011475 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> 
Added a call to allow for the enabling of LATIC.  LATIC can also
be enabled through the use of a debugfs entry.

LATIC allows some MINI ISMs to be read in the CCPLEX.  The ISMs are used for
various measurements relevant to particular locations in Silicon.  They are
small counters which can be polled to determine how fast a particular location
in the Silicon is.

Bug 1727050

Change-Id: I2cf8e86951e26617a93f58acc1c2f7246a22c7b9
Signed-off-by: Guy Sotomayor <gsotomayor@nvidia.com>
Reviewed-on: http://git-master/r/1011475
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
t18x: add new roc cache clean interface 2016-02-02T09:25:03+00:00 Guy Sotomayor gsotomayor@nvidia.com 2015-12-17T01:05:14+00:00 93533997813875425a8c8bf89019aa5e4a1402bb Added new cache management interfaces for cleaning the cache. bug 200164447 Change-Id: I6a7454f25562b1c2fa234af7f46a4572cf990fb9 Signed-off-by: Guy Sotomayor <gsotomayor@nvidia.com> Reviewed-on: http://git-master/r/923916 Reviewed-by: Sri Krishna Chowdary <schowdary@nvidia.com> Tested-by: Sri Krishna Chowdary <schowdary@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/1001073 GVS: Gerrit_Virtual_Submit 
Added new cache management interfaces for cleaning the cache.

bug 200164447

Change-Id: I6a7454f25562b1c2fa234af7f46a4572cf990fb9
Signed-off-by: Guy Sotomayor <gsotomayor@nvidia.com>
Reviewed-on: http://git-master/r/923916
Reviewed-by: Sri Krishna Chowdary <schowdary@nvidia.com>
Tested-by: Sri Krishna Chowdary <schowdary@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/1001073
GVS: Gerrit_Virtual_Submit