nvidia-tegra-modules.git/include/linux/platform/tegra, branch gpu-paging NVIDIA's kernel modules to support tegra chips (used in Jetson boards) tegra: mc: Add resume function for mc 2021-12-10T15:54:20+00:00 Ketan Patil ketanp@nvidia.com 2021-11-09T14:14:14+00:00 34d8735fb9bdab04a7cfaee566f60341b659a911 mc_err is not reported after device resume as MC_INTMASK register is in reset state. Restore this register in resume. Bug 3418979 Change-Id: I04884b81164a4b95e1f11e6e78e35499b6f5e977 Signed-off-by: Ketan Patil <ketanp@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2622984 (cherry picked from commit c9638f54e8b3dc48158cce548c24bae6dbf09adc) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2638812 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: Puneet Saxena <puneets@nvidia.com> Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
mc_err is not reported after device resume as MC_INTMASK register is in
reset state. Restore this register in resume.

Bug 3418979

Change-Id: I04884b81164a4b95e1f11e6e78e35499b6f5e977
Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2622984
(cherry picked from commit c9638f54e8b3dc48158cce548c24bae6dbf09adc)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2638812
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
tegra: safety: Phase notification command 2021-07-01T22:54:13+00:00 Mantravadi Karthik mkarthik@nvidia.com 2021-06-10T08:44:50+00:00 4f6bc7b5a7fe5ceb1a7200e5752746a63eb0bb31 Why? SCE HB working starts with Init done phase notification from CCPLEX. How? The init done phase notification is scheduled at the end of safety-ivc drver probe as all the necessary items for l1ss are initialized by then. Bug 200700400 Change-Id: I18cb66b2cbe6c3184c9c23c9b7ee6f6c53f62c06 Signed-off-by: Mantravadi Karthik <mkarthik@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2542621 Reviewed-by: Preetham Chandru <pchandru@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit 
Why?
SCE HB working starts with Init done phase
notification from CCPLEX.

How?
The init done phase notification is scheduled at
the end of safety-ivc drver probe as all the
necessary items for l1ss are initialized by then.

Bug 200700400

Change-Id: I18cb66b2cbe6c3184c9c23c9b7ee6f6c53f62c06
Signed-off-by: Mantravadi Karthik <mkarthik@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2542621
Reviewed-by: Preetham Chandru <pchandru@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
tegra: safety: Move header files to include/linux 2021-05-19T08:08:56+00:00 Preetham Chandru Ramchandra pchandru@nvidia.com 2021-05-17T12:27:54+00:00 f95d8afa523faee5374d44e3b318eae82562fa66 Move tegra_nv_guard_group_id.h and tegra_nv_guard_service_id.h header files to include/linux path. Also move l1ss_submit_rq() to tegra_l1ss_kernel_interface.h Bug 200700404 Change-Id: Ib609c3f3cbaebb495729eba6d607c340c9a2f185 Signed-off-by: Preetham Chandru Ramchandra <pchandru@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2530519 Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Move tegra_nv_guard_group_id.h and tegra_nv_guard_service_id.h header
files to include/linux path.
Also move l1ss_submit_rq() to tegra_l1ss_kernel_interface.h

Bug 200700404

Change-Id: Ib609c3f3cbaebb495729eba6d607c340c9a2f185
Signed-off-by: Preetham Chandru Ramchandra <pchandru@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2530519
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
tegra: safety: Enable L1SS 2021-05-12T21:11:31+00:00 Preetham Chandru Ramchandra pchandru@nvidia.com 2021-05-05T18:44:25+00:00 397f8bd575cad792b2f6835bc7ab6eedce0a15eb This change enable L1SS with minimal functionality. Currently it only supports sending sw error to SCE (SERVICESTATUS_NOTIFICATION) and IST erros. Bug 200700404 Change-Id: I4a33756dd2f4b6715157a39d3dbc4d0d968fc52b Signed-off-by: Preetham Chandru Ramchandra <pchandru@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2525248 Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
This change enable L1SS with minimal functionality.
Currently it only supports sending sw error to SCE
(SERVICESTATUS_NOTIFICATION) and IST erros.

Bug 200700404

Change-Id: I4a33756dd2f4b6715157a39d3dbc4d0d968fc52b
Signed-off-by: Preetham Chandru Ramchandra <pchandru@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2525248
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
platform: tegra: cbb: mask SError due to CBB error 2020-12-14T12:54:09+00:00 Sumit Gupta sumitg@nvidia.com 2020-07-21T19:03:06+00:00 af707d09befb567b124be1d440feadfa41149bc5 Mask SError for illegal accesses from CCPLEX master. Interrupts will be generated for access from CCPLEX and error info will be printed within the interrupt handler instead of SError callback. Also, call BUG() to crash the system if illegal access is from CCPLEX master. For illegal accesses from other masters, interrupt is already getting generated instead of SError. Bug 3191922 Change-Id: Ie03f4f0f0ca58fb695a54183456861dd98931855 Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2118672 (cherry picked from commit ef8df45ba078e6d9ab2d648c4c122e38b600c77d) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2458251 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Mask SError for illegal accesses from CCPLEX master.
Interrupts will be generated for access from CCPLEX and
error info will be printed within the interrupt handler
instead of SError callback. Also, call BUG() to crash
the system if illegal access is from CCPLEX master.
For illegal accesses from other masters, interrupt is
already getting generated instead of SError.

Bug 3191922

Change-Id: Ie03f4f0f0ca58fb695a54183456861dd98931855
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2118672
(cherry picked from commit ef8df45ba078e6d9ab2d648c4c122e38b600c77d)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2458251
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
platform: tegra: Add API to check VPR resize 2019-08-30T08:24:37+00:00 Vedashree Vidwans vvidwans@nvidia.com 2019-08-02T20:58:45+00:00 b9cce1e2aaf3105a9e64ae594f90a8f1d51da812 This patch adds a new API to check if vpr resize is supported. This will be used in nvgpu driver module. Bug 200532122 Change-Id: I4513c2bbdadd5b1db747216ab99bb6d8466268b1 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2167079 Reviewed-on: https://git-master.nvidia.com/r/2180579 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sungwook Kim <sungwookk@nvidia.com> Reviewed-by: Vinayak Pane <vpane@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
This patch adds a new API to check if vpr resize is supported. This will
be used in nvgpu driver module.

Bug 200532122

Change-Id: I4513c2bbdadd5b1db747216ab99bb6d8466268b1
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2167079
Reviewed-on: https://git-master.nvidia.com/r/2180579
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sungwook Kim <sungwookk@nvidia.com>
Reviewed-by: Vinayak Pane <vpane@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
platform: tegra2: Support EMC/CPU ratio src switch 2019-03-08T14:00:43+00:00 Somdutta Roy somduttar@nvidia.com 2019-03-04T10:49:03+00:00 5e81f10f9bb1574a9406ee500afa9c1047e278bf Added support for switching the EMC/CPU ratio src. Src could be either the DT table or default. The DT generally will have values tuned for perf/power balance. But in less demanding use cases like display off, a low power subset of the table can be used. Provide ability to userspace HALs to notify the kernel of the change in interactivity for it to switch the src. Sysfs Node /sys/kernel/tegra_cpu_emc/table_src Use DT values echo 1 > /sys/kernel/tegra_cpu_emc/table_src Use default values echo 0 > /sys/kernel/tegra_cpu_emc/table_src Bug 2384717 Bug 1758252 Change-Id: I9bafddf2b401567d8f7976f9a8a8be21d8c08ad8 Signed-off-by: Somdutta Roy <somduttar@nvidia.com> Reviewed-on: http://git-master/r/1131520 (cherry picked from commit 029c1cf1ceb7039f4090a098f4172f59d2874e67) Signed-off-by: Biao Cao <bcao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2032522 Reviewed-by: Daniel Fu <danifu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vinayak Pane <vpane@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Added support for switching the EMC/CPU ratio src.
Src could be either the DT table or default. The
DT generally will have values tuned for perf/power
balance. But in less demanding use cases like
display off, a low power subset of the table can
be used.
Provide ability to userspace HALs to notify the
kernel of the change in interactivity for it to
switch the src.

Sysfs Node
/sys/kernel/tegra_cpu_emc/table_src

Use DT values
echo 1 > /sys/kernel/tegra_cpu_emc/table_src

Use default values
echo 0 > /sys/kernel/tegra_cpu_emc/table_src

Bug 2384717
Bug 1758252

Change-Id: I9bafddf2b401567d8f7976f9a8a8be21d8c08ad8
Signed-off-by: Somdutta Roy <somduttar@nvidia.com>
Reviewed-on: http://git-master/r/1131520
(cherry picked from commit 029c1cf1ceb7039f4090a098f4172f59d2874e67)
Signed-off-by: Biao Cao <bcao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2032522
Reviewed-by: Daniel Fu <danifu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
platform: tegra: parse userbits for cluster NOC's 2018-09-14T22:34:29+00:00 sumitg sumitg@nvidia.com 2018-09-12T11:00:27+00:00 3ca32bf749eef2c338d9f8707001ca883e9933e8 Parse failed transaction's userbits separately for Cluster Fabric NOC's from CBB central NOC's. Bug 200340783 Change-Id: I8d635b5a28b3e15e6a86978b2dc8325e131f476d Signed-off-by: sumitg <sumitg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1821397 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Parse failed transaction's userbits separately for
Cluster Fabric NOC's from CBB central NOC's.

Bug 200340783

Change-Id: I8d635b5a28b3e15e6a86978b2dc8325e131f476d
Signed-off-by: sumitg <sumitg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1821397
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
t194: bwmgr: add nvdla as bwmgr client 2018-09-13T00:48:41+00:00 Sharif Inamdar isharif@nvidia.com 2018-09-06T13:26:13+00:00 53f5b1b54a9322e1a471c801bbe8c2d3ea9e2a42 This patch updates bwmgr with nvdla as the new client for setting the emc bandwidth. Each nvdla client can independently make floor request for their bw requirement. Jira DLA-1187 Change-Id: I600812e2ae0c81111207fcd0a8a621362c770a99 Signed-off-by: Sharif Inamdar <isharif@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1814145 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
This patch updates bwmgr with nvdla as the new client
for setting the emc bandwidth.
Each nvdla client can independently make floor request
for their bw requirement.

Jira DLA-1187

Change-Id: I600812e2ae0c81111207fcd0a8a621362c770a99
Signed-off-by: Sharif Inamdar <isharif@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1814145
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
tegra: camera: rtcpu: fix boot timeouts 2018-09-13T00:47:24+00:00 Pekka Pessi ppessi@nvidia.com 2018-08-20T17:25:22+00:00 a16f79eeff8f61dccc679dd84a0ecb1f138c506e The t186-sce boot time sometimes exceeds 2000 milliseconds. The undue boot time is because the memory bandwidth problems. During the boot the DRAM image is read twice (once when copying, once when calculating SHA1). Calculate time from deasserting resets to the first mailbox handshake with camrtc. Add a dedicated bandwidth manager client for camrtc. Request for extra memory bandwidth during boot time. Retry camrtc boot if it fails. Report failed boot handshake correctly to the platform, avoid corruption. Bug 2305627 Change-Id: Ia96e369ee1b09d6298268f7bd309db1c8f326564 Signed-off-by: Pekka Pessi <ppessi@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1803895 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Semi Malinen <smalinen@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
The t186-sce boot time sometimes exceeds 2000 milliseconds. The undue
boot time is because the memory bandwidth problems. During the boot
the DRAM image is read twice (once when copying, once when calculating
SHA1).

Calculate time from deasserting resets to the first mailbox handshake
with camrtc.

Add a dedicated bandwidth manager client for camrtc. Request for extra
memory bandwidth during boot time.

Retry camrtc boot if it fails.

Report failed boot handshake correctly to the platform, avoid
corruption.

Bug 2305627

Change-Id: Ia96e369ee1b09d6298268f7bd309db1c8f326564
Signed-off-by: Pekka Pessi <ppessi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803895
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Semi Malinen <smalinen@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>