<feed xmlns='http://www.w3.org/2005/Atom'>
<title>nvidia-tegra-modules.git/include/linux/platform/tegra/carmel_ras.h, branch rtss22-ae</title>
<subtitle>NVIDIA's kernel modules to support tegra chips (used in Jetson boards)</subtitle>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/'/>
<entry>
<title>platform: tegra: create generic debugfs for RAS error inject</title>
<updated>2018-07-18T21:25:56+00:00</updated>
<author>
<name>Sumit Gupta</name>
<email>sumitg@nvidia.com</email>
</author>
<published>2018-07-04T12:56:32+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/commit/?id=07a0ad3bc9497253f19b079ab57acfc088319643'/>
<id>07a0ad3bc9497253f19b079ab57acfc088319643</id>
<content type='text'>
Creating generic debugfs node for injecting
RAS errors(one of each type).

How to use:
  - reading the node gives help info about using.
      cat /d/RAS_MCA_ERR-trip
  - write node to cause error.
    e.g:
	echo EEDDCCBBAA &gt; /d/RAS_MCA_ERR-trip
	where:
	   EE[32-39] - L3_Bank_ID
	   DD[24-31] - Logical_Cluster_ID
	   CC[16-23] - Logical_CPU_ID
	   BB[08-15] - Error type(Corr is 0, UnCorr is 1)
	   AA[00-07] - Unit
        Unit numbers will be printed in help info on reading same node

Bug 200420692

Change-Id: Ib83548b1781a55e9b980b0a506b93d5ef14b5119
Signed-off-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/1770600
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt &lt;avanbrunt@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Creating generic debugfs node for injecting
RAS errors(one of each type).

How to use:
  - reading the node gives help info about using.
      cat /d/RAS_MCA_ERR-trip
  - write node to cause error.
    e.g:
	echo EEDDCCBBAA &gt; /d/RAS_MCA_ERR-trip
	where:
	   EE[32-39] - L3_Bank_ID
	   DD[24-31] - Logical_Cluster_ID
	   CC[16-23] - Logical_CPU_ID
	   BB[08-15] - Error type(Corr is 0, UnCorr is 1)
	   AA[00-07] - Unit
        Unit numbers will be printed in help info on reading same node

Bug 200420692

Change-Id: Ib83548b1781a55e9b980b0a506b93d5ef14b5119
Signed-off-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/1770600
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt &lt;avanbrunt@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>platform: tegra: update RAS error codes</title>
<updated>2018-07-14T00:27:44+00:00</updated>
<author>
<name>Sumit Gupta</name>
<email>sumitg@nvidia.com</email>
</author>
<published>2018-07-09T13:07:00+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/commit/?id=8be06c2bf3ca96fb216f064f18da7ac6470633a7'/>
<id>8be06c2bf3ca96fb216f064f18da7ac6470633a7</id>
<content type='text'>
Updating ERR&lt;x&gt;CTLR bits and IERR codes to report correct error.
RAS/MCA error codes and bits have been changed in recent MTS code
due to which error info will not be reported correctly. So, updating
related codevalues and bits in RAS driver as per latest sheet
from MTS member "New_MCA_20180619_0114.xlsx".

Bug 200420692

Change-Id: If5268a8f0b8005cf97b147b154b9249529c108ec
Signed-off-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/1774516
Reviewed-by: svc-mobile-coverity &lt;svc-mobile-coverity@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
Reviewed-by: Rohit Khanna &lt;rokhanna@nvidia.com&gt;
Reviewed-by: Bo Yan &lt;byan@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Updating ERR&lt;x&gt;CTLR bits and IERR codes to report correct error.
RAS/MCA error codes and bits have been changed in recent MTS code
due to which error info will not be reported correctly. So, updating
related codevalues and bits in RAS driver as per latest sheet
from MTS member "New_MCA_20180619_0114.xlsx".

Bug 200420692

Change-Id: If5268a8f0b8005cf97b147b154b9249529c108ec
Signed-off-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/1774516
Reviewed-by: svc-mobile-coverity &lt;svc-mobile-coverity@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
Reviewed-by: Rohit Khanna &lt;rokhanna@nvidia.com&gt;
Reviewed-by: Bo Yan &lt;byan@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>tegra: ras: Fix L2 Error Record bits</title>
<updated>2018-05-22T01:54:39+00:00</updated>
<author>
<name>Rohit Khanna</name>
<email>rokhanna@nvidia.com</email>
</author>
<published>2018-05-08T17:21:58+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/commit/?id=8e0f27d465e2dd05d55e10667b78f3e9a0e0400d'/>
<id>8e0f27d465e2dd05d55e10667b78f3e9a0e0400d</id>
<content type='text'>
This patch does the following:-

1. This patch combines L2 URD_ECCUC(ERRCTLR bit 37) and URD_ECCUD(ERRCTLR bit 35)
to a single bit called L2 URD_ECCU(ERRCTLR bit 35).

2. Set error message for IERR = 0x53 to "L2 URD Uncorrectable"

3. Remove IERR == 0x55 for L2.

Bug 2061430

Change-Id: I46ea4fa5edaba13fe96fedbd8309fed03db5f5d8
Signed-off-by: Rohit Khanna &lt;rokhanna@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/1710654
Reviewed-by: svc-mobile-coverity &lt;svc-mobile-coverity@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt &lt;avanbrunt@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch does the following:-

1. This patch combines L2 URD_ECCUC(ERRCTLR bit 37) and URD_ECCUD(ERRCTLR bit 35)
to a single bit called L2 URD_ECCU(ERRCTLR bit 35).

2. Set error message for IERR = 0x53 to "L2 URD Uncorrectable"

3. Remove IERR == 0x55 for L2.

Bug 2061430

Change-Id: I46ea4fa5edaba13fe96fedbd8309fed03db5f5d8
Signed-off-by: Rohit Khanna &lt;rokhanna@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/1710654
Reviewed-by: svc-mobile-coverity &lt;svc-mobile-coverity@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt &lt;avanbrunt@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>tegra: ras: Add test for Correctable Errors</title>
<updated>2018-05-04T04:43:17+00:00</updated>
<author>
<name>Rohit Khanna</name>
<email>rokhanna@nvidia.com</email>
</author>
<published>2018-04-30T23:16:37+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/commit/?id=680f66da3a560599fd74d52695a3a1b0d4977c9a'/>
<id>680f66da3a560599fd74d52695a3a1b0d4977c9a</id>
<content type='text'>
This patch does the following:
- Add a test for triggering below Correctable Errors:
  1. SCF_IOB-PUTDATA_CECC_ERR
  2. L3_0_CECC_ERR-trip

How to trigger?
  1. cat /d/carmel_ras/SCF_IOB-PUTDATA_CECC_ERR-trip gives value
     echo value &gt; /d/carmel_ras/SCF_IOB-PUTDATA_CECC_ERR-trip

  2. cat /d/carmel_ras/L3_0_CECC_ERR-trip gives value
     echo value &gt; /d/carmel_ras/L3_0_CECC_ERR-trip

- Fix value of bit ERR_CTL_SCFL3_CECC_ERR

- Rename registers RAS_IFU_CTL* to ERR_CTL_IFU*

- Remove hard-coded values

Bug 200368651
Bug 200319716
Bug 200368651

Change-Id: Id3833d15e2c485f499b0b3538efbf6e237f8a983
Signed-off-by: Rohit Khanna &lt;rokhanna@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/1667697
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy &lt;vdumpa@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch does the following:
- Add a test for triggering below Correctable Errors:
  1. SCF_IOB-PUTDATA_CECC_ERR
  2. L3_0_CECC_ERR-trip

How to trigger?
  1. cat /d/carmel_ras/SCF_IOB-PUTDATA_CECC_ERR-trip gives value
     echo value &gt; /d/carmel_ras/SCF_IOB-PUTDATA_CECC_ERR-trip

  2. cat /d/carmel_ras/L3_0_CECC_ERR-trip gives value
     echo value &gt; /d/carmel_ras/L3_0_CECC_ERR-trip

- Fix value of bit ERR_CTL_SCFL3_CECC_ERR

- Rename registers RAS_IFU_CTL* to ERR_CTL_IFU*

- Remove hard-coded values

Bug 200368651
Bug 200319716
Bug 200368651

Change-Id: Id3833d15e2c485f499b0b3538efbf6e237f8a983
Signed-off-by: Rohit Khanna &lt;rokhanna@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/1667697
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy &lt;vdumpa@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>tegra: add RAS support for Carmel</title>
<updated>2017-11-08T02:01:09+00:00</updated>
<author>
<name>Rohit Khanna</name>
<email>rokhanna@nvidia.com</email>
</author>
<published>2017-02-21T23:41:45+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/commit/?id=6431ad3e99f4bcb0ff3b130049306cb16ff9fab8'/>
<id>6431ad3e99f4bcb0ff3b130049306cb16ff9fab8</id>
<content type='text'>
Add a driver to handle Carmel RAS errors per core, per core cluster
and per CCPLEX.

Carmel supports two kinds of errors :
Correctable and Uncorrectable

Correctable errors are handled using Fault Handling Interrupt (FHI)
and Uncorrectable errors using SERROR.

For FHI, the driver registers and defines callbacks that interface
with arm64_ras driver.

For SError, driver registers callbacks and defines callbacks that
interface with arm64_traps driver.

Driver also provides support for triggering RAS errors for SW testing
via debugfs nodes.

Bug 1814444
Bug 200319716
Change-Id: Id543bf62d8d00317cc1aaea9fd8c65dd03c29822
Signed-off-by: Rohit Khanna &lt;rokhanna@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/1309006
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt &lt;avanbrunt@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add a driver to handle Carmel RAS errors per core, per core cluster
and per CCPLEX.

Carmel supports two kinds of errors :
Correctable and Uncorrectable

Correctable errors are handled using Fault Handling Interrupt (FHI)
and Uncorrectable errors using SERROR.

For FHI, the driver registers and defines callbacks that interface
with arm64_ras driver.

For SError, driver registers callbacks and defines callbacks that
interface with arm64_traps driver.

Driver also provides support for triggering RAS errors for SW testing
via debugfs nodes.

Bug 1814444
Bug 200319716
Change-Id: Id543bf62d8d00317cc1aaea9fd8c65dd03c29822
Signed-off-by: Rohit Khanna &lt;rokhanna@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/1309006
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt &lt;avanbrunt@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
