nvidia-tegra-modules.git/include/linux/platform/tegra/bridge_mca.h, branch rtss22-ae NVIDIA's kernel modules to support tegra chips (used in Jetson boards) t18x: configure bridge timeout via debugfs 2017-03-29T00:03:24+00:00 Rohit Khanna rokhanna@nvidia.com 2017-02-08T02:09:06+00:00 58339ee8d02d666440dd2ed1a043675885a78479 This patch allows you to program bridge timeouts via debugfs nodes. Bug 1775293 Change-Id: I776790740d69d7116f4990fcdceb3db59bf7043b Signed-off-by: Rohit Khanna <rokhanna@nvidia.com> Reviewed-on: http://git-master/r/1306466 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> 
This patch allows you to program bridge timeouts via
debugfs nodes.

Bug 1775293

Change-Id: I776790740d69d7116f4990fcdceb3db59bf7043b
Signed-off-by: Rohit Khanna <rokhanna@nvidia.com>
Reviewed-on: http://git-master/r/1306466
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
platform: tegra: mca: configure bus timeout 2017-01-27T21:54:34+00:00 Seema Khowala seemaj@nvidia.com 2016-05-11T21:55:52+00:00 f4118d212d865bc9c707e08534107d3ed1b8b675 This patch allows you to configure bridge timeouts for axi2apb and axip2p bridges. Configuration of bridge timeout requires Bridge device tree node which has timeout specified in microseconds and "axi_cbb" clock. See Documentation/devicetree/bindings/platform/tegra/bridge-mca.txt for example. If device tree entry for the bridge doesnt specify timeout then bridge timeout is not configured. Bug 1734121 Change-Id: I7f5e76593f1d376b2425534f7d2c9bf8a8094964 Signed-off-by: Rohit Khanna <rokhanna@nvidia.com> Reviewed-on: http://git-master/r/1286125 GVS: Gerrit_Virtual_Submit Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> 
This patch allows you to configure bridge timeouts
for axi2apb and axip2p bridges.

Configuration of bridge timeout requires Bridge device tree node which has
timeout specified in microseconds and "axi_cbb" clock. See
Documentation/devicetree/bindings/platform/tegra/bridge-mca.txt for
example.

If device tree entry for the bridge doesnt specify timeout then bridge
timeout is not configured. 


Bug 1734121

Change-Id: I7f5e76593f1d376b2425534f7d2c9bf8a8094964
Signed-off-by: Rohit Khanna <rokhanna@nvidia.com>
Reviewed-on: http://git-master/r/1286125
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
t18x: add debugfs node for bridge errors 2016-02-02T23:49:20+00:00 Guy Sotomayor gsotomayor@nvidia.com 2015-12-14T22:21:50+00:00 57b9393d785404bd99ebb8f97f638683123386ac Added a debugfs node that reports the current status of the bridges in terms of what errors may be present but unreported. Change-Id: I31c3aa104afe60e696a688bd452331a30dac1322 Signed-off-by: Guy Sotomayor <gsotomayor@nvidia.com> Reviewed-on: http://git-master/r/922641 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> 
Added a debugfs node that reports the current status of the bridges in
terms of what errors may be present but unreported.

Change-Id: I31c3aa104afe60e696a688bd452331a30dac1322
Signed-off-by: Guy Sotomayor <gsotomayor@nvidia.com>
Reviewed-on: http://git-master/r/922641
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
arm64: refined machine check handling for bridges 2015-10-20T16:52:53+00:00 Guy Sotomayor gsotomayor@nvidia.com 2015-10-01T00:23:03+00:00 875fc17a0bc9611ca9dc3e9882cfa170d528ddde Fixed the protocol to the bridge for determining that there is an error being reported by a bridge and capturing the information from the bridge's error FIFO. Changed the data structure representing the bridges to allow for different bridges to have different functions for capturing the error information since the locations of the registers and the bits within those registers are different for different bridges. Change-Id: Ic4caa1910319689987e7f8d79b5d910d1038c2cf Signed-off-by: Guy Sotomayor <gsotomayor@nvidia.com> Reviewed-on: http://git-master/r/807738 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Richard Wiley <rwiley@nvidia.com> Reviewed-on: http://git-master/r/819751 Tested-by: Richard Wiley <rwiley@nvidia.com> 
Fixed the protocol to the bridge for determining that there
is an error being reported by a bridge and capturing the
information from the bridge's error FIFO.

Changed the data structure representing the bridges to allow
for different bridges to have different functions for capturing
the error information since the locations of the registers and
the bits within those registers are different for different
bridges.

Change-Id: Ic4caa1910319689987e7f8d79b5d910d1038c2cf
Signed-off-by: Guy Sotomayor <gsotomayor@nvidia.com>
Reviewed-on: http://git-master/r/807738
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Richard Wiley <rwiley@nvidia.com>
Reviewed-on: http://git-master/r/819751
Tested-by: Richard Wiley <rwiley@nvidia.com>
tegra: add bridge MCA support 2015-10-20T16:52:46+00:00 Rich Wiley rwiley@nvidia.com 2015-09-14T21:39:40+00:00 0cd84389a52914b617169cde986076f26f2f15c3 This driver adds support for the AXI/APB bridge machine check hardware in t18x. bug 200090842 Change-Id: I7f784845c1bf7033be7201570c0a72df8a497d2a Signed-off-by: Rich Wiley <rwiley@nvidia.com> Reviewed-on: http://git-master/r/798903 Reviewed-on: http://git-master/r/819750 GVS: Gerrit_Virtual_Submit 
This driver adds support for the AXI/APB bridge machine check
hardware in t18x.

bug 200090842

Change-Id: I7f784845c1bf7033be7201570c0a72df8a497d2a
Signed-off-by: Rich Wiley <rwiley@nvidia.com>
Reviewed-on: http://git-master/r/798903
Reviewed-on: http://git-master/r/819750
GVS: Gerrit_Virtual_Submit