nvidia-tegra-modules.git/include/linux/nvmap.h, branch rtss22-ae NVIDIA's kernel modules to support tegra chips (used in Jetson boards) gpu-paging: Functions to support initial working version 2022-05-25T01:16:30+00:00 Joshua Bakita jbakita@cs.unc.edu 2022-05-25T01:16:30+00:00 2c076a01e5bd0949032ef81cd0e2d37bdecafba5 - Buffer deallocation (+IOCTL) - Buffer reallocation - Private dmabuf user list and accessor 
- Buffer deallocation (+IOCTL)
- Buffer reallocation
- Private dmabuf user list and accessor
video: tegra: nvmap: add support to create RO handle from user VA 2021-05-11T03:40:05+00:00 Puneet Saxena puneets@nvidia.com 2020-07-07T16:06:40+00:00 a3c08fdbdb3508ac4895fd159aaabff576fdcd14 User malloc + mprotect/mmap a buffer as RO and as part of alloc_from_va, user pass the ACCESS_FLAGS as RO and expects NvMap to give dma_buf_fd with RO access. Below are the conditions result in NvRmMemHandle creation - 1) VA: RO and Attr: RW - Don't create NvMap Handle 2) VA: RO and Attr: RO - Create NvMap Handle and set dma_buf_fd as RO 3) VA: RW and Attr: RO - Create NvMap Handle and set dma_buf_fd as RO 4) Mixed VA: RO + RW and Attr: RO - Create NvMap Handle with dma_buf_fd as RO for the whole buffer 5) Mixed VA: RO + RW and Attr: RW - Don't Create NvMap Handle If few pages of the buffer is set as RO and rest as RW, multiple vma are created and vma->end and vma->start doesn't differ by the buffer size, passed to create handle from VA. Hence remove the check. Anyway the check is done in get_user_pages. The change sets dma_buf_fd as RW/RO so that other process should fetch the access permission just by reading f_mode of dma_buf_fd. Bug 200621238 Bug 200634660 Change-Id: I9c50c6f28664f0ff9f70dc08b15d93389e7d7201 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2515023 (cherry picked from commit 0514e68ce8948428b417c55057a4dd2f57acd9c2) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2521313 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: Amulya Yarlagadda <ayarlagadda@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit 
User malloc + mprotect/mmap a buffer as RO and
as part of alloc_from_va, user pass
the ACCESS_FLAGS as RO and expects  NvMap to give dma_buf_fd with
RO access.

Below are the conditions result in NvRmMemHandle creation -

1) VA: RO and Attr: RW
	- Don't create NvMap Handle
2) VA: RO and Attr: RO
	- Create NvMap Handle and set dma_buf_fd as RO
3) VA: RW and Attr: RO
	- Create NvMap Handle and set dma_buf_fd as RO
4) Mixed VA: RO + RW and Attr: RO
	- Create NvMap Handle with dma_buf_fd as RO for the whole
	  buffer
5) Mixed VA: RO + RW and Attr: RW
	- Don't Create NvMap Handle

If few pages of the buffer is set as RO and rest as RW,
multiple vma are created and vma->end and vma->start doesn't
differ by the buffer size, passed to create handle from VA.
Hence remove the check. Anyway the check is done in get_user_pages.

The change sets dma_buf_fd as RW/RO so that other process
should fetch the access permission just by reading f_mode
of dma_buf_fd.

Bug 200621238
Bug 200634660

Change-Id: I9c50c6f28664f0ff9f70dc08b15d93389e7d7201
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2515023
(cherry picked from commit 0514e68ce8948428b417c55057a4dd2f57acd9c2)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2521313
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Amulya Yarlagadda <ayarlagadda@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
include :uapi: move nvmap header file with IOCTL 2019-05-06T15:28:31+00:00 Anuj Gangwar anujg@nvidia.com 2019-03-13T07:24:57+00:00 8668379cc2d0dde1f97603f1b3dda4117f41cae5 Create new header file nvmap in include/uapi/linux/. The new file has IOCTL definitions which is moved from include/linux/nvmap.h. Bug 2062672 Change-Id: I87b5cc8e8a6b80168550b8033e98a5e719677fa8 Signed-off-by: Anuj Gangwar <anujg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2071430 (cherry picked from commit 2282a431b61ced655738f73fd4cf6d0df276b3c1) Reviewed-on: https://git-master.nvidia.com/r/2109951 Reviewed-by: Bibek Basu <bbasu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Create new header file nvmap in include/uapi/linux/. The new file has
IOCTL definitions which is moved from include/linux/nvmap.h.

Bug 2062672

Change-Id: I87b5cc8e8a6b80168550b8033e98a5e719677fa8
Signed-off-by: Anuj Gangwar <anujg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2071430
(cherry picked from commit 2282a431b61ced655738f73fd4cf6d0df276b3c1)
Reviewed-on: https://git-master.nvidia.com/r/2109951
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
video: tegra: nvmap: add runtime busy/idle calls 2018-04-02T05:33:00+00:00 Puneet Saxena puneets@nvidia.com 2018-03-01T10:32:31+00:00 d2c3fc38fb4afcb34503e121ccc1acda00c56dcd CVSRAM falls under cvnas cluster. nvmap_alloc/free from cvsram heap requires CV rail to be power ungated/gated. Presently CV rail is always on/not power gated as CVNAS power gating is called from driver remove and cvnas driver is statically loaded The change registers runtime cvnas busy/idle callbacks at cvsram carveout creation. It exports CVNAS power gate(nvcvnas_idle()) and CVNAS power ungate(nvcvnas_busy). The callbacks are used during nvmap_alloc/free from CVSRAM. Bug 200383595 Change-Id: I545c18ea7bcf61bb6356e2d6d05c2f4f9b1f5368 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1666574 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Rajkumar Kasirajan <rkasirajan@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
CVSRAM falls under cvnas cluster. nvmap_alloc/free
from cvsram heap requires CV rail to be power ungated/gated.
Presently CV rail is always on/not power gated as CVNAS power
gating is called from driver remove and cvnas driver is statically loaded

The change registers runtime cvnas busy/idle callbacks at
cvsram carveout creation.
It exports CVNAS power gate(nvcvnas_idle()) and CVNAS power
ungate(nvcvnas_busy). The callbacks are used during  nvmap_alloc/free
from CVSRAM.

Bug 200383595

Change-Id: I545c18ea7bcf61bb6356e2d6d05c2f4f9b1f5368
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1666574
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Rajkumar Kasirajan <rkasirajan@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
video: tegra: nvmap: support query heap size 2018-03-21T03:14:54+00:00 Navneet Kumar navneetk@nvidia.com 2018-02-21T00:41:11+00:00 8b89e98168f496ba6f1f904ed7ce7f93e83b7efe Add query heap size support ioctl, so that userspace applications could query heap sizes. Bug 2056986 Change-Id: Ia2c31559a770f4a5833b869092e013177981afee Signed-off-by: Navneet Kumar <navneetk@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1662034 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Add query heap size support ioctl, so that userspace applications could
query heap sizes.

Bug 2056986

Change-Id: Ia2c31559a770f4a5833b869092e013177981afee
Signed-off-by: Navneet Kumar <navneetk@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1662034
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
video: tegra: nvmap: support cache op on handles >= 4GB size 2017-07-07T14:39:41+00:00 Sri Krishna chowdary schowdary@nvidia.com 2017-03-15T10:41:45+00:00 8eb41a68955e4c40881e11afe0cdfd165b33473b Add a new field len_msb to nvmap_cache_op struct so as to not modify the struct's size and also support cache operations on handles larger than 4GB. This len_msb will store the most significant 32 bits of length. bug 1860962 Change-Id: I75360a8531975e79329daa655575ee58525841f6 Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com> Reviewed-on: https://git-master/r/1509944 GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com> 
Add a new field len_msb to nvmap_cache_op struct so as to not
modify the struct's size and also support cache operations
on handles larger than 4GB. This len_msb will store the most
significant 32 bits of length.

bug 1860962

Change-Id: I75360a8531975e79329daa655575ee58525841f6
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: https://git-master/r/1509944
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
video: tegra: nvmap: introduce NVMAP_IOCTL_CREATE_64 2017-05-16T04:24:21+00:00 Sri Krishna chowdary schowdary@nvidia.com 2017-03-08T10:38:38+00:00 803e99320b282e6f0dd1a1b9af74e41860c4a549 This new ioctl is needed to let user space create handles larger than 4GB. For 32-bit IOCTL, do PAGE_ALIGN before copying the value into the 64 bit size64 field. If not, some negative tests on the 32-bit IOCTL fail. bug 1860962 Change-Id: Id906916420a9696d0c3c67c8a0cae0bb33fe4465 Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com> Reviewed-on: http://git-master/r/1317169 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com> 
This new ioctl is needed to let user space create handles
larger than 4GB.

For 32-bit IOCTL, do PAGE_ALIGN before copying the value
into the 64 bit size64 field. If not, some negative tests
on the 32-bit IOCTL fail.

bug 1860962

Change-Id: Id906916420a9696d0c3c67c8a0cae0bb33fe4465
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/1317169
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
video: tegra: nvmap: add NVMAP_IOC_READ{WRITE}_64 ioctl 2017-05-10T21:16:12+00:00 Sri Krishna chowdary schowdary@nvidia.com 2017-03-08T12:41:57+00:00 29cd7b378238f4a3ccd7e1914b2060870a05de93 Allow read/write to handles larger than 4 GB. bug 1860962 Change-Id: I81b44e4e6d8753738e0c22d888a977360c363e3c Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com> Reviewed-on: http://git-master/r/1317171 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> 
Allow read/write to handles larger than 4 GB.

bug 1860962

Change-Id: I81b44e4e6d8753738e0c22d888a977360c363e3c
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/1317171
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
video: tegra: nvmap: update copyrights 2017-04-26T06:07:01+00:00 Sri Krishna chowdary schowdary@nvidia.com 2017-04-25T14:01:24+00:00 c7d2b674596f890ffd4a37cad8efc72ae992a5fc Update the text used in copyright as per GPLv2. bug 200302395 Change-Id: I5ae6186cbb55f485f81804397db656845c94fcbf Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com> Reviewed-on: http://git-master/r/1469578 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sachin Nikam <snikam@nvidia.com> 
Update the text used in copyright as per GPLv2.

bug 200302395

Change-Id: I5ae6186cbb55f485f81804397db656845c94fcbf
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/1469578
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
video: tegra: nvmap: Add NVMAP_ELEM_SIZE_U64 macro 2017-03-31T10:47:14+00:00 Sri Krishna chowdary schowdary@nvidia.com 2017-02-22T19:34:46+00:00 26d425fe8071ef56e947103c1dfd90c204989200 Support reserve and cache list operations for handles larger than 4GB. Use the NVMAP_ELEM_SIZE_U64 flag to differentiate between 32 bit and 64 bit sizes, offsets. bug 1860962 Change-Id: Ia067c7afd01df28be36ea5c82cb465e1e2f79e58 Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com> Reviewed-on: http://git-master/r/1287378 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Support reserve and cache list operations for handles
larger than 4GB. Use the NVMAP_ELEM_SIZE_U64 flag to
differentiate between 32 bit and 64 bit sizes, offsets.

bug 1860962

Change-Id: Ia067c7afd01df28be36ea5c82cb465e1e2f79e58
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/1287378
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>