nvidia-tegra-modules.git/include/dt-bindings, branch gpu-paging NVIDIA's kernel modules to support tegra chips (used in Jetson boards) thermal: Kernel driver for OC event handling 2020-06-11T21:23:53+00:00 Mantravadi Karthik mkarthik@nvidia.com 2020-03-27T15:59:22+00:00 4c608d479ed156b1b3d73ca6002501d24e1bb538 Why? In case of an OC(Over Current) event in Tegra SOC, BPMP gets an interrupt indicating the same. However, there is no indication to ccplex and userspace about the same. This driver provides the interface between BPMP OC implementation and userspace. How? Once there is an EDP OC interrupt to BPMP, BPMP writes to a Shared mailbox register dedicated for BPMP and CCPLEX communication for EDP OC. Once the interrupt is received, Kernel reads the OC status registers to realize the state of the EDP OC HW. The kernel driver provides interfaces for Userspace to poll for the status/interrupts count. Bug 1688327 Change-Id: Iec57849b2be8343bc9d8c617bffd44ab63c8fa9d Signed-off-by: Mantravadi Karthik <mkarthik@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2319540 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit 
Why?
In case of an OC(Over Current) event in Tegra SOC,
BPMP gets an interrupt indicating the same. However,
there is no indication to ccplex and userspace about
the same. This driver provides the interface between
BPMP OC implementation and userspace.

How?
Once there is an EDP OC interrupt to BPMP, BPMP writes
to a Shared mailbox register dedicated for BPMP and CCPLEX
communication for EDP OC. Once the interrupt is received,
Kernel reads the OC status registers to realize the state
of the EDP OC HW. The kernel driver provides interfaces
for Userspace to poll for the status/interrupts count.

Bug 1688327

Change-Id: Iec57849b2be8343bc9d8c617bffd44ab63c8fa9d
Signed-off-by: Mantravadi Karthik <mkarthik@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2319540
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
dt-bindings: add fuse header for gv11b 2019-05-15T23:15:01+00:00 Debarshi Dutta ddutta@nvidia.com 2019-05-14T07:15:58+00:00 8da6bfc5ad0c60f1188e5ef1fd510371e8a29fff Bug 200518434 Change-Id: I852a01ce373232fa4152debd6bc4239e6ecad22c Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2118348 Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Bug 200518434

Change-Id: I852a01ce373232fa4152debd6bc4239e6ecad22c
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118348
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
dt-bindings: define sids for virtualization 2018-07-04T21:04:05+00:00 Mika Liljeberg mliljeberg@nvidia.com 2018-07-04T11:22:06+00:00 3c142f6fa13bb94b77e1b546826b751d50a11e0a Add TEGRA_SID_VI_VM2 and rename TEGRA_SID_RCE_1X to TEGRA_SID_RCE_VM2. Jira CAMASIL-184 Change-Id: I289fc9e82f5202ce8c6ca0326efe6e0fdc95b876 Signed-off-by: Mika Liljeberg <mliljeberg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1770561 Reviewed-by: Kirill Artamonov <kartamonov@nvidia.com> Reviewed-by: Kalle Jokiniemi <kjokiniemi@nvidia.com> Reviewed-by: Deepak Kamurthy <dkamurthy@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Add TEGRA_SID_VI_VM2 and rename TEGRA_SID_RCE_1X to TEGRA_SID_RCE_VM2.

Jira CAMASIL-184

Change-Id: I289fc9e82f5202ce8c6ca0326efe6e0fdc95b876
Signed-off-by: Mika Liljeberg <mliljeberg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1770561
Reviewed-by: Kirill Artamonov <kartamonov@nvidia.com>
Reviewed-by: Kalle Jokiniemi <kjokiniemi@nvidia.com>
Reviewed-by: Deepak Kamurthy <dkamurthy@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
dt-bindings: Add various DT-Bindings headers 2018-05-04T11:32:56+00:00 Ishan Mittal imittal@nvidia.com 2016-04-04T10:51:25+00:00 788d572b0e384f1602607df2e4cec776444040b7 This pulls the DT-Binding headers needed to build T186 DTBs Change-Id: I809f719ff57e441d3921a868b6159a313a8ee7e1 Signed-off-by: Ishan Mittal <imittal@nvidia.com> Reviewed-on: http://git-master/r/1119738 
This pulls the DT-Binding headers needed to build
T186 DTBs

Change-Id: I809f719ff57e441d3921a868b6159a313a8ee7e1
Signed-off-by: Ishan Mittal <imittal@nvidia.com>
Reviewed-on: http://git-master/r/1119738
platform: tegra: add new thermal throttling driver 2018-04-27T17:24:23+00:00 Srikar Srimath Tirumala srikars@nvidia.com 2018-04-04T22:02:47+00:00 06b71702b60e9b74f71540be89579ea9b83c1bb5 Add a new throttling driver that can support one or more cooling devices which can throttle one or more clocks. Parse the DT to read the clocks that need to be throttled and calculate the throttling frequency by doing a linear interapolation between the min and max clock rates. Add initial support to throttle the CPUs using cpufreq and GPU using pmqos. Allow the slope and offset of the throttling curve to be tunable via DT properties. Bug 2022953 Change-Id: I744e1e4f65bcf12363e3f9a97cd4aebbf2c6e86a Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1699802 GVS: Gerrit_Virtual_Submit Reviewed-by: Navneet Kumar <navneetk@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Add a new throttling driver that can support one or more cooling
devices which can throttle one or more clocks.

Parse the DT to read the clocks that need to be throttled and
calculate the throttling frequency by doing a linear interapolation
between the min and max clock rates.

Add initial support to throttle the CPUs using cpufreq and GPU using
pmqos.

Allow the slope and offset of the throttling curve to be tunable via
DT properties.

Bug 2022953

Change-Id: I744e1e4f65bcf12363e3f9a97cd4aebbf2c6e86a
Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1699802
GVS: Gerrit_Virtual_Submit
Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
misc: nct1008: fix dt parsing 2018-04-06T02:40:57+00:00 Srikar Srimath Tirumala srikars@nvidia.com 2018-03-22T18:25:36+00:00 acf223c7fd95249856e881138c7ec07b5f99fa24 * Convert shutdown from nodes to properties and mark it optional. * Disable shutdown if dt property is missing. * Remove the usage of legacy gpio apis. * Fix a typo in extended-range property. * Deprecate support-hwrev. * Add dt binding header for NCT's sensors. Bug 200278110 Change-Id: I165a423a86202fc061a1bf04c442857af600c2d2 Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1680588 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Navneet Kumar <navneetk@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
* Convert shutdown from nodes to properties and mark it optional.
* Disable shutdown if dt property is missing.
* Remove the usage of legacy gpio apis.
* Fix a typo in extended-range property.
* Deprecate support-hwrev.
* Add dt binding header for NCT's sensors.

Bug 200278110

Change-Id: I165a423a86202fc061a1bf04c442857af600c2d2
Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1680588
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
platform: tegra: powergate: refactor as per linux-4.4 2018-01-11T09:08:09+00:00 Timo Alho talho@nvidia.com 2017-03-01T10:57:01+00:00 d8404ee092164033889cbba02e70f3b6b4f0883e NVIDIA linux 4.4 repository has refactored power gating driver to support T21x and T18x chips at same build. Import those changes into linux 4.9 as is since the code can be shared between kernel versions. This commit is created using git command: git checkout linux-4.4/dev-kernel-4.4 -- \ drivers/platform/tegra/powergate/powergate-t21x.c \ drivers/platform/tegra/powergate/powergate.c \ include/dt-bindings/soc/tegra186-powergate.h \ include/linux/tegra-powergate.h \ include/soc/tegra/tegra-powergate-driver.h \ include/soc/tegra/tegra_powergate.h git rm \ drivers/platform/tegra/powergate/powergate-priv.h The list of commits in linux-4.4 repository that has modified the files imported in this patch is following: 0035d30 platform: tegra: correct return value of function 725465a tegra: powergate: add weak symbol for t19x init 56547e6 include: soc: tegra: Use ARCH_TEGRA_210_SOC 350a6ec tegra: powergate: t19x support 4098a50 include: powergate: fix compilation error bfdd0dd platform: tegra: powergate: Make TEGRA_POWERGATE as integer 263cd0d tegra: platform: powergate: Get rid of powergate_ops a867f9a soc/tegra: powergate: Define minimum TEGRA_POWERGATE macros a3b6514 platform: tegra: powergate: Remove private header file ddaaac7 platform: tegra: powergate: Move powergate_chip init function to driver header 27d16e0 platform: tegra: powergate-t21x: get rid of slcg clock public APIs b185a4c platform: tegra: powergate: get rid of tegra_powergate_id_matching() 99116d4 platform: tegra: powergate: Get rid of TEGRA_IS_XXX_POWERGATE() macros 3ab7861 include: dt-bindings: Add tegra186-powergate.h c445a96 platform: tegra: powergate-t21x: Use T210_POWER_DOMAIN macros a8f6874 platform: tegra: powergate: Check ID validity for debugfs creation 15bfe28 platform: tegra: powergate: Disable boot partition for T210 938c29e platform: tegra: powergate: Use partition ID instead of powergate ID bf1387f platform: tegra: powergate: Return name as NULL if ID not supported fd6866d platform: tegra: t21x-powergate: Use local implementation for is_powered() 83a7ad0 platform: tegra: powergate: Make powergate IDS to generic d62d2cb platform: tegra: powergate: Convert powergate macros to SoC specific function b8e65dd platform: tegra: powergate: Use local APIs in tegra210 powergate driver f8a33e1 platform: tegra: powergate: Remove non-implemented APIs from header 25c644f platform: tegra: powergate: Remove local usage APIs from header e7b09e5 platform: tegra: powergate: Implement public API in common driver c7e815f platform: tegra: powergate: Move pmc/mc register access to driver e847101 platform: tegra: powergate: Do not access pmc register from common APIs 03b2d00 platform: tegra: powergate: Move SoC specific APIs to SoC HW driver 2d3eaaf platform: tegra: powergate: Get t1xx powergate ops 59c93a7 platform: tegra:powergate: Use SoC specific ops for validating ID ca2ef50 platform: tegra: Move powergate ops to common includes e43a2c8 include: tegra: powergate: Use dtbinding header for t210 powergate macros f338ba2 include: tegra: powergate: Simplify the soc ifdefs 7c1c5eec soc: tegra: use soc/tegra/chip-id.h for soc header 25db841 platform: powergate: update clock names for ve 4037683 clk: tegar: Update t210 clock settings. ab96634 platform: powergate: update clock names for ve/ve2 4ed2927 tegra: powergate: only use t186 pg_ops when chip id is TEGRA186 e93613f platform: powergate: correct sclg clock names for APE d68b41b platform: powergate: tegra: control SATA pll sequencer input 7118c16 platform: powergate: tegra: update ISPA name b11cdba platform: tegra: powergate: do not handle SATA clk 944bdbf clk: tegra: Correct some nvenc clock names Change-Id: I94ac99b79e3f15cf08d3845a80d596b7ab662455 Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-on: http://git-master/r/1308064 GVS: Gerrit_Virtual_Submit Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> 
NVIDIA linux 4.4 repository has refactored power gating driver to
support T21x and T18x chips at same build. Import those changes into
linux 4.9 as is since the code can be shared between kernel versions.

This commit is created using git command:
  git checkout linux-4.4/dev-kernel-4.4 -- \
    drivers/platform/tegra/powergate/powergate-t21x.c \
    drivers/platform/tegra/powergate/powergate.c \
    include/dt-bindings/soc/tegra186-powergate.h \
    include/linux/tegra-powergate.h \
    include/soc/tegra/tegra-powergate-driver.h \
    include/soc/tegra/tegra_powergate.h

  git rm \
    drivers/platform/tegra/powergate/powergate-priv.h

The list of commits in linux-4.4 repository that has modified the
files imported in this patch is following:
 0035d30 platform: tegra: correct return value of function
 725465a tegra: powergate: add weak symbol for t19x init
 56547e6 include: soc: tegra: Use ARCH_TEGRA_210_SOC
 350a6ec tegra: powergate: t19x support
 4098a50 include: powergate: fix compilation error
 bfdd0dd platform: tegra: powergate: Make TEGRA_POWERGATE as integer
 263cd0d tegra: platform: powergate: Get rid of powergate_ops
 a867f9a soc/tegra: powergate: Define minimum TEGRA_POWERGATE macros
 a3b6514 platform: tegra: powergate: Remove private header file
 ddaaac7 platform: tegra: powergate: Move powergate_chip init function to driver header
 27d16e0 platform: tegra: powergate-t21x: get rid of slcg clock public APIs
 b185a4c platform: tegra: powergate: get rid of tegra_powergate_id_matching()
 99116d4 platform: tegra: powergate: Get rid of TEGRA_IS_XXX_POWERGATE() macros
 3ab7861 include: dt-bindings: Add tegra186-powergate.h
 c445a96 platform: tegra: powergate-t21x: Use T210_POWER_DOMAIN macros
 a8f6874 platform: tegra: powergate: Check ID validity for debugfs creation
 15bfe28 platform: tegra: powergate: Disable boot partition for T210
 938c29e platform: tegra: powergate: Use partition ID instead of powergate ID
 bf1387f platform: tegra: powergate: Return name as NULL if ID not supported
 fd6866d platform: tegra: t21x-powergate: Use local implementation for is_powered()
 83a7ad0 platform: tegra: powergate: Make powergate IDS to generic
 d62d2cb platform: tegra: powergate: Convert powergate macros to SoC specific function
 b8e65dd platform: tegra: powergate: Use local APIs in tegra210 powergate driver
 f8a33e1 platform: tegra: powergate: Remove non-implemented APIs from header
 25c644f platform: tegra: powergate: Remove local usage APIs from header
 e7b09e5 platform: tegra: powergate: Implement public API in common driver
 c7e815f platform: tegra: powergate: Move pmc/mc register access to driver
 e847101 platform: tegra: powergate: Do not access pmc register from common APIs
 03b2d00 platform: tegra: powergate: Move SoC specific APIs to SoC HW driver
 2d3eaaf platform: tegra: powergate: Get t1xx powergate ops
 59c93a7 platform: tegra:powergate: Use SoC specific ops for validating ID
 ca2ef50 platform: tegra: Move powergate ops to common includes
 e43a2c8 include: tegra: powergate: Use dtbinding header for t210 powergate macros
 f338ba2 include: tegra: powergate: Simplify the soc ifdefs
 7c1c5eec soc: tegra: use soc/tegra/chip-id.h for soc header
 25db841 platform: powergate: update clock names for ve
 4037683 clk: tegar: Update t210 clock settings.
 ab96634 platform: powergate: update clock names for ve/ve2
 4ed2927 tegra: powergate: only use t186 pg_ops when chip id is TEGRA186
 e93613f platform: powergate: correct sclg clock names for APE
 d68b41b platform: powergate: tegra: control SATA pll sequencer input
 7118c16 platform: powergate: tegra: update ISPA name
 b11cdba platform: tegra: powergate: do not handle SATA clk
 944bdbf clk: tegra: Correct some nvenc clock names

Change-Id: I94ac99b79e3f15cf08d3845a80d596b7ab662455
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: http://git-master/r/1308064
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
include: soc: tegra: Add powergate header in soc/tegra 2018-01-11T09:08:08+00:00 Laxman Dewangan ldewangan@nvidia.com 2017-02-01T10:35:23+00:00 6d40e31d065c320dc1c6783d67ed25f8b0802712 The powergate IDs are define in the tegra210-powergate.h and tegra186-powergate.h. For client make the single header soc/tegra/tegra_powergate.h for their usage and this header will include the chip specific header for powergate definition. tegra210-powergate.h header is based on the legacy header include/dt-binding/soc/nvidia,tegra210-powergate.h with renaming the macro names. bug 200257351 Change-Id: I2366b653683d19862dc1dcf0b89be7323806326d Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/1297225 (cherry picked from commit 9385d513cbb614a9b68b70f67641d7e50f948f24) Reviewed-on: http://git-master/r/1298448 Reviewed-by: Timo Alho <talho@nvidia.com> Tested-by: Timo Alho <talho@nvidia.com> 
The powergate IDs are define in the tegra210-powergate.h and
tegra186-powergate.h. For client make the single header
soc/tegra/tegra_powergate.h for their usage and this header
will include the chip specific header for powergate definition.

tegra210-powergate.h header is based on the legacy header
include/dt-binding/soc/nvidia,tegra210-powergate.h with
renaming the macro names.

bug 200257351

Change-Id: I2366b653683d19862dc1dcf0b89be7323806326d
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/1297225
(cherry picked from commit 9385d513cbb614a9b68b70f67641d7e50f948f24)
Reviewed-on: http://git-master/r/1298448
Reviewed-by: Timo Alho <talho@nvidia.com>
Tested-by: Timo Alho <talho@nvidia.com>
Merge remote-tracking branch 'remotes/origin/dev/linux-t19x' into linux-nvidia 2017-11-16T07:44:33+00:00 Deepak Nibade dnibade@nvidia.com 2017-11-16T07:34:20+00:00 7047764bbc20ff8d839b646ad31bb4a9f97a243a Bug 200363166 Change-Id: Id0fcee1cc01fe1648afe7e3f2d44f820563898ca Signed-off-by: Deepak Nibade <dnibade@nvidia.com> 
Bug 200363166

Change-Id: Id0fcee1cc01fe1648afe7e3f2d44f820563898ca
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
dt: camrtc: Add camrtc device tree constants 2017-10-26T05:47:37+00:00 Kai Lee kailee@nvidia.com 2016-12-15T06:47:22+00:00 f735bea944b75e0e3110c99f9e928e8d51db78ac JIRA CRTC-552 Bug 1853141 Change-Id: If531c70fbee2589c91c321cb51277ce2d63572b1 Signed-off-by: Ashish Singh <assingh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1527266 Reviewed-by: Bhanu Murthy V <bmurthyv@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Jihoon Bang <jbang@nvidia.com> 
JIRA CRTC-552
Bug 1853141

Change-Id: If531c70fbee2589c91c321cb51277ce2d63572b1
Signed-off-by: Ashish Singh <assingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1527266
Reviewed-by: Bhanu Murthy V <bmurthyv@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jihoon Bang <jbang@nvidia.com>