nvidia-tegra-modules.git/include/dt-bindings/soc, branch rtss22-ae NVIDIA's kernel modules to support tegra chips (used in Jetson boards) dt-bindings: add fuse header for gv11b 2019-05-15T23:15:01+00:00 Debarshi Dutta ddutta@nvidia.com 2019-05-14T07:15:58+00:00 8da6bfc5ad0c60f1188e5ef1fd510371e8a29fff Bug 200518434 Change-Id: I852a01ce373232fa4152debd6bc4239e6ecad22c Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2118348 Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Bug 200518434

Change-Id: I852a01ce373232fa4152debd6bc4239e6ecad22c
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118348
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
platform: tegra: powergate: refactor as per linux-4.4 2018-01-11T09:08:09+00:00 Timo Alho talho@nvidia.com 2017-03-01T10:57:01+00:00 d8404ee092164033889cbba02e70f3b6b4f0883e NVIDIA linux 4.4 repository has refactored power gating driver to support T21x and T18x chips at same build. Import those changes into linux 4.9 as is since the code can be shared between kernel versions. This commit is created using git command: git checkout linux-4.4/dev-kernel-4.4 -- \ drivers/platform/tegra/powergate/powergate-t21x.c \ drivers/platform/tegra/powergate/powergate.c \ include/dt-bindings/soc/tegra186-powergate.h \ include/linux/tegra-powergate.h \ include/soc/tegra/tegra-powergate-driver.h \ include/soc/tegra/tegra_powergate.h git rm \ drivers/platform/tegra/powergate/powergate-priv.h The list of commits in linux-4.4 repository that has modified the files imported in this patch is following: 0035d30 platform: tegra: correct return value of function 725465a tegra: powergate: add weak symbol for t19x init 56547e6 include: soc: tegra: Use ARCH_TEGRA_210_SOC 350a6ec tegra: powergate: t19x support 4098a50 include: powergate: fix compilation error bfdd0dd platform: tegra: powergate: Make TEGRA_POWERGATE as integer 263cd0d tegra: platform: powergate: Get rid of powergate_ops a867f9a soc/tegra: powergate: Define minimum TEGRA_POWERGATE macros a3b6514 platform: tegra: powergate: Remove private header file ddaaac7 platform: tegra: powergate: Move powergate_chip init function to driver header 27d16e0 platform: tegra: powergate-t21x: get rid of slcg clock public APIs b185a4c platform: tegra: powergate: get rid of tegra_powergate_id_matching() 99116d4 platform: tegra: powergate: Get rid of TEGRA_IS_XXX_POWERGATE() macros 3ab7861 include: dt-bindings: Add tegra186-powergate.h c445a96 platform: tegra: powergate-t21x: Use T210_POWER_DOMAIN macros a8f6874 platform: tegra: powergate: Check ID validity for debugfs creation 15bfe28 platform: tegra: powergate: Disable boot partition for T210 938c29e platform: tegra: powergate: Use partition ID instead of powergate ID bf1387f platform: tegra: powergate: Return name as NULL if ID not supported fd6866d platform: tegra: t21x-powergate: Use local implementation for is_powered() 83a7ad0 platform: tegra: powergate: Make powergate IDS to generic d62d2cb platform: tegra: powergate: Convert powergate macros to SoC specific function b8e65dd platform: tegra: powergate: Use local APIs in tegra210 powergate driver f8a33e1 platform: tegra: powergate: Remove non-implemented APIs from header 25c644f platform: tegra: powergate: Remove local usage APIs from header e7b09e5 platform: tegra: powergate: Implement public API in common driver c7e815f platform: tegra: powergate: Move pmc/mc register access to driver e847101 platform: tegra: powergate: Do not access pmc register from common APIs 03b2d00 platform: tegra: powergate: Move SoC specific APIs to SoC HW driver 2d3eaaf platform: tegra: powergate: Get t1xx powergate ops 59c93a7 platform: tegra:powergate: Use SoC specific ops for validating ID ca2ef50 platform: tegra: Move powergate ops to common includes e43a2c8 include: tegra: powergate: Use dtbinding header for t210 powergate macros f338ba2 include: tegra: powergate: Simplify the soc ifdefs 7c1c5eec soc: tegra: use soc/tegra/chip-id.h for soc header 25db841 platform: powergate: update clock names for ve 4037683 clk: tegar: Update t210 clock settings. ab96634 platform: powergate: update clock names for ve/ve2 4ed2927 tegra: powergate: only use t186 pg_ops when chip id is TEGRA186 e93613f platform: powergate: correct sclg clock names for APE d68b41b platform: powergate: tegra: control SATA pll sequencer input 7118c16 platform: powergate: tegra: update ISPA name b11cdba platform: tegra: powergate: do not handle SATA clk 944bdbf clk: tegra: Correct some nvenc clock names Change-Id: I94ac99b79e3f15cf08d3845a80d596b7ab662455 Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-on: http://git-master/r/1308064 GVS: Gerrit_Virtual_Submit Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> 
NVIDIA linux 4.4 repository has refactored power gating driver to
support T21x and T18x chips at same build. Import those changes into
linux 4.9 as is since the code can be shared between kernel versions.

This commit is created using git command:
  git checkout linux-4.4/dev-kernel-4.4 -- \
    drivers/platform/tegra/powergate/powergate-t21x.c \
    drivers/platform/tegra/powergate/powergate.c \
    include/dt-bindings/soc/tegra186-powergate.h \
    include/linux/tegra-powergate.h \
    include/soc/tegra/tegra-powergate-driver.h \
    include/soc/tegra/tegra_powergate.h

  git rm \
    drivers/platform/tegra/powergate/powergate-priv.h

The list of commits in linux-4.4 repository that has modified the
files imported in this patch is following:
 0035d30 platform: tegra: correct return value of function
 725465a tegra: powergate: add weak symbol for t19x init
 56547e6 include: soc: tegra: Use ARCH_TEGRA_210_SOC
 350a6ec tegra: powergate: t19x support
 4098a50 include: powergate: fix compilation error
 bfdd0dd platform: tegra: powergate: Make TEGRA_POWERGATE as integer
 263cd0d tegra: platform: powergate: Get rid of powergate_ops
 a867f9a soc/tegra: powergate: Define minimum TEGRA_POWERGATE macros
 a3b6514 platform: tegra: powergate: Remove private header file
 ddaaac7 platform: tegra: powergate: Move powergate_chip init function to driver header
 27d16e0 platform: tegra: powergate-t21x: get rid of slcg clock public APIs
 b185a4c platform: tegra: powergate: get rid of tegra_powergate_id_matching()
 99116d4 platform: tegra: powergate: Get rid of TEGRA_IS_XXX_POWERGATE() macros
 3ab7861 include: dt-bindings: Add tegra186-powergate.h
 c445a96 platform: tegra: powergate-t21x: Use T210_POWER_DOMAIN macros
 a8f6874 platform: tegra: powergate: Check ID validity for debugfs creation
 15bfe28 platform: tegra: powergate: Disable boot partition for T210
 938c29e platform: tegra: powergate: Use partition ID instead of powergate ID
 bf1387f platform: tegra: powergate: Return name as NULL if ID not supported
 fd6866d platform: tegra: t21x-powergate: Use local implementation for is_powered()
 83a7ad0 platform: tegra: powergate: Make powergate IDS to generic
 d62d2cb platform: tegra: powergate: Convert powergate macros to SoC specific function
 b8e65dd platform: tegra: powergate: Use local APIs in tegra210 powergate driver
 f8a33e1 platform: tegra: powergate: Remove non-implemented APIs from header
 25c644f platform: tegra: powergate: Remove local usage APIs from header
 e7b09e5 platform: tegra: powergate: Implement public API in common driver
 c7e815f platform: tegra: powergate: Move pmc/mc register access to driver
 e847101 platform: tegra: powergate: Do not access pmc register from common APIs
 03b2d00 platform: tegra: powergate: Move SoC specific APIs to SoC HW driver
 2d3eaaf platform: tegra: powergate: Get t1xx powergate ops
 59c93a7 platform: tegra:powergate: Use SoC specific ops for validating ID
 ca2ef50 platform: tegra: Move powergate ops to common includes
 e43a2c8 include: tegra: powergate: Use dtbinding header for t210 powergate macros
 f338ba2 include: tegra: powergate: Simplify the soc ifdefs
 7c1c5eec soc: tegra: use soc/tegra/chip-id.h for soc header
 25db841 platform: powergate: update clock names for ve
 4037683 clk: tegar: Update t210 clock settings.
 ab96634 platform: powergate: update clock names for ve/ve2
 4ed2927 tegra: powergate: only use t186 pg_ops when chip id is TEGRA186
 e93613f platform: powergate: correct sclg clock names for APE
 d68b41b platform: powergate: tegra: control SATA pll sequencer input
 7118c16 platform: powergate: tegra: update ISPA name
 b11cdba platform: tegra: powergate: do not handle SATA clk
 944bdbf clk: tegra: Correct some nvenc clock names

Change-Id: I94ac99b79e3f15cf08d3845a80d596b7ab662455
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: http://git-master/r/1308064
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
include: soc: tegra: Add powergate header in soc/tegra 2018-01-11T09:08:08+00:00 Laxman Dewangan ldewangan@nvidia.com 2017-02-01T10:35:23+00:00 6d40e31d065c320dc1c6783d67ed25f8b0802712 The powergate IDs are define in the tegra210-powergate.h and tegra186-powergate.h. For client make the single header soc/tegra/tegra_powergate.h for their usage and this header will include the chip specific header for powergate definition. tegra210-powergate.h header is based on the legacy header include/dt-binding/soc/nvidia,tegra210-powergate.h with renaming the macro names. bug 200257351 Change-Id: I2366b653683d19862dc1dcf0b89be7323806326d Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/1297225 (cherry picked from commit 9385d513cbb614a9b68b70f67641d7e50f948f24) Reviewed-on: http://git-master/r/1298448 Reviewed-by: Timo Alho <talho@nvidia.com> Tested-by: Timo Alho <talho@nvidia.com> 
The powergate IDs are define in the tegra210-powergate.h and
tegra186-powergate.h. For client make the single header
soc/tegra/tegra_powergate.h for their usage and this header
will include the chip specific header for powergate definition.

tegra210-powergate.h header is based on the legacy header
include/dt-binding/soc/nvidia,tegra210-powergate.h with
renaming the macro names.

bug 200257351

Change-Id: I2366b653683d19862dc1dcf0b89be7323806326d
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/1297225
(cherry picked from commit 9385d513cbb614a9b68b70f67641d7e50f948f24)
Reviewed-on: http://git-master/r/1298448
Reviewed-by: Timo Alho <talho@nvidia.com>
Tested-by: Timo Alho <talho@nvidia.com>
Merge remote-tracking branch 'remotes/origin/dev/linux-t19x' into linux-nvidia 2017-11-16T07:44:33+00:00 Deepak Nibade dnibade@nvidia.com 2017-11-16T07:34:20+00:00 7047764bbc20ff8d839b646ad31bb4a9f97a243a Bug 200363166 Change-Id: Id0fcee1cc01fe1648afe7e3f2d44f820563898ca Signed-off-by: Deepak Nibade <dnibade@nvidia.com> 
Bug 200363166

Change-Id: Id0fcee1cc01fe1648afe7e3f2d44f820563898ca
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
dt-bindings: remove unnecesary headers 2017-10-18T14:06:19+00:00 Timo Alho talho@nvidia.com 2017-10-16T11:35:02+00:00 2846ed94c951374c75b2350f74d1abb77016126c The .dts build flow is self-contained and in separate repository, most of the dt-binding files in linux repository are unused. Remove them as unneccessary and to avoid them being off-sync with the files in .dts repos. Change-Id: I9f7120b03059590789b3c139131bd91a3a4c15a0 Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1579684 GVS: Gerrit_Virtual_Submit Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> 
The .dts build flow is self-contained and in separate repository, most
of the dt-binding files in linux repository are unused. Remove them as
unneccessary and to avoid them being off-sync with the files in .dts
repos.

Change-Id: I9f7120b03059590789b3c139131bd91a3a4c15a0
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1579684
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
bpmp: ABI headers update 2017-04-28T17:14:30+00:00 Sivaram Nair sivaramn@nvidia.com 2017-04-25T22:55:13+00:00 ffd79b26d4c8d3cce6edd1207fc3a3408678591c 866fb24 [t194][powergate] update power gate IDs to latest spec files Change-Id: Ibdede17e46f81509fdf5985d461cd273a9d8d785 Signed-off-by: Sivaram Nair <sivaramn@nvidia.com> Reviewed-on: http://git-master/r/1469935 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com> Reviewed-by: Timo Alho <talho@nvidia.com> 
866fb24 [t194][powergate] update power gate IDs to latest spec files

Change-Id: Ibdede17e46f81509fdf5985d461cd273a9d8d785
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/1469935
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com>
Reviewed-by: Timo Alho <talho@nvidia.com>
bpmp: ABI headers update 2017-02-21T18:07:46+00:00 Sivaram Nair sivaramn@nvidia.com 2017-02-16T23:23:33+00:00 c660a0a75342a820c87b36415a12a3d380de9f8a cee08ae [t194][powergate] update PCIEX IDs Change-Id: I6f8aaff32928c7d516e1d5b3289f9a386a14bcf2 Signed-off-by: Sivaram Nair <sivaramn@nvidia.com> Reviewed-on: http://git-master/r/1306494 GVS: Gerrit_Virtual_Submit Reviewed-by: Timo Alho <talho@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> 
cee08ae [t194][powergate] update PCIEX IDs

Change-Id: I6f8aaff32928c7d516e1d5b3289f9a386a14bcf2
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/1306494
GVS: Gerrit_Virtual_Submit
Reviewed-by: Timo Alho <talho@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
bpmp: ABI headers update 2016-11-11T10:21:16+00:00 Timo Alho talho@nvidia.com 2016-11-09T09:39:53+00:00 5ec3ef556d8b81db94bc3de5d931a04081fb37da 6e9f1cc [abi] add updated power gating MRQ (MRQ_PG) 2f91646 [abi][powergate] mark DFD power domain as deprecated Bug 1807173 Bug 1816297 Bug 200103574 Change-Id: I1a574595eafec3ee7afc5b5cd93420ec98922013 Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-on: http://git-master/r/1250346 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Sivaram Nair <sivaramn@nvidia.com> 
6e9f1cc [abi] add updated power gating MRQ (MRQ_PG)
2f91646 [abi][powergate] mark DFD power domain as deprecated

Bug 1807173
Bug 1816297
Bug 200103574

Change-Id: I1a574595eafec3ee7afc5b5cd93420ec98922013
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: http://git-master/r/1250346
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sivaram Nair <sivaramn@nvidia.com>
dt-bindings: add gp10b fuse header 2016-05-10T19:30:48+00:00 Adeel Raza araza@nvidia.com 2016-05-04T00:15:16+00:00 4ad7aab2aba4ac345da3cbd79c6c48c0be4e8736 Bug 1699676 Change-Id: I36032884f8df93d665d16611946184d1f95d5fd8 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/1140889 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> 
Bug 1699676

Change-Id: I36032884f8df93d665d16611946184d1f95d5fd8
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/1140889
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
bpmp: ABI headers update 2016-04-28T12:57:15+00:00 Timo Alho talho@nvidia.com 2016-04-28T05:55:01+00:00 95be2303a8f88dc040a72f81c5663ddfa940f066 72c7670 bpmp: clock documentation 25c5749 [abi] remove NPG power partitions b861b72 [abi] improve powergate ABI documentation 125a9fd [doxy] Improve the documentation structure Bug 1751204 Bug 1751205 Change-Id: I50cd2b54aeacb5f31bba6763ada2c87a5fa7e191 Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-on: http://git-master/r/1133998 Reviewed-by: Stefan Kristiansson <stefank@nvidia.com> GVS: Gerrit_Virtual_Submit 
72c7670 bpmp: clock documentation
25c5749 [abi] remove NPG power partitions
b861b72 [abi] improve powergate ABI documentation
125a9fd [doxy] Improve the documentation structure

Bug 1751204
Bug 1751205

Change-Id: I50cd2b54aeacb5f31bba6763ada2c87a5fa7e191
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: http://git-master/r/1133998
Reviewed-by: Stefan Kristiansson <stefank@nvidia.com>
GVS: Gerrit_Virtual_Submit