nvidia-tegra-modules.git/drivers/video/tegra/dc/edid.h, branch gpu-paging

video: tegra: vary i2c clock rate for scdc read

2019-06-19T22:41:47+00:00

DDC i2c clock rate is 100Khz by default. Few monitors don't seem
to handle i2c communications properly at this frequency. These
monitors work fine with lower frequencies. Hence, similar to the
approach used for EDID read, lowerd the DDC i2c clock rate for
every failed i2c read until i2c read succeeds or until we have
tried the lowest possible clock rate. We reset the clock rate
to original rate after the read operation.

API used for halving i2c clock rate during EDID read was a static
function in edid parsing source code. Updated it to make it
available in other files since we can re-use the functionality.

Also, reduced severity of i2c clock rate update print to info as
it is an info message to user, not an error.

bug 200525506

Change-Id: Idca45983a7e73b99a195e758a339b2132c3cc43c
Signed-off-by: Naveen Kumar S 
Reviewed-on: https://git-master.nvidia.com/r/2137612
Reviewed-by: Shu Zhong 
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prafull Suryawanshi 
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu 
Reviewed-by: mobile promotions 
Tested-by: mobile promotions

include: uapi: move video user-interface headers

2019-05-03T20:43:17+00:00

Move the video user-interface headers from
include/video/ to include/uapi/video/

Change the path for above headers in the dependent files

Bug 2062672

Change-Id: I95a6112097e85efea8fbc7327fbda803de7d2432
Signed-off-by: Anuj Gangwar 
Reviewed-on: https://git-master.nvidia.com/r/1943977
(cherry picked from commit bd3eb3e84b4e34e85d9d04f32fffe34fea2174de)
Signed-off-by: Anuj Gangwar 
Reviewed-on: https://git-master.nvidia.com/r/2110044
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu 
Reviewed-by: mobile promotions 
Tested-by: mobile promotions

video: tegra: fix quantization selectable

2019-01-24T13:59:17+00:00

Due to FB_CAP overflow of bits, the quant selectable bit
can't be propogated to application properly. Hence, moving
the quant selectable bits to IOCTL TEGRA_DC_EXT_GET_CAP_INFO.

bug 1774621
bug 1997185

Change-Id: I0e9fb2f87444e46ccd7c567dd783d8b18fd39052
Signed-off-by: Ahung Cheng 
Reviewed-on: https://git-master.nvidia.com/r/1574279
(cherry picked from commit 6a95bd3b8902b45c61996b241644ce02cd90818a)
Reviewed-on: https://git-master.nvidia.com/r/1972961
Reviewed-on: https://git-master.nvidia.com/r/1987684
Reviewed-by: mobile promotions 
Tested-by: mobile promotions

video: dc: add edid quirk for only cea modes

2018-10-12T22:54:04+00:00

This change is workaround for a TV where it does not
support 1080p but support CEA modes. So add edid quirk
only to force CEA modes on this TV.

bug 2408317

Change-Id: I9a54b8947a7837146c6862f06b6388ae57062590
Signed-off-by: Prafull Suryawanshi 
Reviewed-on: https://git-master.nvidia.com/r/1918950
(cherry picked from commit 8b1aecb6689840d6aa571234afe8f9ecdcaa55e6)
Reviewed-on: https://git-master.nvidia.com/r/1925144
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ujwal Patel 
Reviewed-by: mobile promotions 
Tested-by: mobile promotions

video: tegra: hdmi: hpd debounce work around

2018-06-29T21:24:44+00:00

Few TVs are known to cause HPD debounce of 1 to 4 seconds.
This change tries to identify it and retain hdmi state for
such debounce for given TVs only.

bug 2051353

Change-Id: I3c126e15e3125bdcf8cccc1890de535855a17c48
Signed-off-by: Prafull Suryawanshi 
Signed-off-by: Aly Hirani 
(cherry picked from commit 31fe100d389713988df7d057ab39b6b2346aa542)
Reviewed-on: https://git-master.nvidia.com/r/1764674
Reviewed-by: mobile promotions 
Tested-by: mobile promotions

video: tegra: dc: Add edid quirk for denon dvr

2018-06-29T21:24:34+00:00

Denon DVR 2313 have YUV422 bug where it display out
pink screen when set this mode. So adding edid quirk
to filter out YUV422 modes for this DVR.

bug 200265680

Change-Id: I394bcb0df660cf18e460aaad88c0744c9f8ffeff
Signed-off-by: Prafull Suryawanshi 
Signed-off-by: Aly Hirani 
Reviewed-on: http://git-master/r/1301331
(cherry picked from commit 665da618c0ab47b13a973d3e3dc5792c7aa4eaae)
Reviewed-on: https://git-master.nvidia.com/r/1764673
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinayak Pane 
Reviewed-by: mobile promotions 
Tested-by: mobile promotions

video: tegra: hdmi: Disable HDCP for BlackMagic

2018-06-29T21:24:30+00:00

BlackMagic 12G has a bug where it spams us with a constant stream of
hotplugs 130 ms apart if we enable HDCP. This stream of hotplugs end up
as a "blank screen" since we are stuck in a loop of modeset and display
teardown.

Since it doesn't support HDCP, this change blacklists it from HDCP. Once
done, it never sends us a hotplug and the device works perfectly after.

Bug 1870842

Change-Id: Id93b7e9bb1e11ca0cb969c9a8179bae7b4c64072
Signed-off-by: Aly Hirani 
Reviewed-on: http://git-master/r/1298315
(cherry picked from commit 33be76c8401a2ead5a802c5a0c659ca0fb8cd2e0)
Reviewed-on: https://git-master.nvidia.com/r/1764672
Reviewed-by: svc-mobile-coverity 
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinayak Pane 
Reviewed-by: mobile promotions 
Tested-by: mobile promotions

video: tegra: dc: Add quick for Vizio P series

2018-06-29T21:24:27+00:00

The Vizio SmartCast P series 4K TVs fail 1/3 hotplugs with "No Signal".
Experiments showed that enabling HDMI 2.0 scrambling and HDCP at the
same time causes this failure from Vizio's side.

This change adds a WAR to introduce a 5 second delay after modeset to
start the hdcp (instead of the standard 100ms delay).

This change also adds edid quirks to limit the 5 second delay to only
the P cast series.

Bug 1718858

Change-Id: I96d1200afa20401d09ab5d1d2966ab24ac761b2b
Signed-off-by: Aly Hirani 
Reviewed-on: http://git-master/r/1283347
(cherry picked from commit 3a7ae1de0d5ad8be78d2a84554f244a8a3ae8dfb)
Reviewed-on: https://git-master.nvidia.com/r/1764671
Reviewed-by: svc-mobile-coverity 
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinayak Pane 
Reviewed-by: mobile promotions 
Tested-by: mobile promotions

tegra: edid: Parse DisplayID E-EDID extension

2017-11-18T00:29:50+00:00

For certain timings, the pixel clock needs to be higher than 655 MHz.
Such pixel clock values can not be encoded within 16 bits, as defined
by CEA-861 format of the E-EDID extension blocks. Instead, such
extension blocks are encoded using Display ID format.

- Add minimal support to parse such extension blocks
- The change only adds support for one of the types of data block,
  called timing descriptor 1. But care has been taken to keep the
  code extensible when the need arises to parse other types of data
  blocks

TDS-3040

Change-Id: I164b31ed0f015b35467182d09334f66a3b8d7030
Signed-off-by: Jay Bhukhanwala 
Reviewed-on: https://git-master.nvidia.com/r/1597711
Reviewed-by: mobile promotions 
Tested-by: mobile promotions

video: tegra: edid: replace hard coded block size

2017-04-21T17:45:00+00:00

Replace hard coded constants with EDID_BYTES_PER_BLOCK.
This will allow low-level code to process EDID blocks without
further proliferation of hard coded constants.

Bug 1858144
JIRA: EVLR-1204

Change-Id: I8af0f04a962d68290ab54c48dfc1735030cd5c05
Signed-off-by: Tow Wang 
Reviewed-on: http://git-master/r/1464229
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Santosh Galma 
Reviewed-by: svccoveritychecker 
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban