nvidia-tegra-modules.git/drivers/video/tegra/dc/dp_debug.c, branch gpu-paging NVIDIA's kernel modules to support tegra chips (used in Jetson boards) video: dc: include k4.14 headers to fix build 2018-07-10T17:05:51+00:00 Anshuman Kar anshumank@nvidia.com 2018-06-15T22:07:30+00:00 a175ab96740e67c7417cffb8eb243399745ee613 Header changes & NULL functions required for compilation Change-Id: I89d95a3a63a4b65158d24149687912fffa0f33b7 Signed-off-by: Anshuman Kar <anshumank@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1751365 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Header changes & NULL functions required for
compilation

Change-Id: I89d95a3a63a4b65158d24149687912fffa0f33b7
Signed-off-by: Anshuman Kar <anshumank@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1751365
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
dp: add dp_debug support for HBR3 and CP2520 2018-01-26T00:55:33+00:00 Shu Zhong shuz@nvidia.com 2018-01-17T09:04:06+00:00 3d4d9c938a153392298981513cf1bb476032f18e This change updates the dp_debug test framework as follows: 1) Adds support for HBR3. 2) Adds support for the CP2520_PAT1 and CP2520_PAT3 training/test patterns. Enhanced framing should be disabled for the CP2520 patterns. 3) Changes the default test linkrate to RBR in order to be semantically consistent with the default values for all the other fields. 4) Removes all support for the "dynrange" command-line parameter since it was never needed for PHY/electrical testing. TDS-3266 Change-Id: I6d523a4ad216d95f7a6f0c9a08f34ca5413b4c39 Signed-off-by: Shu Zhong <shuz@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640727 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
This change updates the dp_debug test framework as follows:
1) Adds support for HBR3.
2) Adds support for the CP2520_PAT1 and CP2520_PAT3 training/test
   patterns. Enhanced framing should be disabled for the CP2520
   patterns.
3) Changes the default test linkrate to RBR in order to be
   semantically consistent with the default values for all the
   other fields.
4) Removes all support for the "dynrange" command-line parameter
   since it was never needed for PHY/electrical testing.

TDS-3266

Change-Id: I6d523a4ad216d95f7a6f0c9a08f34ca5413b4c39
Signed-off-by: Shu Zhong <shuz@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640727
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
tegra: sor: Add a struct for training patterns 2017-10-18T23:01:02+00:00 Jay Bhukhanwala jbhukhanwala@nvidia.com 2017-10-12T03:46:27+00:00 8760c3237b25856507fa60185e8d81d5185dea81 There is a need to gather various parameters associated with the training pattern sequences used for Display Port Link training - Define a new data structure tegra_dc_dp_training_pattern - Define a new enum, that can be used to index into the array of training pattern sequences which is initialized during sor init TDS-2806 Change-Id: I7d59c2c9fcf755998585f135525e8a84419923b8 Signed-off-by: Jay Bhukhanwala <jbhukhanwala@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1577497 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
There is a need to gather various parameters associated with the
training pattern sequences used for Display Port Link training

- Define a new data structure tegra_dc_dp_training_pattern
- Define a new enum, that can be used to index into the array of
  training pattern sequences which is initialized during sor init

TDS-2806

Change-Id: I7d59c2c9fcf755998585f135525e8a84419923b8
Signed-off-by: Jay Bhukhanwala <jbhukhanwala@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1577497
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
video: tegra: Including paneltype in test setting 2017-06-16T14:35:11+00:00 Pradeepan Patra ppatra@nvidia.com 2017-05-18T03:53:11+00:00 4271e2c0fa2d213966206bd46eea3ce0726839b5 Included panel type in DP test settings parameter. Reset value for paneltype in SOR_DP_SPARE is 1, which makes it INTERNAL panel by default. As scrambler reset value for internal and external panel are different hence test fails for external panel. To overcome the issue we provide panel type parameter in test settings to program it internal or external as per need. Bug 1904926 Change-Id: If29b1b32ad77f251904b1efef83dc1e5567861c0 Signed-off-by: Pradeepan Patra <ppatra@nvidia.com> Reviewed-on: http://git-master/r/1484539 (cherry picked from commit b3ed7ec09149d3f56a0918ca9b8977fd82c6c770) Reviewed-on: http://git-master/r/1500651 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Included panel type in DP test settings parameter.
Reset value for paneltype in SOR_DP_SPARE is 1,
which makes it INTERNAL panel by default. As scrambler
reset value for internal and external panel are
different hence test fails for external panel.
To overcome the issue we provide panel type
parameter in test settings to program it
internal or external as per need.

Bug 1904926

Change-Id: If29b1b32ad77f251904b1efef83dc1e5567861c0
Signed-off-by: Pradeepan Patra <ppatra@nvidia.com>
Reviewed-on: http://git-master/r/1484539
(cherry picked from commit b3ed7ec09149d3f56a0918ca9b8977fd82c6c770)
Reviewed-on: http://git-master/r/1500651
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
dp: stub out SSC option in dp_debug 2017-06-15T18:53:10+00:00 Shu Zhong shuz@nvidia.com 2017-06-15T01:34:13+00:00 624543f7b939aaa092afe00ead91f46a721f296f SSC is a fixed clk PROD setting that is configured at boot, and cannot be changed by SW. As such, the option that the dp_debug framework exposes to toggle SSC for PLLDP is no longer valid. To avoid breaking backwards-compatibility, this patch makes the above option a no-op and prints an informative warning message if the option is supplied by the user, instead of completely removing it. Bug 1940273 Change-Id: Iad75b57d2645c6c556dd5be582221781e9de062a Signed-off-by: Shu Zhong <shuz@nvidia.com> Reviewed-on: http://git-master/r/1502706 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Mitch Luban <mluban@nvidia.com> 
SSC is a fixed clk PROD setting that is configured at boot,
and cannot be changed by SW. As such, the option that the
dp_debug framework exposes to toggle SSC for PLLDP is no
longer valid. To avoid breaking backwards-compatibility,
this patch makes the above option a no-op and prints an
informative warning message if the option is supplied by
the user, instead of completely removing it.

Bug 1940273

Change-Id: Iad75b57d2645c6c556dd5be582221781e9de062a
Signed-off-by: Shu Zhong <shuz@nvidia.com>
Reviewed-on: http://git-master/r/1502706
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>
dc: update driver to use SOR register wrappers 2017-04-28T05:06:47+00:00 Shu Zhong shuz@nvidia.com 2017-04-14T02:15:26+00:00 3c10e67bc115435679d305d1cba55ef668dbdaa8 Inline wrapper functions are being added for certain SOR registers which have new base offsets on T19x. This change updates the driver to use these wrapper functions, instead of directly using the preexisting macro definitions. TDS-2129 Change-Id: I67eb02adf2b257a166765774310c6c32c17ee842 Signed-off-by: Shu Zhong <shuz@nvidia.com> Reviewed-on: http://git-master/r/1462878 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aron Wong <awong@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Ujwal Patel <ujwalp@nvidia.com> 
Inline wrapper functions are being added for certain
SOR registers which have new base offsets on T19x.
This change updates the driver to use these wrapper
functions, instead of directly using the preexisting
macro definitions.

TDS-2129

Change-Id: I67eb02adf2b257a166765774310c6c32c17ee842
Signed-off-by: Shu Zhong <shuz@nvidia.com>
Reviewed-on: http://git-master/r/1462878
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aron Wong <awong@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ujwal Patel <ujwalp@nvidia.com>
video: tegra: cleanup include of "dev.h" 2017-03-09T13:55:16+00:00 Timo Alho talho@nvidia.com 2017-02-14T21:23:09+00:00 ebe194b0e78a6dea51c6b7eef197327d13589649 dev.h does not exists in display repostitory. And it does not seem to be needed for anything, hence stop including it. Bug 1846312 Change-Id: I24d8bb50d849e4607d30b61f4076c1859ed22a46 Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-on: http://git-master/r/1304830 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
dev.h does not exists in display repostitory. And it does not seem to
be needed for anything, hence stop including it.

Bug 1846312

Change-Id: I24d8bb50d849e4607d30b61f4076c1859ed22a46
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: http://git-master/r/1304830
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
video: tegra: dc: add purpose of file in comments. 2017-01-17T18:44:19+00:00 Prafull Suryawanshi prafulls@nvidia.com 2016-12-23T06:22:42+00:00 10de8c3d05a48ade73b61e7500282e09d057bb49 As a part of display relocation, update file header with purpose of file instead of relative path. Change-Id: I5fe665d7e85054dbc2d370879339f1cda05be022 Signed-off-by: Prafull Suryawanshi <prafulls@nvidia.com> Reviewed-on: http://git-master/r/1275946 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit 
As a part of display relocation, update file header
with purpose of file instead of relative path.

Change-Id: I5fe665d7e85054dbc2d370879339f1cda05be022
Signed-off-by: Prafull Suryawanshi <prafulls@nvidia.com>
Reviewed-on: http://git-master/r/1275946
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
video: tegra: dp: Fix coverity defect 2016-06-24T19:17:45+00:00 Daniel Solomon daniels@nvidia.com 2016-06-16T21:12:21+00:00 bc023f990770c0c03e0fac4131b4d9160ef58c64 Fix for "CID 27856: String not null terminated (STRING_NULL)" Added +1 to buffer size during kzmalloc to allocate a terminating null. Bug 200192413 Change-Id: I0273692c5960a034b2bdfd00f2a7f2818b7058ff Signed-off-by: Daniel Solomon <daniels@nvidia.com> Reviewed-on: http://git-master/r/1166236 Reviewed-by: Shu Zhong <shuz@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Mitch Luban <mluban@nvidia.com> (cherry picked from commit 34de6232b63478329ec263fa80752e70bd56224b) Reviewed-on: http://git-master/r/1170695 
Fix for "CID 27856: String not null terminated (STRING_NULL)"

Added +1 to buffer size during kzmalloc to allocate a
terminating null.

Bug 200192413

Change-Id: I0273692c5960a034b2bdfd00f2a7f2818b7058ff
Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/1166236
Reviewed-by: Shu Zhong <shuz@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>
(cherry picked from commit 34de6232b63478329ec263fa80752e70bd56224b)
Reviewed-on: http://git-master/r/1170695
video: tegra: dp: Bypass clock register access 2016-02-15T07:47:35+00:00 Animesh Kishore ankishore@nvidia.com 2016-02-10T11:32:53+00:00 f22d1db5aafc84b539a3c09b2093f37a11cf35f2 Direct clock register access not allowed. Bug 1725378 Change-Id: Icd27a25208ebe1fe06451cee8c103e74772720f2 Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/1010412 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> 
Direct clock register access not allowed.

Bug 1725378

Change-Id: Icd27a25208ebe1fe06451cee8c103e74772720f2
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/1010412
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>