nvidia-tegra-modules.git/drivers/platform/tegra/t19x_cache.c, branch rtss22-ae

tegra: cache: fix dcache flush retry

2022-02-02T14:24:20+00:00

Presently we have number of retries as 10 to flush cache,
each flush operation takes around 95-100 us

Increased number of retries to 20, and
enabled debug version of flush code which
profiles latency, executing the flush instruction.

Bug 200782744

Change-Id: Ie32c17bacdb9d091e9e21a8384727a6479d83b47
Signed-off-by: Aditya Gupta 
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2648815
Reviewed-by: svcacv 
Reviewed-by: Rohit Upadhyay 
GVS: Gerrit_Virtual_Submit

tegra: cache: fix dcache flush retry

2018-07-04T07:49:58+00:00

Presently, dcache flush instruction is called
repeatedly in a loop and not giving chance
to context switch and service pending interrupts.

Hw recommends that if there are pending interrupts
in CPU side and flush operation is underway,
flush may exit without completing.

The change adds delay of 1 Micro second to let
interrupts should be serviced in CPU side.

It also adds debug version of flush code which
profiles latency, executing the flush instruction.
It bails out complete flush operation if flush
instruction doesn't pass after 1000 micro second.

Measured flush instruction takes 95us to 110 us
to complete the operation.

Bug 200424202

Change-Id: I625926eebc45c17d9141b0a341fe16d082da8293
Signed-off-by: Puneet Saxena 
Reviewed-on: https://git-master.nvidia.com/r/1760527
Reviewed-by: svc-mobile-coverity 
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam 
Reviewed-by: mobile promotions 
Tested-by: mobile promotions

t19x: l3 cache: sysfs node to set/get l3 ways

2018-04-13T11:15:14+00:00

Add sysfs nodes -
"sys/devices/tegra-cache/l3_gpu_only_ways"
"sys/devices/tegra-cache/l3_gpu_cpu_ways"

to set/get gpu_only and gpu_cpu ways to L3 cache.

Bug 200396528

Change-Id: I349e46afbf2dcd2e2e95442f1c29aa215141aeeb
Signed-off-by: Puneet Saxena 
Reviewed-on: https://git-master.nvidia.com/r/1684321
Reviewed-by: mobile promotions 
Tested-by: mobile promotions

t19x: l3 cache: remove hardcoded Max l3 cache ways

2018-04-09T05:32:55+00:00

Replace hardcoded L3 cache total ways by "total_ways" passed by DT.

Bug  200396528

Change-Id: I6d72cd4e1bb7a4fbd260dc01ede7d6ba3897ba60
Signed-off-by: Puneet Saxena 
Reviewed-on: https://git-master.nvidia.com/r/1684335
Reviewed-by: svc-mobile-coverity 
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam 
Tested-by: Sachin Nikam 
Reviewed-by: mobile promotions 
Tested-by: mobile promotions

t19x: l3 cache: move setting l3 cache ways in mce driver

2018-03-14T10:57:22+00:00

Tegra mce driver manages all the NVG requests to MCE.
An important purpose of this driver is to ensure that
nvg accesses do not have conflict and only one thread
is accessing these requests.

Calls set and read interfaces from tegra-mce driver to
set and read L3 cache ways.

Bug 2069803

Change-Id: I695a80a17cac28e8247c05d42c1938cb6536be29
Signed-off-by: Puneet Saxena 
Reviewed-on: https://git-master.nvidia.com/r/1670158
Reviewed-by: svc-mobile-coverity 
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam 
Reviewed-by: mobile promotions 
Tested-by: mobile promotions

t194: cache: Get instead of Set in Hypervisor mode

2018-02-26T16:18:16+00:00

In Virtualization scenario, RM server programs
the cache way setting and other VMs are not allowed
to write to CACHE_CONTROL registers.

In Linux, userspace might need to know the cache way
allocation and hence the driver is modified to provide
the same by reading the CACHE_CONTROL registers when
hypervisor mode is true.

Jira SSV-1116

Change-Id: If02bf01854adc81345298e5dca48b98c907c24e2
Signed-off-by: Ashok Kumar Sekar 
Reviewed-on: https://git-master.nvidia.com/r/1642726
Reviewed-by: svc-mobile-coverity 
Reviewed-by: Sachin Nikam 
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions 
Tested-by: mobile promotions

t19x: cache: exit from non supported platforms

2017-12-26T08:41:40+00:00

It exits out from beginning of L3 cache driver probe
if platform where the driver runs doesn't support
L3 cache.

Bug 200369620

Change-Id: I84c6ac47d7a8dff65e5535dbaa1de1c4fc07ab90
Signed-off-by: Puneet Saxena 
Reviewed-on: https://git-master.nvidia.com/r/1621150
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani 
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu 
Tested-by: Bibek Basu 
Reviewed-by: mobile promotions 
Tested-by: mobile promotions

platform: tegra: Reconstruct mce and cache drivers

2017-12-05T17:13:14+00:00

The tegra-mce driver was designed for T18x only and being selected
based on CONFIG_ARCH_TEGRA_18x_SOC. But Kernel 4.9 uses a unified
defconfig file which means CONFIG_ARCH_TEGRA_18x_SOC is enabled on
platforms like T21x as well. The same thing happends to the system
with CONFIG_ARCH_TEGRA_19x_SOC as well.

This creates a problem that: with previous kernel version the mce
driver was not expected to be compiled while now it's compiled and
its functions are being called by other drivers without caring if
it's fine to execute them or not.

Althouth there are some code being added to the functions based on
the SoC ID so as to make them be NOP functions for older platforms
like T21x, this approach is not only tedious because every exported
function would need an ID check, but also doesn't fix all issues.

The cache functions defined in the tegra-mce driver are using the
same names of those default functions in the arch/arm64/mm/cache.S
file, which means, once the tegra-mce driver gets compiled, these
mce cache functions will override the default ones. On a platform
like T21x, it is supposed to call those default functions but now
they gets NOP functions instead.

So this patch reconstructs the whole mce and cache drivers:
1) Changes tegra-mce driver to be a core driver that runs on all
   platforms and defines corresponding function pointers for the
   running platform: Abstracts similar functions in this file and
   diversifies them in other separate files (eg. tegra18x-mce and
   tegra19x-mce); Shares its header file with other user drivers.
2) Adds a new tegra18x-mce by moving T18x specific functions out
   of the core tegra-mce driver. Renames t19x_mce to tegra19x-mce.
   Allows both of SoC specific drivers and their header files to
   be shared and accessed by tegra-mce core driver only.
3) Adds tegra_ prefixed cache functions by calling different cache
   functions based on SoC ID, instead of overriding default ones.
4) Falls back to default arm64 VA cache functions for T19x instead
   of calling T18x roc functions, since it does not make sense to
   call T18x cache functions on a T19x platform.
5) Raises WARN_ON() if cache flush/clean fails.
6) Fix retry issue in t19x cache functions as retry would be -1
   after the original WARN_ONCE(retry-- == 0).

Bug 200363383
Bug 2017226

Change-Id: I67344ee48cc4faebef91fb7f8cf3b0bd3d4a7cec
Signed-off-by: Nicolin Chen 
Reviewed-on: https://git-master.nvidia.com/r/1603072
Reviewed-by: svc-mobile-coverity 
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam 
Tested-by: Sachin Nikam 
Reviewed-by: mobile promotions 
Tested-by: mobile promotions

nvidia: t19x_cache: fix static sparse warning

2017-09-11T08:35:54+00:00

Make t19x_l3cache_root as static to fix the
sparse wanring which is used only in this file.

Bug 200299572

Change-Id: I434ed190a1b47718a8e1633598b5d5a1af88d878
Signed-off-by: Sachin Nikam 
Reviewed-on: https://git-master.nvidia.com/r/1556741
Reviewed-by: svc-mobile-coverity 
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Amit Sharma (SW-TEGRA) 
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker

tegra: l3: cache: rename header file

2017-09-08T03:51:51+00:00

It renames header file "t19x_cache.h" ->
"tegra_l3_cache.h" as header file name which exposes
ioctl to userspace should be by the ioctl name.

The IOCTL prefix is TEGRA_L3_CACHE hence renaming it
tegra_l3_cache.h

Bug 200324092

Change-Id: I15911073417499f31b51e7d027fdf9d932e039c2
Signed-off-by: Puneet Saxena 
Reviewed-on: https://git-master.nvidia.com/r/1554241
Reviewed-by: mobile promotions 
Tested-by: mobile promotions