nvidia-tegra-modules.git/drivers/platform/tegra/mc, branch gpu-paging NVIDIA's kernel modules to support tegra chips (used in Jetson boards) platform: tegra: mc: add option to disable L3 alloc hint from mss nvlink 2022-02-02T20:10:57+00:00 Brad Griffis bgriffis@nvidia.com 2022-02-01T00:29:03+00:00 70c252977fc080c829b195fece6f46f73586f1e4 Accessing memory beyond 64GB boundary from GPU on Xavier needs L3 cache alloc hint disabled at mss nvlink. Bug 3486025 Change-Id: Iac3a8932a6877b371df15d3e0d8dc9ebe1e48bdd Signed-off-by: Brad Griffis <bgriffis@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2662169 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> GVS: Gerrit_Virtual_Submit 
Accessing memory beyond 64GB boundary from GPU on Xavier needs L3 cache
alloc hint disabled at mss nvlink.

Bug 3486025

Change-Id: Iac3a8932a6877b371df15d3e0d8dc9ebe1e48bdd
Signed-off-by: Brad Griffis <bgriffis@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2662169
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
GVS: Gerrit_Virtual_Submit
tegra: mc: Restore value of nvlink registers on resume 2021-12-21T03:25:36+00:00 Ketan Patil ketanp@nvidia.com 2021-12-15T05:15:03+00:00 df16cbaaabd67d8e52a802fa77c60a44e03ad15d NvLink registers are not getting restored after suspend resume. Restore these registers during resume. Bug 3418979 Change-Id: I8dff27d03c43df61d1a2c64e1aa77e0cec926645 Signed-off-by: Ketan Patil <ketanp@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2642340 (cherry picked from commit eb0b8117551011bbde82f8ef3504e36160c9ece3) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2642845 Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit 
NvLink registers are not getting restored after suspend resume. Restore
these registers during resume.

Bug 3418979

Change-Id: I8dff27d03c43df61d1a2c64e1aa77e0cec926645
Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2642340
(cherry picked from commit eb0b8117551011bbde82f8ef3504e36160c9ece3)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2642845
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
tegra: mc: Add resume function for mc 2021-12-10T15:54:20+00:00 Ketan Patil ketanp@nvidia.com 2021-11-09T14:14:14+00:00 34d8735fb9bdab04a7cfaee566f60341b659a911 mc_err is not reported after device resume as MC_INTMASK register is in reset state. Restore this register in resume. Bug 3418979 Change-Id: I04884b81164a4b95e1f11e6e78e35499b6f5e977 Signed-off-by: Ketan Patil <ketanp@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2622984 (cherry picked from commit c9638f54e8b3dc48158cce548c24bae6dbf09adc) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2638812 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: Puneet Saxena <puneets@nvidia.com> Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
mc_err is not reported after device resume as MC_INTMASK register is in
reset state. Restore this register in resume.

Bug 3418979

Change-Id: I04884b81164a4b95e1f11e6e78e35499b6f5e977
Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2622984
(cherry picked from commit c9638f54e8b3dc48158cce548c24bae6dbf09adc)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2638812
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
tegra-mc:fix 'using uninitialized variable' 2020-03-19T05:02:01+00:00 Achal Verma achalv@nvidia.com 2020-03-17T13:23:30+00:00 34c6df2fdb649f911ceae50ce973c9571578f7fb stack variable should be initailized before use. This fixes coverity issue:3008567 Bug 2028892 Change-Id: I65a554eb0727ae49060363e6e1d186de2b456886 Signed-off-by: Achal Verma <achalv@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2314056 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Dmitry Pervushin <dpervushin@nvidia.com> Reviewed-by: Phoenix Jung <pjung@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
stack variable should be initailized before
use.

This fixes coverity issue:3008567

Bug 2028892

Change-Id: I65a554eb0727ae49060363e6e1d186de2b456886
Signed-off-by: Achal Verma <achalv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2314056
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Dmitry Pervushin <dpervushin@nvidia.com>
Reviewed-by: Phoenix Jung <pjung@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
platform: t21x: bwmgr: use correct emc base addr 2019-11-15T10:39:35+00:00 Naveen Kumar S nkumars@nvidia.com 2019-11-13T14:53:06+00:00 51848b8dc9d6e101c334b6fb407b722d5c7a3f9b T21x Tegra EMC driver uses 0x7001A0000 (TEGRA_EMC0_BASE) as the EMC base address, which is not T210's EMC base address. Hence, updated it to the correct address. bug 200566618 Change-Id: Ifc2354afc50b64395d74465d6b90ea0885ecf810 Signed-off-by: Naveen Kumar S <nkumars@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2238485 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
T21x Tegra EMC driver uses 0x7001A0000 (TEGRA_EMC0_BASE) as the
EMC base address, which is not T210's EMC base address. Hence,
updated it to the correct address.

bug 200566618

Change-Id: Ifc2354afc50b64395d74465d6b90ea0885ecf810
Signed-off-by: Naveen Kumar S <nkumars@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2238485
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Revert "video: tegra: dc: fix t21x IMP calculations" 2019-10-11T22:55:45+00:00 Naveen Kumar S nkumars@nvidia.com 2019-10-09T09:00:27+00:00 a8982a76957422762b26e785e3ea10b3bbc8ff10 This reverts commit 9897007bb2f5ef2c6b7557ce719154205c6c7ab7. This change was cherry-picked to rel-32 since it was found to resolve underflow issues. But, this change seems to be causing some unexpected issues with display bandwidth allocation on T210 Jetson-TX1 and Porg platforms. Hence, reverting this change. We will have a follow-up change to fix bandwidth calculations. bug 200555268 Change-Id: I402bc0470d840cbcb32390cb309714f6da386864 Signed-off-by: Naveen Kumar S <nkumars@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2214797 GVS: Gerrit_Virtual_Submit Reviewed-by: Shu Zhong <shuz@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
This reverts commit 9897007bb2f5ef2c6b7557ce719154205c6c7ab7.

This change was cherry-picked to rel-32 since it was found to
resolve underflow issues. But, this change seems to be causing
some unexpected issues with display bandwidth allocation on
T210 Jetson-TX1 and Porg platforms. Hence, reverting this change.
We will have a follow-up change to fix bandwidth calculations.

bug 200555268

Change-Id: I402bc0470d840cbcb32390cb309714f6da386864
Signed-off-by: Naveen Kumar S <nkumars@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2214797
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shu Zhong <shuz@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Revert "video: tegra: t210: fix dram width and bw reset" 2019-10-07T22:22:25+00:00 Naveen Kumar S nkumars@nvidia.com 2019-10-07T18:16:45+00:00 c2a9b600f0ade97d03ac79cc659db5627ce5d9ad This reverts commit 0ea0f8276fa750d7db0077721ed28ad5ffad10c7. ap_drm is found to be failing with high intermittency with this change. bug 200555268 Change-Id: I91b61fa3ed99021c8943bf02aea9bf58e38d28d6 Signed-off-by: Naveen Kumar S <nkumars@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2213005 Reviewed-by: Akshatha Somayaji <asomayaji@nvidia.com> Tested-by: Akshatha Somayaji <asomayaji@nvidia.com> 
This reverts commit 0ea0f8276fa750d7db0077721ed28ad5ffad10c7.

ap_drm is found to be failing with high intermittency with this change.

bug 200555268

Change-Id: I91b61fa3ed99021c8943bf02aea9bf58e38d28d6
Signed-off-by: Naveen Kumar S <nkumars@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2213005
Reviewed-by: Akshatha Somayaji <asomayaji@nvidia.com>
Tested-by: Akshatha Somayaji <asomayaji@nvidia.com>
video: tegra: t210: fix dram width and bw reset 2019-10-04T16:12:33+00:00 Naveen Kumar S nkumars@nvidia.com 2019-09-27T07:17:29+00:00 0ea0f8276fa750d7db0077721ed28ad5ffad10c7 DRAM width was updated to 128bit as per Shield's (T214) configuration. But, T210 SoCs have 64bit DRAM width. Since Shield is on a different branch than rel-32, updating the T21x DRAM width parameter to match that of T210 SoCs on rel-32. Also, a recent update to display bandwidth programming logic caused issues with clearing/resetting bandwidth when userspace clients go down. Updated logic to avoid ignoring requests to reset bandwidth. bug 200555268 Change-Id: Ib67587ff01e26bc472167d0781cd57404f22d7a9 Signed-off-by: Naveen Kumar S <nkumars@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2207027 Reviewed-by: Shu Zhong <shuz@nvidia.com> Reviewed-by: Prafull Suryawanshi <prafulls@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Ninad Malwade <nmalwade@nvidia.com> Tested-by: Ninad Malwade <nmalwade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
DRAM width was updated to 128bit as per Shield's (T214) configuration.
But, T210 SoCs have 64bit DRAM width. Since Shield is on a different
branch than rel-32, updating the T21x DRAM width parameter to match
that of T210 SoCs on rel-32.

Also, a recent update to display bandwidth programming logic caused
issues with clearing/resetting bandwidth when userspace clients go
down. Updated logic to avoid ignoring requests to reset bandwidth.

bug 200555268

Change-Id: Ib67587ff01e26bc472167d0781cd57404f22d7a9
Signed-off-by: Naveen Kumar S <nkumars@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2207027
Reviewed-by: Shu Zhong <shuz@nvidia.com>
Reviewed-by: Prafull Suryawanshi <prafulls@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ninad Malwade <nmalwade@nvidia.com>
Tested-by: Ninad Malwade <nmalwade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
video: tegra: dc: fix t21x IMP calculations 2019-09-20T12:40:43+00:00 Prafull Suryawanshi prafulls@nvidia.com 2019-07-16T08:17:24+00:00 9897007bb2f5ef2c6b7557ce719154205c6c7ab7 This change fixes IMP calculations for t21x to align it with reference hw calculations. 1. Change DRAM WIDTH to 128. 2. Fix overflow calculation for drain_time. 3. Fix effective_row_srt_sz_bytes calculations. 4. Set emc floor for max emc clock of all windows. Bug 200515736 Change-Id: I8d49ef29493ceb9ce99c61eb64c1500a36742099 Signed-off-by: Prafull Suryawanshi <prafulls@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2153937 Reviewed-by: Shu Zhong <shuz@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Ujwal Patel <ujwalp@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> (cherry picked from commit f7134642db9235ca98435a846f77278024888c58) Reviewed-on: https://git-master.nvidia.com/r/2200626 Reviewed-by: Ahung Cheng <ahcheng@nvidia.com> Tested-by: Ahung Cheng <ahcheng@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> 
This change fixes IMP calculations for t21x to align
it with reference hw calculations.
1. Change DRAM WIDTH to 128.
2. Fix overflow calculation for drain_time.
3. Fix effective_row_srt_sz_bytes calculations.
4. Set emc floor for max emc clock of all windows.

Bug 200515736

Change-Id: I8d49ef29493ceb9ce99c61eb64c1500a36742099
Signed-off-by: Prafull Suryawanshi <prafulls@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2153937
Reviewed-by: Shu Zhong <shuz@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ujwal Patel <ujwalp@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
(cherry picked from commit f7134642db9235ca98435a846f77278024888c58)
Reviewed-on: https://git-master.nvidia.com/r/2200626
Reviewed-by: Ahung Cheng <ahcheng@nvidia.com>
Tested-by: Ahung Cheng <ahcheng@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
emc: bwmgr: add missing camrtc in client names 2019-02-27T22:57:10+00:00 sumitg sumitg@nvidia.com 2019-01-31T10:58:40+00:00 a6bbae6ac897af1771466b6f108c137bd2b56cbc Adding missing camrtc entry in tegra_bwmgr_client_names array. Due to missing entry, client_names array go out of sync with tegra_bwmgr_client_id enum. Bug 200465919 Change-Id: I31e6e7596d03ee62f38b9f1ac1aa5475f3cf90c3 Signed-off-by: sumitg <sumitg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2008461 (cherry picked from commit eae27a986b328fb620e5c429b6f22f9ba981f71c) Reviewed-on: https://git-master.nvidia.com/r/2017286 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aaron Tian <atian@nvidia.com> Tested-by: Aaron Tian <atian@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Rajkumar Kasirajan <rkasirajan@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Adding missing camrtc entry in tegra_bwmgr_client_names array.
Due to missing entry, client_names array go out of sync with
tegra_bwmgr_client_id enum.

Bug 200465919

Change-Id: I31e6e7596d03ee62f38b9f1ac1aa5475f3cf90c3
Signed-off-by: sumitg <sumitg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2008461
(cherry picked from commit eae27a986b328fb620e5c429b6f22f9ba981f71c)
Reviewed-on: https://git-master.nvidia.com/r/2017286
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aaron Tian <atian@nvidia.com>
Tested-by: Aaron Tian <atian@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Rajkumar Kasirajan <rkasirajan@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>