nvidia-tegra-modules.git/drivers/pinctrl, branch gpu-paging NVIDIA's kernel modules to support tegra chips (used in Jetson boards) pinctrl: qspi clk pin drive entry update 2019-09-20T18:09:06+00:00 Shubhi Garg shgarg@nvidia.com 2019-09-18T05:15:16+00:00 420590dadb10e9689d93148972cab77424f5a014 Offset address is wrong for qspi clk pins which causes crash while reading sysfs node to get info of "pinconf-groups". There is no pad drive register for qspi clk pins. drive entry for the pin is added under no_entry group. Bug 2694961 Change-Id: I1b5bb2c71e0593ed548dda658c3fb2c3f8be012f Signed-off-by: Shubhi Garg <shgarg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2200274 Reviewed-by: Rajesh Gumasta <rgumasta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Offset address is wrong for qspi clk pins which causes crash while reading
sysfs node to get info of "pinconf-groups".
There is no pad drive register for qspi clk pins. drive entry for the pin
is added under no_entry group.

Bug 2694961

Change-Id: I1b5bb2c71e0593ed548dda658c3fb2c3f8be012f
Signed-off-by: Shubhi Garg <shgarg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2200274
Reviewed-by: Rajesh Gumasta <rgumasta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
tegra: dpaux: support pm functionality 2018-06-21T09:57:54+00:00 Sandipan Patra spatra@nvidia.com 2018-06-20T10:51:22+00:00 d67d4939eb5982a760f2183b6f7960c66218ac8e Power management functionalities are supported on dpaux driver. Which will enabled i2c/dp to behave correctly after system resumes back from SC7. Functionalities: suspend resume Bug 200387262 Change-Id: Ie8d75c06acc4c50a74acd26a767bf23a61a3abc6 Signed-off-by: Sandipan Patra <spatra@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1755721 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Power management functionalities are supported on dpaux driver. Which
will enabled i2c/dp to behave correctly after system resumes back from
SC7.
Functionalities:
	suspend
	resume

Bug 200387262

Change-Id: Ie8d75c06acc4c50a74acd26a767bf23a61a3abc6
Signed-off-by: Sandipan Patra <spatra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1755721
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
pinctrl: tegra186-padctrl: remove nvhost dependency 2018-06-01T21:05:26+00:00 Timo Alho talho@nvidia.com 2018-05-04T13:08:36+00:00 21c6542a905a06c1e836b1a4475652ddfb2303df The standalone Tegra186 DPAUX pinmuxing driver is split into two driver parts: "tegra186-dpaux-driver" and "tegra186-dpaux-pinctrl". The former driver initializes a power domain via nvhost domain intialization calls and latter driver controls the domain via nvhost runtime calls. I was not able to find written history for this driver architecture, but this complexity should not be needed: DPAUX pin control is not a nvhost client device and there needs to be no interaction with it. Hence with this patch remove "tegra186-dpaux-driver" and all dependencies to nvhost. Instead add calls to control clock, resets, and power domains directly from the "tegra186-dpaux-pinctrl" driver. Bug 200403104 Change-Id: Ic7a92995278cfb81c7a932df0fb30ea0eb0f86ab Signed-off-by: Timo Alho <talho@nvidia.com> Signed-off-by: Vishwaroop <va@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1708450 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
The standalone Tegra186 DPAUX pinmuxing driver is split into two
driver parts: "tegra186-dpaux-driver" and "tegra186-dpaux-pinctrl".
The former driver initializes a power domain via nvhost domain
intialization calls and latter driver controls the domain via nvhost
runtime calls.

I was not able to find written history for this driver architecture, but
this complexity should not be needed: DPAUX pin control is not a nvhost
client device and there needs to be no interaction with it.

Hence with this patch remove "tegra186-dpaux-driver" and all dependencies
to nvhost. Instead add calls to control clock, resets, and power domains
directly from the "tegra186-dpaux-pinctrl" driver.

Bug 200403104

Change-Id: Ic7a92995278cfb81c7a932df0fb30ea0eb0f86ab
Signed-off-by: Timo Alho <talho@nvidia.com>
Signed-off-by: Vishwaroop <va@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1708450
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
tegra: dpaux-pinmux:Add T194 dpaux pinctrl support 2018-03-13T21:10:07+00:00 Shardar Shariff Md smohammed@nvidia.com 2018-03-06T12:10:09+00:00 0bb3b78f4394ac63c12495654f66234d46e23bc3 Add support for T194 dpaux I2C pin configuration. This driver adds support for 4 dpaux instnace that helps in muxing the dpaux I2C pins to configure as I2C or DPAUX functionality. Bug 200387262 Change-Id: I2c16bed87519488c11c265513b59cc7dc4577dc4 Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1665636 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Add support for T194 dpaux I2C pin configuration. This driver
adds support for 4 dpaux instnace that helps in muxing the
dpaux I2C pins to configure as I2C or DPAUX functionality.

Bug 200387262

Change-Id: I2c16bed87519488c11c265513b59cc7dc4577dc4
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1665636
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Kconfig: make PINCTRL and GPIO drivers optional 2018-03-08T12:27:17+00:00 Bitan Biswas bbiswas@nvidia.com 2018-02-20T14:44:37+00:00 78066f6818426daa518243b5bf5fc503ff8e59ba PINCTRL_TEGRA186 and GPIO_TEGRA186 drivers are selected always when ARCH_TEGRA_18x_SOC is enabled (and similarly for T194). This causes build problems for new kernel versions that do not yet have all dependencies in place to support these drivers. Instead of explicitly selecting them as part of ARCH_TEGRA... config, make PINCTRL_TEGRA186, PINCTRL_TEGRA_194, and GPIO_TEGRA186 selectable but default them as 'y' so there will be no visible impact to current defconfig files. Bug 200385931 Bug 200381871 Bug 200381875 Change-Id: I8bb0a1826d04acfe1280676af2f32d97404cde3d Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1661374 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Timo Alho <talho@nvidia.com> Tested-by: Timo Alho <talho@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
PINCTRL_TEGRA186 and GPIO_TEGRA186 drivers are selected always when
ARCH_TEGRA_18x_SOC is enabled (and similarly for T194). This causes
build problems for new kernel versions that do not yet have all
dependencies in place to support these drivers.

Instead of explicitly selecting them as part of ARCH_TEGRA... config,
make PINCTRL_TEGRA186, PINCTRL_TEGRA_194, and GPIO_TEGRA186 selectable
but default them as 'y' so there will be no visible impact to current
defconfig files.

Bug 200385931
Bug 200381871
Bug 200381875

Change-Id: I8bb0a1826d04acfe1280676af2f32d97404cde3d
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1661374
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Timo Alho <talho@nvidia.com>
Tested-by: Timo Alho <talho@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
pinctrl: t19x: Enable tristate in input direction 2017-12-21T20:34:06+00:00 Laxman Dewangan ldewangan@nvidia.com 2017-12-20T14:01:08+00:00 104677351c95873aaf519fad74cb3d740202fb28 Enable tristate of pin in input direction and disable input mode in pin output direction. This helps in emulating the pin in open drain mode. Change-Id: I0416ccb0a43dab93b21cad1d3814342347090619 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1623217 Reviewed-by: Venkat Reddy Talla <vreddytalla@nvidia.com> Tested-by: Venkat Reddy Talla <vreddytalla@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Tested-by: Henry Lin <henryl@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Enable tristate of pin in input direction and disable
input mode in pin output direction. This helps in
emulating the pin in open drain mode.

Change-Id: I0416ccb0a43dab93b21cad1d3814342347090619
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1623217
Reviewed-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
Tested-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Tested-by: Henry Lin <henryl@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
pinctrl: t194: t194: Pin soc_gpio31 has sdmmc1 option 2017-12-08T13:13:37+00:00 Laxman Dewangan ldewangan@nvidia.com 2017-12-07T09:38:13+00:00 dca2870541a490dacfd81d6c10149f4ac3c33310 The pin hsoc_gpio31 have the option1 as SDMMC1. Correct table. Change-Id: I4267b27ae05b9ed5ff400cf5268877831d798f37 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1613116 Reviewed-by: Shardar Mohammed <smohammed@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
The pin hsoc_gpio31 have the option1 as SDMMC1.
Correct table.

Change-Id: I4267b27ae05b9ed5ff400cf5268877831d798f37
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1613116
Reviewed-by: Shardar Mohammed <smohammed@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Merge remote-tracking branch 'remotes/origin/dev/linux-t19x' into linux-nvidia 2017-11-16T07:44:33+00:00 Deepak Nibade dnibade@nvidia.com 2017-11-16T07:34:20+00:00 7047764bbc20ff8d839b646ad31bb4a9f97a243a Bug 200363166 Change-Id: Id0fcee1cc01fe1648afe7e3f2d44f820563898ca Signed-off-by: Deepak Nibade <dnibade@nvidia.com> 
Bug 200363166

Change-Id: Id0fcee1cc01fe1648afe7e3f2d44f820563898ca
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
t19x: use $(srctree.$(overlay)) 2017-11-09T11:27:20+00:00 Stephen Warren swarren@nvidia.com 2017-11-06T21:54:21+00:00 2bce27439a4d2f85232a11e19316d31457abd399 Update all Makefiles to make use of the new srctree.$(overlay) variables to remove hard-coding the path to any overlays. Bug 1978395 Change-Id: Ic512ceebb15fa5e5a132b72446ab476ecac6e37e Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593801 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-by: Timo Alho <talho@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Update all Makefiles to make use of the new srctree.$(overlay) variables
to remove hard-coding the path to any overlays.

Bug 1978395

Change-Id: Ic512ceebb15fa5e5a132b72446ab476ecac6e37e
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1593801
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-by: Timo Alho <talho@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
nvidia: use $(srctree.$(overlay)) 2017-11-09T11:27:16+00:00 Stephen Warren swarren@nvidia.com 2017-11-06T21:53:42+00:00 629ade0daaa5b8a3c24dbeadc2a5fb046d4dbbf4 Update all Makefiles to make use of the new srctree.$(overlay) variables to remove hard-coding the path to any overlays. One direct reference remains in a hard-coded include statement in drivers/misc/tegra-cec/. Bug 1978395 Change-Id: I5cdce04e019567a9bbfffaf0e92a61bd16806e99 Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593800 Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Timo Alho <talho@nvidia.com> Tested-by: Timo Alho <talho@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Update all Makefiles to make use of the new srctree.$(overlay) variables
to remove hard-coding the path to any overlays. One direct reference
remains in a hard-coded include statement in drivers/misc/tegra-cec/.

Bug 1978395

Change-Id: I5cdce04e019567a9bbfffaf0e92a61bd16806e99
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1593800
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Timo Alho <talho@nvidia.com>
Tested-by: Timo Alho <talho@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>