nvidia-tegra-modules.git/drivers/phy, branch gpu-paging NVIDIA's kernel modules to support tegra chips (used in Jetson boards) PHY: tegra: move P2U driver inside tegra 2018-07-11T19:34:02+00:00 Vidya Sagar vidyas@nvidia.com 2018-07-10T09:56:41+00:00 1a79e9d476847138a3e513c1721f429dd09472dc moves PCIe's P2U phy driver to inside tegra folder as this phy is specific to Tegra Bug 200415690 Change-Id: Ie7f3999434f58e98103ac7d432ecfed96577a33a Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1775079 Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
moves PCIe's P2U phy driver to inside tegra folder as
this phy is specific to Tegra

Bug 200415690

Change-Id: Ie7f3999434f58e98103ac7d432ecfed96577a33a
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1775079
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
phy: tegra: pcie: DT based UPHY Rx idle detection 2018-05-04T04:44:11+00:00 Vidya Sagar vidyas@nvidia.com 2018-04-25T06:16:18+00:00 7017f3814900df1e6dcb228e3f8b91a4ab5de851 Implements device tree flag based uphy rx idle EIOS detection Bug 200400004 Change-Id: Ie590631eb7758508d3b3940576f0ffd1508169de Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702200 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Implements device tree flag based uphy rx idle EIOS detection

Bug 200400004

Change-Id: Ie590631eb7758508d3b3940576f0ffd1508169de
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1702200
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
phy: tegra: pcie: Apply Gen-3 EQ setting 2018-03-21T07:24:07+00:00 Vidya Sagar vidyas@nvidia.com 2018-03-16T14:46:08+00:00 eb167e17d64169d62e584eabdb4cbb448d789ed5 Disables periodic equalization setting for Gen-3 speed Bug 200397978 Change-Id: Ibc4f65a465972b554794749c16c46f1bd845df33 Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1676717 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Disables periodic equalization setting for Gen-3 speed

Bug 200397978

Change-Id: Ibc4f65a465972b554794749c16c46f1bd845df33
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1676717
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
phy: tegra: pcie: Enable EIOS based on UPHY rx_idle_status 2018-03-21T07:23:58+00:00 Vidya Sagar vidyas@nvidia.com 2018-03-08T13:41:16+00:00 9162d683b6b4a9c37559ff24fa6eec5cffbc9a8e Enables EIOS based on UPHY's rx_idle_status instead of P2U's EIOS detection mechanism at Gen-1 speed to avoid unwanted DUT symbol alignment with first COM symbol of EIOS Bug 200397640 Change-Id: I30cf5441a6311701eb29de1ac1ce5d5f9c2055ff Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1671284 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Enables EIOS based on UPHY's rx_idle_status instead of P2U's EIOS
detection mechanism at Gen-1 speed to avoid unwanted DUT symbol
alignment with first COM symbol of EIOS

Bug 200397640

Change-Id: I30cf5441a6311701eb29de1ac1ce5d5f9c2055ff
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1671284
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
phy: tegra: pcie: Enale P2U intr based on DT prop 2018-02-13T16:36:57+00:00 Manikanta Maddireddy mmaddireddy@nvidia.com 2018-02-12T09:59:03+00:00 a4bc1ad60d1677cd28a726acbbdcc53b8632f38d One of the lane margining test requirements is to disable ASPM states. P2U registers are not accessible when link is in L1SS state. If driver enables P2U interrupts, P2U isr cannot read INT status when link is in L1SS. Enable P2U interrupts based on nvidia,enable-lm DT property to avoid this issue. Enable nvidia,enable-lm when lane margining test is planned. bug 200385039 Change-Id: I98b998799aac89809c8debaadbf5baeb27a0a657 Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1655840 Reviewed-by: Vidya Sagar <vidyas@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
One of the lane margining test requirements is to disable ASPM states.
P2U registers are not accessible when link is in L1SS state. If driver
enables P2U interrupts, P2U isr cannot read INT status when link is in L1SS.
Enable P2U interrupts based on nvidia,enable-lm DT property to avoid this
issue. Enable nvidia,enable-lm when lane margining test is planned.

bug 200385039

Change-Id: I98b998799aac89809c8debaadbf5baeb27a0a657
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1655840
Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
phy: tegra: pcie: Log invalid interrupt status 2018-02-13T16:36:53+00:00 Manikanta Maddireddy mmaddireddy@nvidia.com 2018-02-12T05:25:18+00:00 1d8e16b4f2df50af0bbf626e8d08d3e87fe84556 Log P2U interrupt status if interrupt is generated with invalid status. bug 200385039 Change-Id: I1b5aa0703792df3b4e41f144738a5c9358d533f1 Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1655648 Reviewed-by: Vidya Sagar <vidyas@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Log P2U interrupt status if interrupt is generated with invalid status.

bug 200385039

Change-Id: I1b5aa0703792df3b4e41f144738a5c9358d533f1
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1655648
Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
phy: tegra: pcie: program debounce timer value 2018-01-26T00:56:48+00:00 Vidya Sagar vidyas@nvidia.com 2018-01-24T11:07:51+00:00 5c150271a8027b4359805d3426a6f1a052a3c464 programs rx debounce timer value to 160 to avoid ASPM L1 entry issue Bug 200383205 Change-Id: Ia4561cf916c93cb2145a4d540fc65ec8474ac59a Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1645269 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
programs rx debounce timer value to 160 to avoid
ASPM L1 entry issue

Bug 200383205

Change-Id: Ia4561cf916c93cb2145a4d540fc65ec8474ac59a
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1645269
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Revert "phy: tegra: pcie: disable SLCG for P2U" 2018-01-26T00:56:32+00:00 Vidya Sagar vidyas@nvidia.com 2018-01-24T10:08:17+00:00 0d18e7fd27afb09a2e2a62f5d994348110a6e4ca This reverts commit 90afc4fd287cca5887e800dfbfb437a002828ee9. Bug 2042244 Change-Id: I9adb4e50c6e43d5c31531461d29d5ae048226c5e Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1645238 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
This reverts commit 90afc4fd287cca5887e800dfbfb437a002828ee9.

Bug 2042244

Change-Id: I9adb4e50c6e43d5c31531461d29d5ae048226c5e
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1645238
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
phy: tegra: pcie: support for Rx lane margining 2018-01-24T08:49:27+00:00 Vidya Sagar vidyas@nvidia.com 2017-11-26T15:19:12+00:00 dc1d26235dfc17e239703da130b1ac69c0fc339a Add support for Receiver lane margining required when link operates at Gen-4 speeds Bug 200366472 Change-Id: Ic4b5197bf6a596b321e1c7ca8a566840aff5489f Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1605095 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Add support for Receiver lane margining required when link
operates at Gen-4 speeds

Bug 200366472

Change-Id: Ic4b5197bf6a596b321e1c7ca8a566840aff5489f
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1605095
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
phy: tegra: pcie: disable SLCG for P2U 2017-12-05T17:13:16+00:00 Vidya Sagar vidyas@nvidia.com 2017-12-01T20:26:10+00:00 90afc4fd287cca5887e800dfbfb437a002828ee9 Disables SLCG for P2U module for initial bringup bug 200369845 Change-Id: I53e9488a1c276046770ccb3e0599cae89d02be5d Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1609992 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> 
Disables SLCG for P2U module for initial bringup

bug 200369845

Change-Id: I53e9488a1c276046770ccb3e0599cae89d02be5d
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1609992
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>