nvidia-tegra-modules.git/drivers/nvlink, branch gpu-paging NVIDIA's kernel modules to support tegra chips (used in Jetson boards) nvlink: Add read op to t19x endpt device node 2018-09-26T06:04:12+00:00 Petlozu Pravareshwar petlozup@nvidia.com 2018-08-31T12:22:59+00:00 760ef4c6a5ecd11fc43ba65ca3667d1763dac800 Nvlink android sanity test in kernel_submit tries to read t19x nvlink endpt device node and depends on its output to determine if nvlink init is successful or not. Currently we don't have any read operation handle for this device node and so read would always fail eventhough nvlink init is successful. This change fixes the above issue and adds read operation handle to the device node. Bug 2133882 Change-Id: I32a20c31b87f9e2f5f0d6d4a1b907afb3c22acd8 Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1810648 Reviewed-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Nvlink android sanity test in kernel_submit tries to read t19x nvlink
endpt device node and depends on its output to determine if nvlink
init is successful or not. Currently we don't have any read operation
handle for this device node and so read would always fail eventhough
nvlink init is successful.

This change fixes the above issue and adds read operation handle to
the device node.

Bug 2133882

Change-Id: I32a20c31b87f9e2f5f0d6d4a1b907afb3c22acd8
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1810648
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
nvlink: Clear warm reset persistent HW state 2018-09-24T07:25:12+00:00 Petlozu Pravareshwar petlozup@nvidia.com 2018-09-17T09:03:42+00:00 30aafb528ebaa8a6b8f9e4a6bf949f5d6acb6d75 As per Nvlink Wrapper IAS guidelines DEBUG_RESET[COMMON] bit should be first cleared to 0 and then only be set to 1. This is required to clear non-link specific(common) warm reset persistent HW state. Currently we are not clearing the above bit to 0 and this change will fix the issue. Bug 200449138 Bug 200449135 Change-Id: If235bc6343be0fde32e59390cc85647c8d70d670 Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1827939 Reviewed-by: Tejal Kudav <tkudav@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
As per Nvlink Wrapper IAS guidelines DEBUG_RESET[COMMON] bit should be
first cleared to 0 and then only be set to 1. This is required to clear
non-link specific(common) warm reset persistent HW state.

Currently we are not clearing the above bit to 0 and this change will
fix the issue.

Bug 200449138
Bug 200449135

Change-Id: If235bc6343be0fde32e59390cc85647c8d70d670
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1827939
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
nvlink: Enable logging, error reporting for SYNC2x 2018-09-19T05:43:33+00:00 Petlozu Pravareshwar petlozup@nvidia.com 2018-06-26T09:48:43+00:00 ef9c8d6a80d2606ebd70602998a566f3e030c331 Enable logging and error reporting for SYNC2X detected errors (Parity and ECC) on the NVLW-MSS interface. ECC errors are separated into single bit errors which are correctable with the ability to report when a programmed threshold is reached and multi-bit errors which are always fatal. Parity errors are always considered fatal. Each error type has an associated log enable, a reporting enable and a containment enable. This change sets each of these for fatal errors and sets the log and report enables (but not the contain enable) for correctable errors. Bug 200389331 Change-Id: Ia4aa52dbf1b6c3789da2890523ca25c1f7098b69 Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1761553 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Abhishek Sahu <absahu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Enable logging and error reporting for SYNC2X detected errors (Parity
and ECC) on the NVLW-MSS interface. ECC errors are separated into single
bit errors which are correctable with the ability to report when a
programmed threshold is reached and multi-bit errors which are always
fatal. Parity errors are always considered fatal.

Each error type has an associated log enable, a reporting enable and
a containment enable. This change sets each of these for fatal errors
and sets the log and report enables (but not the contain enable) for
correctable errors.

Bug 200389331

Change-Id: Ia4aa52dbf1b6c3789da2890523ca25c1f7098b69
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1761553
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Abhishek Sahu <absahu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
nvlink: Remove CFG_CTL_CAL.EOM_DIS usage 2018-09-04T08:57:37+00:00 Tejal Kudav tkudav@nvidia.com 2018-09-04T04:36:44+00:00 1654b259e5ccad8fb11133631e3fa8373dc97814 CFG_CTL_CAL.EOM_DIS register field is deprecated and the PHY init sequence is updated to not use this bit. Remove the driver code touching this bit. Bug 2316090 Change-Id: I911f8bb15e10d6b84ae911b43c87fafeb1644533 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1812171 Reviewed-by: Petlozu Pravareshwar <petlozup@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
CFG_CTL_CAL.EOM_DIS register field is deprecated and the PHY init
sequence is updated to not use this bit. Remove the driver code
touching this bit.

Bug 2316090

Change-Id: I911f8bb15e10d6b84ae911b43c87fafeb1644533
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812171
Reviewed-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
nvlink: Disable 1/8th mode for all t19x topologies 2018-08-30T05:39:44+00:00 Petlozu Pravareshwar petlozup@nvidia.com 2018-08-23T08:27:29+00:00 bb273a3ce0cfdbec3ff447040a2982eff468eafa Disable single-lane(1/8th) mode for all the t19x nvlink topologies. Also make sure we enable single-lane mode on nvlink only when both of the devices connected on either side of the link supports single lane mode. Bug 2341788 Change-Id: I95eae827cc6a3b748dd91637cdef27509a840c87 Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1805191 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Disable single-lane(1/8th) mode for all the t19x nvlink topologies.
Also make sure we enable single-lane mode on nvlink only when
both of the devices connected on either side of the link supports
single lane mode.

Bug 2341788

Change-Id: I95eae827cc6a3b748dd91637cdef27509a840c87
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805191
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
nvlink: fix XAVIER_CALIBRATEPLL failed to complete 2018-08-27T13:22:41+00:00 Seema Khowala seemaj@nvidia.com 2018-08-23T03:37:15+00:00 beb3ce4b62e24e391699b12bfcc257aaab5909c9 master uphy reset should be de-asserted last and asserted first. -deassert uphy lanes -deassert uphy pll0 -deassert uphy Bug 2258148 Bug 2341788 JIRA NVLINK-180 Change-Id: I7c0f02dac468ab3c900e7cea8ea7bf2ff97d8f66 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1805086 Reviewed-by: Abhishek Sahu <absahu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
master uphy reset should be de-asserted last and asserted first.
-deassert uphy lanes
-deassert uphy pll0
-deassert uphy

Bug 2258148
Bug 2341788
JIRA NVLINK-180

Change-Id: I7c0f02dac468ab3c900e7cea8ea7bf2ff97d8f66
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805086
Reviewed-by: Abhishek Sahu <absahu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
nvlink: do not power ungate and gate nvl partition 2018-08-21T21:54:47+00:00 Seema Khowala seemaj@nvidia.com 2018-08-17T18:12:17+00:00 77ac7d3e328166feb8e8d67dccd3673c2c3cb29e Never powergate NVLINK with the intention to restart it later. Power gating should be done for platforms that do not use NVLINK. Bug 2258148 Bug 200433994 Change-Id: Ie4046bd3207a7a079404f503373b1d47b0186aac Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1802171 Reviewed-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-by: Petlozu Pravareshwar <petlozup@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sivaram Nair <sivaramn@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Never powergate NVLINK with the intention to restart it later.
Power gating should be done for platforms that do not use NVLINK.

Bug 2258148
Bug 200433994

Change-Id: Ie4046bd3207a7a079404f503373b1d47b0186aac
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1802171
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Petlozu Pravareshwar <petlozup@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
nvlink: t19x: read nvlink fuses and enable fuse clock 2018-08-09T06:27:05+00:00 Seema Khowala seemaj@nvidia.com 2018-07-20T18:32:47+00:00 b65109afbbdf20b12e07bf42d15dbd392986256a Read fuse_ip_disable_0 to check if nvlink ip is enabled or not. If nvlink ip is disabled in the chip, do not register tegra nvlink device. Dump ucode_minion_rev_0 and secure_minion_debug_dis_0 fuse values. Enable fuse clocks during early init and disable the same at the time of setting link to OFF state. This is required as a WAR for Bug 2301575. Without fuse clocks being ON, sfk request would cause h/w hang. Bug 2258148 Bug 2277570 Bug 200425800 Bug 2301575 Change-Id: Ibf34361ed07d51b24868f60225d59bc70b0a375a Signed-off-by: Seema Khowala <seemaj@nvidia.com> Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1777267 Tested-by: Sandarbh Jain <sanjain@nvidia.com> Reviewed-by: Petlozu Pravareshwar <petlozup@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Read fuse_ip_disable_0 to check if nvlink ip is enabled
or not. If nvlink ip is disabled in the chip, do not register
tegra nvlink device.
Dump ucode_minion_rev_0 and secure_minion_debug_dis_0 fuse
values.
Enable fuse clocks during early init and disable the same
at the time of setting link to OFF state. This is required as a
WAR for Bug 2301575. Without fuse clocks being ON, sfk
request would cause h/w hang.

Bug 2258148
Bug 2277570
Bug 200425800
Bug 2301575

Change-Id: Ibf34361ed07d51b24868f60225d59bc70b0a375a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1777267
Tested-by: Sandarbh Jain <sanjain@nvidia.com>
Reviewed-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
nvlink: Dump minion trace only in error case 2018-07-23T10:14:22+00:00 Tejal Kudav tkudav@nvidia.com 2018-07-03T07:33:55+00:00 06b33392df550508ddf9cee9a599e9ee8a6e8fff The minion_dump_pc_trace API call should be conditional and should be called only in case of failure. Move the API call within the if loop to print only in case of failure. Change-Id: I09455898a6635706dc8d7943f0c588d3c8461517 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1768902 Reviewed-by: Petlozu Pravareshwar <petlozup@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
The minion_dump_pc_trace API call should be conditional
and should be called only in case of failure. Move the
API call within the if loop to print only in case of
failure.

Change-Id: I09455898a6635706dc8d7943f0c588d3c8461517
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1768902
Reviewed-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
nvlink: t19x: Remove 25GBPS speed support 2018-07-19T07:06:32+00:00 Seema Khowala seemaj@nvidia.com 2018-07-10T20:29:14+00:00 6dc5939fc78a55caddc5bfca756ee0c2d35d3208 Based on A01 Silicon Characterization, we cannot meet Nvlink POR speeds of 25G across 100% bin and hence 25GBPS is defeatured. Bug 200425755 Bug 2083356 Change-Id: Ia2166370413571787040e57ade299e3c136f4d5e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1775462 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> 
Based on A01 Silicon Characterization, we cannot meet Nvlink POR speeds
of 25G across 100% bin and hence 25GBPS is defeatured.

Bug 200425755
Bug 2083356

Change-Id: Ia2166370413571787040e57ade299e3c136f4d5e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1775462
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>