<feed xmlns='http://www.w3.org/2005/Atom'>
<title>nvidia-tegra-modules.git/Documentation, branch rtss22-ae</title>
<subtitle>NVIDIA's kernel modules to support tegra chips (used in Jetson boards)</subtitle>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/'/>
<entry>
<title>EQOS: Enable DMA selection with filtering.</title>
<updated>2021-08-13T20:11:13+00:00</updated>
<author>
<name>Achal Verma</name>
<email>achalv@nvidia.com</email>
</author>
<published>2021-06-25T07:57:41+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/commit/?id=a17fd4c3052cb2af717bc17d4451e6562a7a6ee4'/>
<id>a17fd4c3052cb2af717bc17d4451e6562a7a6ee4</id>
<content type='text'>
This change allows to configure filtering such that
specified  DMA channel is selected for packets which
match filtering criteria.

Bug 200743454

Change-Id: If990de0b499c36466258ce7f7cd79e1abe717537
Signed-off-by: Achal Verma &lt;achalv@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2575326
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Reviewed-by: svc-mobile-coverity &lt;svc-mobile-coverity@nvidia.com&gt;
Reviewed-by: Phoenix Jung &lt;pjung@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This change allows to configure filtering such that
specified  DMA channel is selected for packets which
match filtering criteria.

Bug 200743454

Change-Id: If990de0b499c36466258ce7f7cd79e1abe717537
Signed-off-by: Achal Verma &lt;achalv@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2575326
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Reviewed-by: svc-mobile-coverity &lt;svc-mobile-coverity@nvidia.com&gt;
Reviewed-by: Phoenix Jung &lt;pjung@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: PCI: tegra: Add slot supplies enable entry for EP mode</title>
<updated>2021-07-09T11:54:57+00:00</updated>
<author>
<name>Vidya Sagar</name>
<email>vidyas@nvidia.com</email>
</author>
<published>2021-07-07T10:44:17+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/commit/?id=38387300bbef0830e02299ffaaa6a8df4944f17a'/>
<id>38387300bbef0830e02299ffaaa6a8df4944f17a</id>
<content type='text'>
Add optional binding "nvidia,enable-slot-supplies" to instruct the platform
driver to enable the slot supplies even if the controller is operating in
the endpoint mode.

Bug 200614753

Change-Id: I5162c414a8bc81c1b76a3f8dfc956e9bef0de951
Signed-off-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2555250
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Reviewed-by: Bibek Basu &lt;bbasu@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add optional binding "nvidia,enable-slot-supplies" to instruct the platform
driver to enable the slot supplies even if the controller is operating in
the endpoint mode.

Bug 200614753

Change-Id: I5162c414a8bc81c1b76a3f8dfc956e9bef0de951
Signed-off-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2555250
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Reviewed-by: Bibek Basu &lt;bbasu@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: PCI: tegra: Add SRNS configuration entry</title>
<updated>2021-07-09T11:54:47+00:00</updated>
<author>
<name>Vidya Sagar</name>
<email>vidyas@nvidia.com</email>
</author>
<published>2021-07-06T15:57:45+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/commit/?id=208f1969795888b4095ebed7401f6eab88e5925e'/>
<id>208f1969795888b4095ebed7401f6eab88e5925e</id>
<content type='text'>
Add optional binding "nvidia,enable-srns" to describe a controller's
configuration in a platform that implements SRNS (Separate Reference
clocks with No Spread-spectrum clocking) scheme.

Bug 200614753

Change-Id: Icd10672c7a67b297d61d1b319505e7259f9f29a1
Signed-off-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2555161
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Reviewed-by: Bibek Basu &lt;bbasu@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add optional binding "nvidia,enable-srns" to describe a controller's
configuration in a platform that implements SRNS (Separate Reference
clocks with No Spread-spectrum clocking) scheme.

Bug 200614753

Change-Id: Icd10672c7a67b297d61d1b319505e7259f9f29a1
Signed-off-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2555161
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Reviewed-by: Bibek Basu &lt;bbasu@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
</pre>
</div>
</content>
</entry>
<entry>
<title>eqos: use phy reset low power mode from DT</title>
<updated>2021-05-13T01:43:36+00:00</updated>
<author>
<name>Sushil Singh</name>
<email>sushilkumars@nvidia.com</email>
</author>
<published>2020-11-18T10:15:53+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/commit/?id=38cd360781ca67b686829d8dd3d8023d0d7c13dc'/>
<id>38cd360781ca67b686829d8dd3d8023d0d7c13dc</id>
<content type='text'>
Issue:
Some ethernet PHY consume low power only when
they are put in reset mode otherwise power
consumption is high.

Fix:
Add DT flag which can be set for the PHYs which
consume low power when they are in reset. Driver
puts those phy chip to reset mode for low power
consumption state if the corresponding dt flag is
set, else use supported low power mode operation
for the selected phy. Default operation is to use
phy reset mode for low power consumption.

Bug 200627703

Change-Id: If86c37b43c8f737c332c46188ab2e91ae9c72343
Signed-off-by: Sushil Singh &lt;sushilkumars@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2447746
Reviewed-by: svcacv &lt;svcacv@nvidia.com&gt;
Reviewed-by: svc-mobile-coverity &lt;svc-mobile-coverity@nvidia.com&gt;
Reviewed-by: Bhadram Varka &lt;vbhadram@nvidia.com&gt;
Reviewed-by: Nagaraj Annaiah &lt;nannaiah@nvidia.com&gt;
Reviewed-by: Srinivas Ramachandran &lt;srinivasra@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
Tested-by: Aaron Tian &lt;atian@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Issue:
Some ethernet PHY consume low power only when
they are put in reset mode otherwise power
consumption is high.

Fix:
Add DT flag which can be set for the PHYs which
consume low power when they are in reset. Driver
puts those phy chip to reset mode for low power
consumption state if the corresponding dt flag is
set, else use supported low power mode operation
for the selected phy. Default operation is to use
phy reset mode for low power consumption.

Bug 200627703

Change-Id: If86c37b43c8f737c332c46188ab2e91ae9c72343
Signed-off-by: Sushil Singh &lt;sushilkumars@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2447746
Reviewed-by: svcacv &lt;svcacv@nvidia.com&gt;
Reviewed-by: svc-mobile-coverity &lt;svc-mobile-coverity@nvidia.com&gt;
Reviewed-by: Bhadram Varka &lt;vbhadram@nvidia.com&gt;
Reviewed-by: Nagaraj Annaiah &lt;nannaiah@nvidia.com&gt;
Reviewed-by: Srinivas Ramachandran &lt;srinivasra@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
Tested-by: Aaron Tian &lt;atian@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pwm: fan: Add support for always on fan</title>
<updated>2020-12-25T17:38:32+00:00</updated>
<author>
<name>Mantravadi Karthik</name>
<email>mkarthik@nvidia.com</email>
</author>
<published>2020-11-20T07:43:40+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/commit/?id=c3cd2b4417ea8767d35b4e04ba9731fb58a2a477'/>
<id>c3cd2b4417ea8767d35b4e04ba9731fb58a2a477</id>
<content type='text'>
Why?
In case of continuous governor, the fan-poweron pwm
value is assumed to be at index 1 of pwm values.
In case of tmargin the pwm table would be reversed
(high to low) and hence the assumption is invalid.

How?
While calculating the pwm value in the case of
continuous governor, add a check if the cooling device
is always on fan. If true, for all values of temp,
pwm should be calculated instead of assigning 0.

Bug 200646929

Change-Id: Ibed572fa2af9f8bd36a4a4cbb472029e21aeb442
Signed-off-by: Mantravadi Karthik &lt;mkarthik@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2448826
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Reviewed-by: svc-mobile-coverity &lt;svc-mobile-coverity@nvidia.com&gt;
Reviewed-by: Bibek Basu &lt;bbasu@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Why?
In case of continuous governor, the fan-poweron pwm
value is assumed to be at index 1 of pwm values.
In case of tmargin the pwm table would be reversed
(high to low) and hence the assumption is invalid.

How?
While calculating the pwm value in the case of
continuous governor, add a check if the cooling device
is always on fan. If true, for all values of temp,
pwm should be calculated instead of assigning 0.

Bug 200646929

Change-Id: Ibed572fa2af9f8bd36a4a4cbb472029e21aeb442
Signed-off-by: Mantravadi Karthik &lt;mkarthik@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2448826
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Reviewed-by: svc-mobile-coverity &lt;svc-mobile-coverity@nvidia.com&gt;
Reviewed-by: Bibek Basu &lt;bbasu@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
</pre>
</div>
</content>
</entry>
<entry>
<title>thermal: pwm-fan: Add support for tmargin</title>
<updated>2020-12-17T19:40:05+00:00</updated>
<author>
<name>Mantravadi Karthik</name>
<email>mkarthik@nvidia.com</email>
</author>
<published>2020-12-16T18:09:53+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/commit/?id=22fd87123c4a31566d621efd4ab007e481a0e937'/>
<id>22fd87123c4a31566d621efd4ab007e481a0e937</id>
<content type='text'>
Why?
Tmargin feature uses reverse pwm mapping in DT. The current
rru/rrd calculation logic assumes that the pwm table is in
ascending order. In the case of tmargin, the pwm table is
given in descending order.

How?
pwm fan dt node should have a "use_tmargin" identifier similar
to therm_fan_est dt node. This dt entry switches the logic in
rru/rrd calculation

Bug 200646929

Change-Id: I2042aaff5347553202212c6b69f707511bb9b7dd
Signed-off-by: Mantravadi Karthik &lt;mkarthik@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2460881
Tested-by: Rajkumar Kasirajan &lt;rkasirajan@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Reviewed-by: svc-mobile-coverity &lt;svc-mobile-coverity@nvidia.com&gt;
Reviewed-by: Rajkumar Kasirajan &lt;rkasirajan@nvidia.com&gt;
Reviewed-by: Bibek Basu &lt;bbasu@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Why?
Tmargin feature uses reverse pwm mapping in DT. The current
rru/rrd calculation logic assumes that the pwm table is in
ascending order. In the case of tmargin, the pwm table is
given in descending order.

How?
pwm fan dt node should have a "use_tmargin" identifier similar
to therm_fan_est dt node. This dt entry switches the logic in
rru/rrd calculation

Bug 200646929

Change-Id: I2042aaff5347553202212c6b69f707511bb9b7dd
Signed-off-by: Mantravadi Karthik &lt;mkarthik@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2460881
Tested-by: Rajkumar Kasirajan &lt;rkasirajan@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Reviewed-by: svc-mobile-coverity &lt;svc-mobile-coverity@nvidia.com&gt;
Reviewed-by: Rajkumar Kasirajan &lt;rkasirajan@nvidia.com&gt;
Reviewed-by: Bibek Basu &lt;bbasu@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
</pre>
</div>
</content>
</entry>
<entry>
<title>therm-fan-est: Add support for Tmargin to drive fan</title>
<updated>2020-09-15T15:39:29+00:00</updated>
<author>
<name>mkarthik</name>
<email>mkarthik@nvidia.com</email>
</author>
<published>2020-06-17T12:01:11+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/commit/?id=f9d1658833bbd2dfd5b24bb8cfff4da88db658ce'/>
<id>f9d1658833bbd2dfd5b24bb8cfff4da88db658ce</id>
<content type='text'>
Why?
Tmargin method of fan control allows multiple groups of
therma-fan-est devices temperatures to be considered for
the fan control algorithm/fan curve. The limitation of the
existing max temp algorithm in therm-fan-est driver is that
devices with different fan curves cannot be accomodated in
the driver. In case, there are multple fan curves, the device
which has the steepest curve wins the algoritm. Hence, taking
the temperatures as a reference from their respective critical
temperatures and using that value to drive the fan will help in
accomodating both the devices' fan curves.

How?
* Calculate the effective crit temp of all the thermal zones
  during probe.
* In the polling cycles, calculate the effective temperatures
  of the individual groups and use the tmargin formula to
  calculate the current temperature.
* Since the Tmargin temp trip values are in reverse order, we
  need to use the reverse order in the pwm-fan dt profile.
* The hysterysis is subtracted from the temp in cooling scenario
  to avoid frequent switching at trip temps. Since the tmargin
  trip values are taken in the decending order, hysterysis temps
  in dt should be given as negative values.

Bug 200627962

Change-Id: Ideba4bfdb3d3306d1b4aff15093bcfac13d7bb86
Signed-off-by: Mantravadi Karthik &lt;mkarthik@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2362354
Reviewed-by: automaticguardword &lt;automaticguardword@nvidia.com&gt;
Reviewed-by: Rajkumar Kasirajan &lt;rkasirajan@nvidia.com&gt;
Reviewed-by: Bibek Basu &lt;bbasu@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Tested-by: Rajkumar Kasirajan &lt;rkasirajan@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Why?
Tmargin method of fan control allows multiple groups of
therma-fan-est devices temperatures to be considered for
the fan control algorithm/fan curve. The limitation of the
existing max temp algorithm in therm-fan-est driver is that
devices with different fan curves cannot be accomodated in
the driver. In case, there are multple fan curves, the device
which has the steepest curve wins the algoritm. Hence, taking
the temperatures as a reference from their respective critical
temperatures and using that value to drive the fan will help in
accomodating both the devices' fan curves.

How?
* Calculate the effective crit temp of all the thermal zones
  during probe.
* In the polling cycles, calculate the effective temperatures
  of the individual groups and use the tmargin formula to
  calculate the current temperature.
* Since the Tmargin temp trip values are in reverse order, we
  need to use the reverse order in the pwm-fan dt profile.
* The hysterysis is subtracted from the temp in cooling scenario
  to avoid frequent switching at trip temps. Since the tmargin
  trip values are taken in the decending order, hysterysis temps
  in dt should be given as negative values.

Bug 200627962

Change-Id: Ideba4bfdb3d3306d1b4aff15093bcfac13d7bb86
Signed-off-by: Mantravadi Karthik &lt;mkarthik@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2362354
Reviewed-by: automaticguardword &lt;automaticguardword@nvidia.com&gt;
Reviewed-by: Rajkumar Kasirajan &lt;rkasirajan@nvidia.com&gt;
Reviewed-by: Bibek Basu &lt;bbasu@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Tested-by: Rajkumar Kasirajan &lt;rkasirajan@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
</pre>
</div>
</content>
</entry>
<entry>
<title>thermal: pwm-fan: Add tach feedback support</title>
<updated>2020-09-02T13:24:37+00:00</updated>
<author>
<name>mkarthik</name>
<email>mkarthik@nvidia.com</email>
</author>
<published>2020-07-01T13:26:10+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/commit/?id=d489e9eab5e854ca996753f7fe314f1337e1308c'/>
<id>d489e9eab5e854ca996753f7fe314f1337e1308c</id>
<content type='text'>
Why?
The current implementation of the pwm-fan driver only writes
a pwm value to the HW when requested. There is no tachometer
rpm read back to check if the thermal performance is as
expected. This change aims to add the rpm offsets necessary
to maintain the desired fan rpm.

How?
A new work queue is added which gets the pwm fan rpm and checks
the same for a rpm diff tolerance value. In case the tolerance
value is exceeded, the next pwm corresponding to the next rpm
ramp index is written to the pwm controller.

Bug 200646929

Change-Id: Iff780a7edf98ca457ace10079149925adf06189d
Signed-off-by: Mantravadi Karthik &lt;mkarthik@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2369412
Tested-by: Rajkumar Kasirajan &lt;rkasirajan@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Reviewed-by: Rajkumar Kasirajan &lt;rkasirajan@nvidia.com&gt;
Reviewed-by: Bibek Basu &lt;bbasu@nvidia.com&gt;
Reviewed-by: Sandipan Patra &lt;spatra@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Why?
The current implementation of the pwm-fan driver only writes
a pwm value to the HW when requested. There is no tachometer
rpm read back to check if the thermal performance is as
expected. This change aims to add the rpm offsets necessary
to maintain the desired fan rpm.

How?
A new work queue is added which gets the pwm fan rpm and checks
the same for a rpm diff tolerance value. In case the tolerance
value is exceeded, the next pwm corresponding to the next rpm
ramp index is written to the pwm controller.

Bug 200646929

Change-Id: Iff780a7edf98ca457ace10079149925adf06189d
Signed-off-by: Mantravadi Karthik &lt;mkarthik@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2369412
Tested-by: Rajkumar Kasirajan &lt;rkasirajan@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Reviewed-by: Rajkumar Kasirajan &lt;rkasirajan@nvidia.com&gt;
Reviewed-by: Bibek Basu &lt;bbasu@nvidia.com&gt;
Reviewed-by: Sandipan Patra &lt;spatra@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
</pre>
</div>
</content>
</entry>
<entry>
<title>thermal: fix cpu throttling for floorswept parts</title>
<updated>2020-08-10T08:23:35+00:00</updated>
<author>
<name>Srikar Srimath Tirumala</name>
<email>srikars@nvidia.com</email>
</author>
<published>2020-07-22T19:00:43+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/commit/?id=4b76b55c2ff611cf555d636910dbeed6010f33fa'/>
<id>4b76b55c2ff611cf555d636910dbeed6010f33fa</id>
<content type='text'>
Make CPU throttling use cpufreq policy instead of querying the CCF.
As CPU clocks are not supported by CCF on T194, querying max and min
CPU frequencies from CCF is not guaranteed to work. Secondly, clocks
for floorswept CPUs are not available and this results in a pesky
warning about failing to get a clock. While it is not required to
get all the CPU clocks for throttling to work, the first reason
requires a change. Fix this by using the values stored in the policy
struct instead. Also defer the registration of the cooling devices if
cpufreq has not already been registered.

Update the binding doc to reflect this change and clarify per CPU
throttling is not supported.

Bug 2928679

Change-Id: I71c5c9b58e1f01550cbe088a5222b593114bcc54
Signed-off-by: Srikar Srimath Tirumala &lt;srikars@nvidia.com&gt;
(cherry picked from commit c6ebee8c2f723277b0966657867c9bb2104a7acb)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2393741
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Reviewed-by: automaticguardword &lt;automaticguardword@nvidia.com&gt;
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bibek Basu &lt;bbasu@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Make CPU throttling use cpufreq policy instead of querying the CCF.
As CPU clocks are not supported by CCF on T194, querying max and min
CPU frequencies from CCF is not guaranteed to work. Secondly, clocks
for floorswept CPUs are not available and this results in a pesky
warning about failing to get a clock. While it is not required to
get all the CPU clocks for throttling to work, the first reason
requires a change. Fix this by using the values stored in the policy
struct instead. Also defer the registration of the cooling devices if
cpufreq has not already been registered.

Update the binding doc to reflect this change and clarify per CPU
throttling is not supported.

Bug 2928679

Change-Id: I71c5c9b58e1f01550cbe088a5222b593114bcc54
Signed-off-by: Srikar Srimath Tirumala &lt;srikars@nvidia.com&gt;
(cherry picked from commit c6ebee8c2f723277b0966657867c9bb2104a7acb)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2393741
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Reviewed-by: automaticguardword &lt;automaticguardword@nvidia.com&gt;
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bibek Basu &lt;bbasu@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
</pre>
</div>
</content>
</entry>
<entry>
<title>eqos: put tegra pads to tristate at cable unplug</title>
<updated>2020-07-03T05:12:34+00:00</updated>
<author>
<name>Sushil Singh</name>
<email>sushilkumars@nvidia.com</email>
</author>
<published>2020-03-03T06:47:23+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/commit/?id=58751cd50107db52a9837edddd1ef76d807eecf8'/>
<id>58751cd50107db52a9837edddd1ef76d807eecf8</id>
<content type='text'>
Issue:
Power consumption was high even after LAN cable unplug.
The tegra padctl registers was not put to tristate(tx/rx both) after cable
unplug event

Fix:
Put tegra pads to tristate state for cable unplug event at PHY layer.

Bug 200536930

Change-Id: I80d1ec57f1f7aafedc431e06336a1942f2c52ed9
Signed-off-by: Sushil Singh &lt;sushilkumars@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2306241
Reviewed-by: automaticguardword &lt;automaticguardword@nvidia.com&gt;
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha &lt;ajha@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Issue:
Power consumption was high even after LAN cable unplug.
The tegra padctl registers was not put to tristate(tx/rx both) after cable
unplug event

Fix:
Put tegra pads to tristate state for cable unplug event at PHY layer.

Bug 200536930

Change-Id: I80d1ec57f1f7aafedc431e06336a1942f2c52ed9
Signed-off-by: Sushil Singh &lt;sushilkumars@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2306241
Reviewed-by: automaticguardword &lt;automaticguardword@nvidia.com&gt;
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha &lt;ajha@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
