<feed xmlns='http://www.w3.org/2005/Atom'>
<title>nvidia-tegra-modules.git/Documentation/devicetree/bindings/platform/tegra, branch rtss22-ae</title>
<subtitle>NVIDIA's kernel modules to support tegra chips (used in Jetson boards)</subtitle>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/'/>
<entry>
<title>eqos: use phy reset low power mode from DT</title>
<updated>2021-05-13T01:43:36+00:00</updated>
<author>
<name>Sushil Singh</name>
<email>sushilkumars@nvidia.com</email>
</author>
<published>2020-11-18T10:15:53+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/commit/?id=38cd360781ca67b686829d8dd3d8023d0d7c13dc'/>
<id>38cd360781ca67b686829d8dd3d8023d0d7c13dc</id>
<content type='text'>
Issue:
Some ethernet PHY consume low power only when
they are put in reset mode otherwise power
consumption is high.

Fix:
Add DT flag which can be set for the PHYs which
consume low power when they are in reset. Driver
puts those phy chip to reset mode for low power
consumption state if the corresponding dt flag is
set, else use supported low power mode operation
for the selected phy. Default operation is to use
phy reset mode for low power consumption.

Bug 200627703

Change-Id: If86c37b43c8f737c332c46188ab2e91ae9c72343
Signed-off-by: Sushil Singh &lt;sushilkumars@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2447746
Reviewed-by: svcacv &lt;svcacv@nvidia.com&gt;
Reviewed-by: svc-mobile-coverity &lt;svc-mobile-coverity@nvidia.com&gt;
Reviewed-by: Bhadram Varka &lt;vbhadram@nvidia.com&gt;
Reviewed-by: Nagaraj Annaiah &lt;nannaiah@nvidia.com&gt;
Reviewed-by: Srinivas Ramachandran &lt;srinivasra@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
Tested-by: Aaron Tian &lt;atian@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Issue:
Some ethernet PHY consume low power only when
they are put in reset mode otherwise power
consumption is high.

Fix:
Add DT flag which can be set for the PHYs which
consume low power when they are in reset. Driver
puts those phy chip to reset mode for low power
consumption state if the corresponding dt flag is
set, else use supported low power mode operation
for the selected phy. Default operation is to use
phy reset mode for low power consumption.

Bug 200627703

Change-Id: If86c37b43c8f737c332c46188ab2e91ae9c72343
Signed-off-by: Sushil Singh &lt;sushilkumars@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2447746
Reviewed-by: svcacv &lt;svcacv@nvidia.com&gt;
Reviewed-by: svc-mobile-coverity &lt;svc-mobile-coverity@nvidia.com&gt;
Reviewed-by: Bhadram Varka &lt;vbhadram@nvidia.com&gt;
Reviewed-by: Nagaraj Annaiah &lt;nannaiah@nvidia.com&gt;
Reviewed-by: Srinivas Ramachandran &lt;srinivasra@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
Tested-by: Aaron Tian &lt;atian@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>thermal: fix cpu throttling for floorswept parts</title>
<updated>2020-08-10T08:23:35+00:00</updated>
<author>
<name>Srikar Srimath Tirumala</name>
<email>srikars@nvidia.com</email>
</author>
<published>2020-07-22T19:00:43+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/commit/?id=4b76b55c2ff611cf555d636910dbeed6010f33fa'/>
<id>4b76b55c2ff611cf555d636910dbeed6010f33fa</id>
<content type='text'>
Make CPU throttling use cpufreq policy instead of querying the CCF.
As CPU clocks are not supported by CCF on T194, querying max and min
CPU frequencies from CCF is not guaranteed to work. Secondly, clocks
for floorswept CPUs are not available and this results in a pesky
warning about failing to get a clock. While it is not required to
get all the CPU clocks for throttling to work, the first reason
requires a change. Fix this by using the values stored in the policy
struct instead. Also defer the registration of the cooling devices if
cpufreq has not already been registered.

Update the binding doc to reflect this change and clarify per CPU
throttling is not supported.

Bug 2928679

Change-Id: I71c5c9b58e1f01550cbe088a5222b593114bcc54
Signed-off-by: Srikar Srimath Tirumala &lt;srikars@nvidia.com&gt;
(cherry picked from commit c6ebee8c2f723277b0966657867c9bb2104a7acb)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2393741
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Reviewed-by: automaticguardword &lt;automaticguardword@nvidia.com&gt;
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bibek Basu &lt;bbasu@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Make CPU throttling use cpufreq policy instead of querying the CCF.
As CPU clocks are not supported by CCF on T194, querying max and min
CPU frequencies from CCF is not guaranteed to work. Secondly, clocks
for floorswept CPUs are not available and this results in a pesky
warning about failing to get a clock. While it is not required to
get all the CPU clocks for throttling to work, the first reason
requires a change. Fix this by using the values stored in the policy
struct instead. Also defer the registration of the cooling devices if
cpufreq has not already been registered.

Update the binding doc to reflect this change and clarify per CPU
throttling is not supported.

Bug 2928679

Change-Id: I71c5c9b58e1f01550cbe088a5222b593114bcc54
Signed-off-by: Srikar Srimath Tirumala &lt;srikars@nvidia.com&gt;
(cherry picked from commit c6ebee8c2f723277b0966657867c9bb2104a7acb)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2393741
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Reviewed-by: automaticguardword &lt;automaticguardword@nvidia.com&gt;
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bibek Basu &lt;bbasu@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
</pre>
</div>
</content>
</entry>
<entry>
<title>eqos: put tegra pads to tristate at cable unplug</title>
<updated>2020-07-03T05:12:34+00:00</updated>
<author>
<name>Sushil Singh</name>
<email>sushilkumars@nvidia.com</email>
</author>
<published>2020-03-03T06:47:23+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/commit/?id=58751cd50107db52a9837edddd1ef76d807eecf8'/>
<id>58751cd50107db52a9837edddd1ef76d807eecf8</id>
<content type='text'>
Issue:
Power consumption was high even after LAN cable unplug.
The tegra padctl registers was not put to tristate(tx/rx both) after cable
unplug event

Fix:
Put tegra pads to tristate state for cable unplug event at PHY layer.

Bug 200536930

Change-Id: I80d1ec57f1f7aafedc431e06336a1942f2c52ed9
Signed-off-by: Sushil Singh &lt;sushilkumars@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2306241
Reviewed-by: automaticguardword &lt;automaticguardword@nvidia.com&gt;
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha &lt;ajha@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Issue:
Power consumption was high even after LAN cable unplug.
The tegra padctl registers was not put to tristate(tx/rx both) after cable
unplug event

Fix:
Put tegra pads to tristate state for cable unplug event at PHY layer.

Bug 200536930

Change-Id: I80d1ec57f1f7aafedc431e06336a1942f2c52ed9
Signed-off-by: Sushil Singh &lt;sushilkumars@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2306241
Reviewed-by: automaticguardword &lt;automaticguardword@nvidia.com&gt;
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha &lt;ajha@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: carmel PMU: add supported events, examples</title>
<updated>2020-02-28T15:41:40+00:00</updated>
<author>
<name>Rich Wiley</name>
<email>rwiley@nvidia.com</email>
</author>
<published>2019-12-11T16:48:56+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/commit/?id=00211a27a09795f7b255901025e85112ca14355e'/>
<id>00211a27a09795f7b255901025e85112ca14355e</id>
<content type='text'>
Bug 200498583

Change-Id: Ic6e67f2af290a3a5c3e9ecbc1ba1f5ec6cfda168
Signed-off-by: Rich Wiley &lt;rwiley@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2260342
Reviewed-by: Bo Yan &lt;byan@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
(cherry picked from commit fb0c6d815db7a880fa9265086e9aaf8959c6d376)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2301930
Tested-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Reviewed-by: Bibek Basu &lt;bbasu@nvidia.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Bug 200498583

Change-Id: Ic6e67f2af290a3a5c3e9ecbc1ba1f5ec6cfda168
Signed-off-by: Rich Wiley &lt;rwiley@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2260342
Reviewed-by: Bo Yan &lt;byan@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
(cherry picked from commit fb0c6d815db7a880fa9265086e9aaf8959c6d376)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2301930
Tested-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Reviewed-by: Bibek Basu &lt;bbasu@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: carmel PMU: add Carmel uncore PMU driver docs</title>
<updated>2019-11-29T20:40:58+00:00</updated>
<author>
<name>Rich Wiley</name>
<email>rwiley@nvidia.com</email>
</author>
<published>2019-11-26T21:42:15+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/commit/?id=05559ec95ad9491f989dd15911f946bc9776bb55'/>
<id>05559ec95ad9491f989dd15911f946bc9776bb55</id>
<content type='text'>
bug 2622963

Change-Id: I436a86d887bcc570acb36b8536d3f42a232423a7
Signed-off-by: Rich Wiley &lt;rwiley@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/2248223
Reviewed-by: Bo Yan &lt;byan@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
(cherry picked from commit c7c18a5d72142e78264ab36b19d218ccbdde791e)
Reviewed-on: https://git-master.nvidia.com/r/2251016
Tested-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Reviewed-by: Bibek Basu &lt;bbasu@nvidia.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
bug 2622963

Change-Id: I436a86d887bcc570acb36b8536d3f42a232423a7
Signed-off-by: Rich Wiley &lt;rwiley@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/2248223
Reviewed-by: Bo Yan &lt;byan@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
(cherry picked from commit c7c18a5d72142e78264ab36b19d218ccbdde791e)
Reviewed-on: https://git-master.nvidia.com/r/2251016
Tested-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Reviewed-by: Bibek Basu &lt;bbasu@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: eqos: update EQOS DT bindings</title>
<updated>2018-09-11T12:21:45+00:00</updated>
<author>
<name>Bhadram Varka</name>
<email>vbhadram@nvidia.com</email>
</author>
<published>2018-08-29T05:40:52+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/commit/?id=9dd7444f99790fc716968ab06ef7e77ade490709'/>
<id>9dd7444f99790fc716968ab06ef7e77ade490709</id>
<content type='text'>
Bug 200432954

Change-Id: I848ce0e1462433bb2d487bdae14d64b0f48361e1
Signed-off-by: Bhadram Varka &lt;vbhadram@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/1808851
Reviewed-by: Narayan Reddy &lt;narayanr@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam &lt;snikam@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Bug 200432954

Change-Id: I848ce0e1462433bb2d487bdae14d64b0f48361e1
Signed-off-by: Bhadram Varka &lt;vbhadram@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/1808851
Reviewed-by: Narayan Reddy &lt;narayanr@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam &lt;snikam@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>tegra: eqos: update EQOS DT bindings</title>
<updated>2018-08-28T04:45:14+00:00</updated>
<author>
<name>Poojan Shah</name>
<email>poojans@nvidia.com</email>
</author>
<published>2018-08-27T20:20:28+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/commit/?id=5fc742cd01013e801c90fd834c49cfbdebf53f7c'/>
<id>5fc742cd01013e801c90fd834c49cfbdebf53f7c</id>
<content type='text'>
Add binding for nvidia,rx_riwt property.

This property is used to define the number of usec to wait before
triggering an Rx interrupt. The field is used to program the RIWT
field in the ethernet controller.

ESQC-3325

Change-Id: If076125f26d18fb36361fd3fb11b299df7bcaa7b
Signed-off-by: Poojan Shah &lt;poojans@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/1807684
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam &lt;snikam@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add binding for nvidia,rx_riwt property.

This property is used to define the number of usec to wait before
triggering an Rx interrupt. The field is used to program the RIWT
field in the ethernet controller.

ESQC-3325

Change-Id: If076125f26d18fb36361fd3fb11b299df7bcaa7b
Signed-off-by: Poojan Shah &lt;poojans@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/1807684
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam &lt;snikam@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>thermal: throttle: fix for floorswept platforms</title>
<updated>2018-07-05T23:53:03+00:00</updated>
<author>
<name>Srikar Srimath Tirumala</name>
<email>srikars@nvidia.com</email>
</author>
<published>2018-06-28T19:27:52+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/commit/?id=a4051c12dc8b22cc0ee05c1a1f14c8f7665b68fa'/>
<id>a4051c12dc8b22cc0ee05c1a1f14c8f7665b68fa</id>
<content type='text'>
Pass the clock handles for all the CPU clusters instead of just the
one cluster from DT. The NAFLLL CLUSTER clock id refers to the
physical cluster and is not guaranteed to be present on floorswept
configurations.

Add logic to look for the appropriate clock handle from a list of
clock handles and fail the driver registration if a missing clock
is referenced in the cooling device.

Bug 2224577

Change-Id: I36a7d308eaa573c6b99390e3fbf36a3828377494
Signed-off-by: Srikar Srimath Tirumala &lt;srikars@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/1764644
Reviewed-by: Aleksandr Frid &lt;afrid@nvidia.com&gt;
Reviewed-by: svc-mobile-coverity &lt;svc-mobile-coverity@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan &lt;byan@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Pass the clock handles for all the CPU clusters instead of just the
one cluster from DT. The NAFLLL CLUSTER clock id refers to the
physical cluster and is not guaranteed to be present on floorswept
configurations.

Add logic to look for the appropriate clock handle from a list of
clock handles and fail the driver registration if a missing clock
is referenced in the cooling device.

Bug 2224577

Change-Id: I36a7d308eaa573c6b99390e3fbf36a3828377494
Signed-off-by: Srikar Srimath Tirumala &lt;srikars@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/1764644
Reviewed-by: Aleksandr Frid &lt;afrid@nvidia.com&gt;
Reviewed-by: svc-mobile-coverity &lt;svc-mobile-coverity@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan &lt;byan@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>tegra: tegra: add support for CV NOC errors</title>
<updated>2018-06-26T23:33:15+00:00</updated>
<author>
<name>Sumit Gupta</name>
<email>sumitg@nvidia.com</email>
</author>
<published>2018-03-19T19:03:07+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/commit/?id=8835b72ded37eb90a779b89f931eb69aaa21add3'/>
<id>8835b72ded37eb90a779b89f931eb69aaa21add3</id>
<content type='text'>
adding support to handle errors from CV NOC.
Enabling clock and using PROBE_DEFER for NOC's
which are not probed yet e.g: CV-NOC here as it
depends on cvnas driver which gets probed later.

Bug 200340783
Bug 200389874

Change-Id: I2608aff0956a67f15426773c6ae0d471e5f645eb
Signed-off-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/1678123
Reviewed-by: svc-mobile-coverity &lt;svc-mobile-coverity@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt &lt;avanbrunt@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
adding support to handle errors from CV NOC.
Enabling clock and using PROBE_DEFER for NOC's
which are not probed yet e.g: CV-NOC here as it
depends on cvnas driver which gets probed later.

Bug 200340783
Bug 200389874

Change-Id: I2608aff0956a67f15426773c6ae0d471e5f645eb
Signed-off-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/1678123
Reviewed-by: svc-mobile-coverity &lt;svc-mobile-coverity@nvidia.com&gt;
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt &lt;avanbrunt@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>tegra: t19x: correct compatible string for NOC's</title>
<updated>2018-05-30T12:32:56+00:00</updated>
<author>
<name>Sumit Gupta</name>
<email>sumitg@nvidia.com</email>
</author>
<published>2018-04-02T11:34:55+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/nvidia-tegra-modules.git/commit/?id=fa24a82867d9bab8cc5c9f942acb5a15063bb3ad'/>
<id>fa24a82867d9bab8cc5c9f942acb5a15063bb3ad</id>
<content type='text'>
Correcting compatible string name from bridge to NOC.
Also, adding is_ax2apb_bridge_connected flag to check if
the cluster is connected to CBB through any AXI2APB bridge.
Currently, AON cluster is only one which is not connected.
So, no need to read AXI2APB bridge registers for that NOC.

Bug 200340783

Change-Id: Iea89b6a3daff1dd30b6d43a9e8254ed362a841d0
Signed-off-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/1686705
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu &lt;bbasu@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Correcting compatible string name from bridge to NOC.
Also, adding is_ax2apb_bridge_connected flag to check if
the cluster is connected to CBB through any AXI2APB bridge.
Currently, AON cluster is only one which is not connected.
So, no need to read AXI2APB bridge registers for that NOC.

Bug 200340783

Change-Id: Iea89b6a3daff1dd30b6d43a9e8254ed362a841d0
Signed-off-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Reviewed-on: https://git-master.nvidia.com/r/1686705
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu &lt;bbasu@nvidia.com&gt;
Reviewed-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
Tested-by: mobile promotions &lt;svcmobile_promotions@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
