nvidia-tegra-modules.git/Documentation/devicetree/bindings/cpufreq, branch gpu-paging NVIDIA's kernel modules to support tegra chips (used in Jetson boards) tegra: cpufreq: add tegra cpufreq dt node 2018-06-21T09:33:27+00:00 Puneet Saxena puneets@nvidia.com 2016-09-28T04:58:42+00:00 c71fb07113036f42ea860b5bce15f8c06c051b2b Bug 200234807 Change-Id: I7ca1f2cc5141b0bdeb5eac35a56a7723f377c8c4 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: http://git-master/r/1228156 (cherry picked from commit c0a737ca7a3ece2559eefc59371ffa6323d7ae93) Reviewed-on: https://git-master.nvidia.com/r/1527971 Reviewed-on: https://git-master.nvidia.com/r/1754143 Reviewed-by: Timo Alho <talho@nvidia.com> 
Bug 200234807

Change-Id: I7ca1f2cc5141b0bdeb5eac35a56a7723f377c8c4
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: http://git-master/r/1228156
(cherry picked from commit c0a737ca7a3ece2559eefc59371ffa6323d7ae93)
Reviewed-on: https://git-master.nvidia.com/r/1527971
Reviewed-on: https://git-master.nvidia.com/r/1754143
Reviewed-by: Timo Alho <talho@nvidia.com>
cpufreq: t18x: update cc3 node for adding freq 2016-09-07T08:43:37+00:00 Puneet Saxena puneets@nvidia.com 2016-08-23T05:20:20+00:00 87dc0fc7beb91878c4935cfe6cc1b69633906085 It updates "nvidia,enable-autocc3" property to enable/disable per cluster cc3. It adds another property "nvidia,autocc3-freq" to override per cluster cc3 freq. Bug 1801873 Change-Id: Ie81a247f61825d89e9717e4ce84acee138956a6b Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: http://git-master/r/1207457 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> 
It updates "nvidia,enable-autocc3" property to enable/disable
per cluster cc3.

It adds another property "nvidia,autocc3-freq" to override per
cluster cc3 freq.

Bug 1801873

Change-Id: Ie81a247f61825d89e9717e4ce84acee138956a6b
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: http://git-master/r/1207457
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
cpufreq: t18x: add property for auto cc3 2016-02-03T04:53:03+00:00 Puneet Saxena puneets@nvidia.com 2015-10-26T16:08:09+00:00 cc482e640eed64b960e3e7c19fff586a2e2fce3c Add auto cc3 property in cpufreq node. If auto cc3 property exists, auto cc3 mode will be enabled in cpu AVFS. Bug 200144999 Change-Id: I38317a34fc439824e9df41cc7ca736f221cfa129 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: http://git-master/r/823185 (cherry picked from commit 2999a47061fa3d17bd6875be0b72ea7dcad9948a) Reviewed-on: http://git-master/r/922487 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> 
Add auto cc3 property in cpufreq node.
If auto cc3 property exists, auto cc3 mode
will be enabled in cpu AVFS.

Bug 200144999

Change-Id: I38317a34fc439824e9df41cc7ca736f221cfa129
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: http://git-master/r/823185
(cherry picked from commit 2999a47061fa3d17bd6875be0b72ea7dcad9948a)
Reviewed-on: http://git-master/r/922487
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
arm64: dt: t186: Add cpu freq_table_step_size 2015-12-30T04:34:21+00:00 sreenivasulu velpula svelpula@nvidia.com 2015-12-22T06:44:50+00:00 f6570e255c8251eb0984ecc309f64fdefa435638 initialize freq table step size as 1 to make more number of freq steps available. Bug 200149085 Change-Id: Iddc632c16e94f4a7ffdb5b2001a12c8bce6d6c13 Signed-off-by: sreenivasulu velpula <svelpula@nvidia.com> Reviewed-on: http://git-master/r/925490 (cherry picked from commit ca28bea05b1b654767446c390e8394d7444ad986) Reviewed-on: http://git-master/r/925993 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Puneet Saxena <puneets@nvidia.com> Reviewed-by: Sandeep Trasi <strasi@nvidia.com> 
initialize freq table step size as 1 to make
more number of freq steps available.

Bug 200149085

Change-Id: Iddc632c16e94f4a7ffdb5b2001a12c8bce6d6c13
Signed-off-by: sreenivasulu velpula <svelpula@nvidia.com>
Reviewed-on: http://git-master/r/925490
(cherry picked from commit ca28bea05b1b654767446c390e8394d7444ad986)
Reviewed-on: http://git-master/r/925993
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
t186: dts: cluster_clk: add other clks 2015-11-24T09:12:18+00:00 Puneet Saxena puneets@nvidia.com 2015-11-18T06:54:20+00:00 b850b3ece0426e86137379755b070214c3731496 Extends below clocks MMCRAB mapping. sys_clock b_cluster_clk_priv b_cluster_clk_pub m_cluster_clk_priv m_cluster_clk_pub Bug 200144999 Change-Id: Iecdef1b22383c4b87479ec9987e3a68d28a27629 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: http://git-master/r/825891 (cherry picked from commit 088af45dabb4233159a00ff8ab082e4406d29410) Reviewed-on: http://git-master/r/835175 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com> 
Extends below clocks MMCRAB mapping.
sys_clock
b_cluster_clk_priv
b_cluster_clk_pub
m_cluster_clk_priv
m_cluster_clk_pub

Bug 200144999

Change-Id: Iecdef1b22383c4b87479ec9987e3a68d28a27629
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: http://git-master/r/825891
(cherry picked from commit 088af45dabb4233159a00ff8ab082e4406d29410)
Reviewed-on: http://git-master/r/835175
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
arm64: dts: cpufreq: remove emc clk properties 2015-10-26T15:47:16+00:00 Puneet Saxena puneets@nvidia.com 2015-10-01T15:07:29+00:00 d7fa18ea4b6d9675a6333186f50a0fea0ddeffe5 It removes emc clk properties as cpufreq driver uses Bandwidth manager which takes care of setting floor, cap, ISO and other requests for emc shared clock Bug 1675053 Change-Id: Icbbcf3a185194431b087d8c641a74f2ec0f4b901 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: http://git-master/r/808094 (cherry picked from commit 0a271dd5d1867465c014b322f0ba853b008aaf12) Reviewed-on: http://git-master/r/822683 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> 
It removes emc clk properties as cpufreq driver
uses Bandwidth manager which takes care of setting
floor, cap, ISO and other requests for emc shared clock

Bug 1675053

Change-Id: Icbbcf3a185194431b087d8c641a74f2ec0f4b901
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: http://git-master/r/808094
(cherry picked from commit 0a271dd5d1867465c014b322f0ba853b008aaf12)
Reviewed-on: http://git-master/r/822683
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
arm64: tegra18x: add clocks in cpufreq device node 2015-08-20T06:04:35+00:00 Puneet Saxena puneets@nvidia.com 2015-08-13T09:59:45+00:00 2aee3c85900ee93167f0f0a5dd510a8eb9a6b9c7 It modifies cpufreq dt node as - - Make tegra18x-cpufreq as compatible property Existing EDVD device node looks more intrinsic. Making this as tegra18x-cpufreq as generic name to accept more properties in future. - Add "clocks" and "clock-name" property for accessing per cluster emc clock. Bug 200128677 Change-Id: I51be5531fd81d056f75f14a5450a59128458ff82 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: http://git-master/r/782969 Reviewed-by: Sachin Nikam <snikam@nvidia.com> 
It modifies cpufreq dt node as -
- Make tegra18x-cpufreq as compatible property
    Existing EDVD device node looks more intrinsic. Making
    this as tegra18x-cpufreq as generic name to accept more
    properties in future.
- Add "clocks"  and "clock-name" property for accessing per
  cluster emc clock.

Bug 200128677

Change-Id: I51be5531fd81d056f75f14a5450a59128458ff82
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: http://git-master/r/782969
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
tegra: dtsi: add device tree support for cpufreq 2015-07-29T09:19:12+00:00 Puneet Saxena puneets@nvidia.com 2015-07-21T08:44:39+00:00 02a571847d3b2ad2bee612b252553ff7183bec44 In T18x, cpu frequency is updated by writing freq and voltage hint in EDVD registers. Create "tegra18x-edvd" dt node to access per cluster EDVD MMIO space. Bug 200111452 Change-Id: Ieb7d11abd0a13965631a20832fcd7001567447b4 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: http://git-master/r/751481 Reviewed-by: Sachin Nikam <snikam@nvidia.com> 
In T18x, cpu frequency is updated by writing freq and voltage
hint in EDVD registers.

Create "tegra18x-edvd" dt node to access per cluster
EDVD MMIO space.

Bug 200111452

Change-Id: Ieb7d11abd0a13965631a20832fcd7001567447b4
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: http://git-master/r/751481
Reviewed-by: Sachin Nikam <snikam@nvidia.com>