1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
|
/*
* Tegra GPU Virtualization Interfaces to Server
*
* Copyright (c) 2014, NVIDIA Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __TEGRA_VGPU_H
#define __TEGRA_VGPU_H
enum {
TEGRA_VGPU_MODULE_GPU = 0,
};
enum {
TEGRA_VGPU_QUEUE_CMD = 2,
TEGRA_VGPU_QUEUE_INTR
};
enum {
TEGRA_VGPU_CMD_CONNECT = 0,
TEGRA_VGPU_CMD_DISCONNECT,
TEGRA_VGPU_CMD_ABORT,
TEGRA_VGPU_CMD_CHANNEL_ALLOC_HWCTX,
TEGRA_VGPU_CMD_CHANNEL_FREE_HWCTX,
TEGRA_VGPU_CMD_GET_ATTRIBUTE,
TEGRA_VGPU_CMD_MAP_BAR1,
TEGRA_VGPU_CMD_AS_ALLOC_SHARE,
TEGRA_VGPU_CMD_AS_BIND_SHARE,
TEGRA_VGPU_CMD_AS_FREE_SHARE,
TEGRA_VGPU_CMD_AS_MAP,
TEGRA_VGPU_CMD_AS_UNMAP,
TEGRA_VGPU_CMD_AS_INVALIDATE,
TEGRA_VGPU_CMD_CHANNEL_BIND,
TEGRA_VGPU_CMD_CHANNEL_UNBIND,
TEGRA_VGPU_CMD_CHANNEL_DISABLE,
TEGRA_VGPU_CMD_CHANNEL_PREEMPT,
TEGRA_VGPU_CMD_CHANNEL_SETUP_RAMFC,
TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_CTX,
TEGRA_VGPU_CMD_CHANNEL_FREE_GR_CTX,
TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_CTX,
TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_PATCH_CTX,
TEGRA_VGPU_CMD_CHANNEL_FREE_GR_PATCH_CTX,
TEGRA_VGPU_CMD_CHANNEL_MAP_GR_GLOBAL_CTX,
TEGRA_VGPU_CMD_CHANNEL_UNMAP_GR_GLOBAL_CTX,
TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_GLOBAL_CTX,
TEGRA_VGPU_CMD_CHANNEL_LOAD_GR_GOLDEN_CTX,
TEGRA_VGPU_CMD_CHANNEL_BIND_ZCULL,
TEGRA_VGPU_CMD_CACHE_MAINT,
TEGRA_VGPU_CMD_SUBMIT_RUNLIST,
TEGRA_VGPU_CMD_GET_ZCULL_INFO
};
struct tegra_vgpu_connect_params {
u32 module;
u64 handle;
};
struct tegra_vgpu_channel_hwctx_params {
u32 id;
u64 handle;
};
enum {
TEGRA_VGPU_ATTRIB_NUM_CHANNELS = 0,
TEGRA_VGPU_ATTRIB_GOLDEN_CTX_SIZE,
TEGRA_VGPU_ATTRIB_ZCULL_CTX_SIZE,
TEGRA_VGPU_ATTRIB_COMPTAG_LINES,
TEGRA_VGPU_ATTRIB_GPC_COUNT,
TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT,
TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT,
TEGRA_VGPU_ATTRIB_PMC_BOOT_0,
TEGRA_VGPU_ATTRIB_L2_SIZE,
TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH
};
struct tegra_vgpu_attrib_params {
u32 attrib;
u32 value;
};
struct tegra_vgpu_as_share_params {
u64 size;
u64 handle;
};
struct tegra_vgpu_as_bind_share_params {
u64 as_handle;
u64 chan_handle;
};
enum {
TEGRA_VGPU_MAP_PROT_NONE = 0,
TEGRA_VGPU_MAP_PROT_READ_ONLY,
TEGRA_VGPU_MAP_PROT_WRITE_ONLY
};
struct tegra_vgpu_as_map_params {
u64 handle;
u64 addr;
u64 gpu_va;
u64 size;
u8 pgsz_idx;
u8 iova;
u8 kind;
u8 cacheable;
u8 clear_ctags;
u8 prot;
u32 ctag_offset;
};
struct tegra_vgpu_as_invalidate_params {
u64 handle;
};
struct tegra_vgpu_channel_config_params {
u64 handle;
};
struct tegra_vgpu_ramfc_params {
u64 handle;
u64 gpfifo_va;
u32 num_entries;
u64 userd_addr;
u8 iova;
};
struct tegra_vgpu_gr_ctx_params {
u64 handle;
u64 gr_ctx_va;
u64 patch_ctx_va;
u64 cb_va;
u64 attr_va;
u64 page_pool_va;
u64 priv_access_map_va;
u32 class_num;
};
struct tegra_vgpu_zcull_bind_params {
u64 handle;
u64 zcull_va;
u32 mode;
};
enum {
TEGRA_VGPU_L2_MAINT_FLUSH = 0,
TEGRA_VGPU_L2_MAINT_INV,
TEGRA_VGPU_L2_MAINT_FLUSH_INV,
TEGRA_VGPU_FB_FLUSH
};
struct tegra_vgpu_cache_maint_params {
u8 op;
};
struct tegra_vgpu_runlist_params {
u8 runlist_id;
u32 num_entries;
};
struct tegra_vgpu_golden_ctx_params {
u32 size;
};
struct tegra_vgpu_zcull_info_params {
u32 width_align_pixels;
u32 height_align_pixels;
u32 pixel_squares_by_aliquots;
u32 aliquot_total;
u32 region_byte_multiplier;
u32 region_header_size;
u32 subregion_header_size;
u32 subregion_width_align_pixels;
u32 subregion_height_align_pixels;
u32 subregion_count;
};
struct tegra_vgpu_cmd_msg {
u32 cmd;
int ret;
u64 handle;
union {
struct tegra_vgpu_connect_params connect;
struct tegra_vgpu_channel_hwctx_params channel_hwctx;
struct tegra_vgpu_attrib_params attrib;
struct tegra_vgpu_as_share_params as_share;
struct tegra_vgpu_as_bind_share_params as_bind_share;
struct tegra_vgpu_as_map_params as_map;
struct tegra_vgpu_as_invalidate_params as_invalidate;
struct tegra_vgpu_channel_config_params channel_config;
struct tegra_vgpu_ramfc_params ramfc;
struct tegra_vgpu_gr_ctx_params gr_ctx;
struct tegra_vgpu_zcull_bind_params zcull_bind;
struct tegra_vgpu_cache_maint_params cache_maint;
struct tegra_vgpu_runlist_params runlist;
struct tegra_vgpu_golden_ctx_params golden_ctx;
struct tegra_vgpu_zcull_info_params zcull_info;
} params;
};
enum {
TEGRA_VGPU_GR_INTR_NOTIFY = 0
};
struct tegra_vgpu_gr_intr_info {
u32 type;
u32 chid;
};
enum {
TEGRA_VGPU_INTR_GR = 0
};
enum {
TEGRA_VGPU_EVENT_INTR = 0,
TEGRA_VGPU_EVENT_ABORT
};
struct tegra_vgpu_intr_msg {
unsigned int event;
u32 unit;
union {
struct tegra_vgpu_gr_intr_info gr_intr;
} info;
};
#define TEGRA_VGPU_QUEUE_SIZES \
512, \
sizeof(struct tegra_vgpu_intr_msg)
#endif
|
