blob: 83f17937581c1ce6b1d8d7fa0b433fccd396af60 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
|
/*
* general p state infrastructure
*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include "gk20a/gk20a.h"
#include "clk/clk.h"
#include "perf/perf.h"
/*sw setup for pstate components*/
int gk20a_init_pstate_support(struct gk20a *g)
{
u32 err;
gk20a_dbg_fn("");
err = clk_vin_sw_setup(g);
if (err)
return err;
err = clk_fll_sw_setup(g);
if (err)
return err;
err = vfe_var_sw_setup(g);
if (err)
return err;
err = vfe_equ_sw_setup(g);
if (err)
return err;
err = clk_domain_sw_setup(g);
if (err)
return err;
err = clk_vf_point_sw_setup(g);
if (err)
return err;
err = clk_prog_sw_setup(g);
return err;
}
/*sw setup for pstate components*/
int gk20a_init_pstate_pmu_support(struct gk20a *g)
{
u32 err;
gk20a_dbg_fn("");
err = vfe_var_pmu_setup(g);
if (err)
return err;
err = vfe_equ_pmu_setup(g);
if (err)
return err;
err = clk_domain_pmu_setup(g);
if (err)
return err;
err = clk_prog_pmu_setup(g);
if (err)
return err;
err = clk_vin_pmu_setup(g);
if (err)
return err;
err = clk_fll_pmu_setup(g);
if (err)
return err;
err = clk_vf_point_pmu_setup(g);
if (err)
return err;
err = clk_pmu_vin_load(g);
if (err)
return err;
err = perf_pmu_vfe_load(g);
if (err)
return err;
err = clk_pmu_vf_inject(g);
return err;
}
|
