blob: 69d55490955040597efc4ea45be6a6f1d8c11d75 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
|
/*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _GPMUIFSEQ_H_
#define _GPMUIFSEQ_H_
#include "gk20a/pmu_common.h"
#define PMU_UNIT_SEQ (0x02)
/*!
* @file gpmuifseq.h
* @brief PMU Command/Message Interfaces - Sequencer
*/
/*!
* Defines the identifiers various high-level types of sequencer commands.
*
* _RUN_SCRIPT @ref NV_PMU_SEQ_CMD_RUN_SCRIPT
*/
enum {
NV_PMU_SEQ_CMD_ID_RUN_SCRIPT = 0,
};
struct nv_pmu_seq_cmd_run_script {
u8 cmd_type;
u8 pad[3];
struct pmu_allocation_v3 script_alloc;
struct pmu_allocation_v3 reg_alloc;
};
#define NV_PMU_SEQ_CMD_ALLOC_OFFSET 4
#define NV_PMU_SEQ_MSG_ALLOC_OFFSET \
(NV_PMU_SEQ_CMD_ALLOC_OFFSET + NV_PMU_CMD_ALLOC_SIZE)
struct nv_pmu_seq_cmd {
struct pmu_hdr hdr;
union {
u8 cmd_type;
struct nv_pmu_seq_cmd_run_script run_script;
};
};
enum {
NV_PMU_SEQ_MSG_ID_RUN_SCRIPT = 0,
};
struct nv_pmu_seq_msg_run_script {
u8 msg_type;
u8 error_code;
u16 error_pc;
u32 timeout_stat;
};
struct nv_pmu_seq_msg {
struct pmu_hdr hdr;
union {
u8 msg_type;
struct nv_pmu_seq_msg_run_script run_script;
};
};
#endif
|
