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/*
 * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __NVGPU_CHANNEL_H__
#define __NVGPU_CHANNEL_H__

#include <linux/workqueue.h>
#include <linux/dma-buf.h>

#include <nvgpu/types.h>

struct channel_gk20a;
struct nvgpu_gpfifo;
struct nvgpu_submit_gpfifo_args;
struct nvgpu_channel_fence;
struct gk20a_fence;
struct fifo_profile_gk20a;
struct nvgpu_os_linux;

struct sync_fence;
struct sync_timeline;

struct nvgpu_channel_completion_cb {
	/*
	 * Signal channel owner via a callback, if set, in job cleanup with
	 * schedule_work. Means that something finished on the channel (perhaps
	 * more than one job).
	 */
	void (*fn)(struct channel_gk20a *, void *);
	void *user_data;
	/* Make access to the two above atomic */
	struct nvgpu_spinlock lock;
	/* Per-channel async work task, cannot reschedule itself */
	struct work_struct work;
};

struct nvgpu_error_notifier {
	struct dma_buf *dmabuf;
	void *vaddr;

	struct nvgpu_notification *notification;

	struct nvgpu_mutex mutex;
};

/*
 * This struct contains fence_related data.
 * e.g. sync_timeline for sync_fences.
 */
struct nvgpu_os_fence_framework {
	struct sync_timeline *timeline;
};

struct nvgpu_channel_linux {
	struct channel_gk20a *ch;

	struct nvgpu_os_fence_framework fence_framework;

	struct nvgpu_channel_completion_cb completion_cb;
	struct nvgpu_error_notifier error_notifier;

	struct dma_buf *cyclestate_buffer_handler;
};

u32 nvgpu_submit_gpfifo_user_flags_to_common_flags(u32 user_flags);
int nvgpu_init_channel_support_linux(struct nvgpu_os_linux *l);
void nvgpu_remove_channel_support_linux(struct nvgpu_os_linux *l);

struct channel_gk20a *gk20a_open_new_channel_with_cb(struct gk20a *g,
		void (*update_fn)(struct channel_gk20a *, void *),
		void *update_fn_data,
		int runlist_id,
		bool is_privileged_channel);

#endif /* __NVGPU_CHANNEL_H__ */
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/*
 * drivers/video/tegra/host/gk20a/sim_gk20a.h
 *
 * GK20A sim support
 *
 * Copyright (c) 2013-2017, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */
#ifndef __SIM_GK20A_H__
#define __SIM_GK20A_H__

struct gk20a;

struct sim_gk20a {
	struct gk20a *g;
	u32 send_ring_put;
	u32 recv_ring_get;
	u32 recv_ring_put;
	u32 sequence_base;
	void (*remove_support)(struct sim_gk20a *);
	int (*esc_readl)(
		struct gk20a *g, char *path, u32 index, u32 *data);
};

#endif /*__SIM_GK20A_H__*/