1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
|
/*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/dma-mapping.h>
#include "gk20a/gk20a_scale.h"
#include "gk20a/gk20a.h"
#define EMC3D_DEFAULT_RATIO 750
static void nvgpu_init_vars(struct gk20a *g)
{
struct gk20a_platform *platform = dev_get_drvdata(g->dev);
init_waitqueue_head(&g->sw_irq_stall_last_handled_wq);
init_waitqueue_head(&g->sw_irq_nonstall_last_handled_wq);
gk20a_init_gr(g);
init_rwsem(&g->busy_lock);
spin_lock_init(&g->mc_enable_lock);
mutex_init(&platform->railgate_lock);
mutex_init(&g->dbg_sessions_lock);
mutex_init(&g->client_lock);
mutex_init(&g->ch_wdt_lock);
mutex_init(&g->poweroff_lock);
g->regs_saved = g->regs;
g->bar1_saved = g->bar1;
g->emc3d_ratio = EMC3D_DEFAULT_RATIO;
/* Set DMA parameters to allow larger sgt lists */
g->dev->dma_parms = &g->dma_parms;
dma_set_max_seg_size(g->dev, UINT_MAX);
}
static void nvgpu_init_timeout(struct gk20a *g)
{
g->gr_idle_timeout_default = CONFIG_GK20A_DEFAULT_TIMEOUT;
if (tegra_platform_is_silicon())
g->timeouts_enabled = true;
}
static void nvgpu_init_timeslice(struct gk20a *g)
{
g->runlist_interleave = true;
g->timeslice_low_priority_us = 1300;
g->timeslice_medium_priority_us = 2600;
g->timeslice_high_priority_us = 5200;
}
static void nvgpu_init_pm_vars(struct gk20a *g)
{
struct gk20a_platform *platform = dev_get_drvdata(g->dev);
/*
* Set up initial power settings. For non-slicon platforms, disable
* power features and for silicon platforms, read from platform data
*/
g->slcg_enabled =
tegra_platform_is_silicon() ? platform->enable_slcg : false;
g->blcg_enabled =
tegra_platform_is_silicon() ? platform->enable_blcg : false;
g->elcg_enabled =
tegra_platform_is_silicon() ? platform->enable_elcg : false;
g->elpg_enabled =
tegra_platform_is_silicon() ? platform->enable_elpg : false;
g->aelpg_enabled =
tegra_platform_is_silicon() ? platform->enable_aelpg : false;
/* set default values to aelpg parameters */
g->pmu.aelpg_param[0] = APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US;
g->pmu.aelpg_param[1] = APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US;
g->pmu.aelpg_param[2] = APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US;
g->pmu.aelpg_param[3] = APCTRL_POWER_BREAKEVEN_DEFAULT_US;
g->pmu.aelpg_param[4] = APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT;
}
static void nvgpu_init_mm_vars(struct gk20a *g)
{
struct gk20a_platform *platform = dev_get_drvdata(g->dev);
g->mm.bypass_smmu = platform->bypass_smmu;
g->mm.disable_bigpage = platform->disable_bigpage;
g->mm.vidmem_is_vidmem = platform->vidmem_is_vidmem;
}
int nvgpu_probe(struct gk20a *g,
const char *debugfs_symlink,
const char *interface_name,
struct class *class)
{
struct gk20a_platform *platform = dev_get_drvdata(g->dev);
int err = 0;
nvgpu_init_vars(g);
nvgpu_init_timeout(g);
nvgpu_init_timeslice(g);
nvgpu_init_pm_vars(g);
err = gk20a_user_init(g->dev, interface_name, class);
if (err)
return err;
/* Initialize the platform interface. */
err = platform->probe(g->dev);
if (err) {
dev_err(g->dev, "platform probe failed");
return err;
}
/* Initialise scaling */
if (IS_ENABLED(CONFIG_GK20A_DEVFREQ))
gk20a_scale_init(g->dev);
err = gk20a_secure_page_alloc(g->dev);
if (err)
dev_err(g->dev,
"failed to allocate secure buffer %d\n", err);
if (platform->late_probe) {
err = platform->late_probe(g->dev);
if (err) {
dev_err(g->dev, "late probe failed");
return err;
}
}
nvgpu_init_mm_vars(g);
gk20a_create_sysfs(g->dev);
gk20a_debug_init(g->dev, debugfs_symlink);
g->remove_support = gk20a_remove_support;
return 0;
}
|
