summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/include/nvgpu/ecc.h
blob: 9b211ef74227478c99b116fa669f4a9585b09b1f (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
/*
 * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#ifndef NVGPU_ECC_H
#define NVGPU_ECC_H

#include <nvgpu/types.h>
#include <nvgpu/list.h>

#define NVGPU_ECC_STAT_NAME_MAX_SIZE	100

struct gk20a;

struct nvgpu_ecc_stat {
	char name[NVGPU_ECC_STAT_NAME_MAX_SIZE];
	u32 counter;
	struct nvgpu_list_node node;
};

static inline struct nvgpu_ecc_stat *nvgpu_ecc_stat_from_node(
		struct nvgpu_list_node *node)
{
	return (struct nvgpu_ecc_stat *)(
			(uintptr_t)node - offsetof(struct nvgpu_ecc_stat, node)
		);
}

struct nvgpu_ecc {
	struct {
		/* stats per tpc */

		struct nvgpu_ecc_stat **sm_lrf_ecc_single_err_count;
		struct nvgpu_ecc_stat **sm_lrf_ecc_double_err_count;

		struct nvgpu_ecc_stat **sm_shm_ecc_sec_count;
		struct nvgpu_ecc_stat **sm_shm_ecc_sed_count;
		struct nvgpu_ecc_stat **sm_shm_ecc_ded_count;

		struct nvgpu_ecc_stat **tex_ecc_total_sec_pipe0_count;
		struct nvgpu_ecc_stat **tex_ecc_total_ded_pipe0_count;
		struct nvgpu_ecc_stat **tex_unique_ecc_sec_pipe0_count;
		struct nvgpu_ecc_stat **tex_unique_ecc_ded_pipe0_count;
		struct nvgpu_ecc_stat **tex_ecc_total_sec_pipe1_count;
		struct nvgpu_ecc_stat **tex_ecc_total_ded_pipe1_count;
		struct nvgpu_ecc_stat **tex_unique_ecc_sec_pipe1_count;
		struct nvgpu_ecc_stat **tex_unique_ecc_ded_pipe1_count;

		struct nvgpu_ecc_stat **sm_l1_tag_ecc_corrected_err_count;
		struct nvgpu_ecc_stat **sm_l1_tag_ecc_uncorrected_err_count;
		struct nvgpu_ecc_stat **sm_cbu_ecc_corrected_err_count;
		struct nvgpu_ecc_stat **sm_cbu_ecc_uncorrected_err_count;
		struct nvgpu_ecc_stat **sm_l1_data_ecc_corrected_err_count;
		struct nvgpu_ecc_stat **sm_l1_data_ecc_uncorrected_err_count;
		struct nvgpu_ecc_stat **sm_icache_ecc_corrected_err_count;
		struct nvgpu_ecc_stat **sm_icache_ecc_uncorrected_err_count;

		/* stats per gpc */

		struct nvgpu_ecc_stat *gcc_l15_ecc_corrected_err_count;
		struct nvgpu_ecc_stat *gcc_l15_ecc_uncorrected_err_count;

		struct nvgpu_ecc_stat *gpccs_ecc_corrected_err_count;
		struct nvgpu_ecc_stat *gpccs_ecc_uncorrected_err_count;
		struct nvgpu_ecc_stat *mmu_l1tlb_ecc_corrected_err_count;
		struct nvgpu_ecc_stat *mmu_l1tlb_ecc_uncorrected_err_count;

		/* stats per device */
		struct nvgpu_ecc_stat *fecs_ecc_corrected_err_count;
		struct nvgpu_ecc_stat *fecs_ecc_uncorrected_err_count;
	} gr;

	struct {
		/* stats per lts */
		struct nvgpu_ecc_stat **ecc_sec_count;
		struct nvgpu_ecc_stat **ecc_ded_count;
	} ltc;

	struct {
		/* stats per device */
		struct nvgpu_ecc_stat *mmu_l2tlb_ecc_corrected_err_count;
		struct nvgpu_ecc_stat *mmu_l2tlb_ecc_uncorrected_err_count;
		struct nvgpu_ecc_stat *mmu_hubtlb_ecc_corrected_err_count;
		struct nvgpu_ecc_stat *mmu_hubtlb_ecc_uncorrected_err_count;
		struct nvgpu_ecc_stat *mmu_fillunit_ecc_corrected_err_count;
		struct nvgpu_ecc_stat *mmu_fillunit_ecc_uncorrected_err_count;
	} fb;

	struct {
		/* stats per device */
		struct nvgpu_ecc_stat *pmu_ecc_corrected_err_count;
		struct nvgpu_ecc_stat *pmu_ecc_uncorrected_err_count;
	} pmu;

	struct {
		/* stats per fbpa */
		struct nvgpu_ecc_stat *fbpa_ecc_sec_err_count;
		struct nvgpu_ecc_stat *fbpa_ecc_ded_err_count;
	} fbpa;

	struct nvgpu_list_node stats_list;
	int stats_count;
};

int nvgpu_ecc_counter_init_per_tpc(struct gk20a *g,
		struct nvgpu_ecc_stat ***stat, const char *name);
#define NVGPU_ECC_COUNTER_INIT_PER_TPC(stat) \
	nvgpu_ecc_counter_init_per_tpc(g, &g->ecc.gr.stat, #stat)

int nvgpu_ecc_counter_init_per_gpc(struct gk20a *g,
		struct nvgpu_ecc_stat **stat, const char *name);
#define NVGPU_ECC_COUNTER_INIT_PER_GPC(stat) \
	nvgpu_ecc_counter_init_per_gpc(g, &g->ecc.gr.stat, #stat)

int nvgpu_ecc_counter_init(struct gk20a *g,
		struct nvgpu_ecc_stat **stat, const char *name);
#define NVGPU_ECC_COUNTER_INIT_GR(stat) \
	nvgpu_ecc_counter_init(g, &g->ecc.gr.stat, #stat)
#define NVGPU_ECC_COUNTER_INIT_FB(stat) \
	nvgpu_ecc_counter_init(g, &g->ecc.fb.stat, #stat)
#define NVGPU_ECC_COUNTER_INIT_PMU(stat) \
	nvgpu_ecc_counter_init(g, &g->ecc.pmu.stat, #stat)

int nvgpu_ecc_counter_init_per_lts(struct gk20a *g,
		struct nvgpu_ecc_stat ***stat, const char *name);
#define NVGPU_ECC_COUNTER_INIT_PER_LTS(stat) \
	nvgpu_ecc_counter_init_per_lts(g, &g->ecc.ltc.stat, #stat)

int nvgpu_ecc_counter_init_per_fbpa(struct gk20a *g,
		struct nvgpu_ecc_stat **stat, const char *name);
#define NVGPU_ECC_COUNTER_INIT_PER_FBPA(stat) \
	nvgpu_ecc_counter_init_per_fbpa(g, &g->ecc.fbpa.stat, #stat)

void nvgpu_ecc_free(struct gk20a *g);

int nvgpu_ecc_init_support(struct gk20a *g);
void nvgpu_ecc_remove_support(struct gk20a *g);

/* OSes to implement */

int nvgpu_ecc_sysfs_init(struct gk20a *g);
void nvgpu_ecc_sysfs_remove(struct gk20a *g);

#endif