1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
|
/*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef CLK_GP106_H
#define CLK_GP106_H
#include <nvgpu/lock.h>
#define CLK_NAMEMAP_INDEX_GPC2CLK 0x00
#define CLK_NAMEMAP_INDEX_XBAR2CLK 0x02
#define CLK_NAMEMAP_INDEX_SYS2CLK 0x07 /* SYSPLL */
#define CLK_NAMEMAP_INDEX_DRAMCLK 0x20 /* DRAMPLL */
#define CLK_DEFAULT_CNTRL_SETTLE_RETRIES 10
#define CLK_DEFAULT_CNTRL_SETTLE_USECS 5
#define XTAL_CNTR_CLKS 27000 /* 1000usec at 27KHz XTAL */
#define XTAL_CNTR_DELAY 1000 /* we need acuracy up to the ms */
#define XTAL_SCALE_TO_KHZ 1
struct namemap_cfg {
u32 namemap;
u32 is_enable; /* Namemap enabled */
u32 is_counter; /* Using cntr */
struct gk20a *g;
union {
struct {
u32 reg_ctrl_addr;
u32 reg_ctrl_idx;
u32 reg_cntr_addr;
} cntr;
struct {
/* Todo */
} pll;
};
u32 scale;
char name[24];
};
int gp106_init_clk_support(struct gk20a *g);
u32 gp106_crystal_clk_hz(struct gk20a *g);
unsigned long gp106_clk_measure_freq(struct gk20a *g, u32 api_domain);
int gp106_suspend_clk_support(struct gk20a *g);
#endif /* CLK_GP106_H */
|