/* * GV11B Tegra HAL interface * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. */ #include #include #include #include #include "gk20a/gk20a.h" #include "gk20a/css_gr_gk20a.h" #include "gk20a/mc_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/bus_gk20a.h" #include "gk20a/flcn_gk20a.h" #include "gk20a/regops_gk20a.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" #include "gp10b/ltc_gp10b.h" #include "gp10b/mc_gp10b.h" #include "gp10b/priv_ring_gp10b.h" #include "hal_gv11b.h" #include "gr_gv11b.h" #include "mc_gv11b.h" #include "ltc_gv11b.h" #include "fecs_trace_gv11b.h" #include "gv11b.h" #include "ce_gv11b.h" #include "gr_ctx_gv11b.h" #include "mm_gv11b.h" #include "pmu_gv11b.h" #include "therm_gv11b.h" #include "fb_gv11b.h" #include "fifo_gv11b.h" #include "gv11b_gating_reglist.h" #include "regops_gv11b.h" #include #include static int gv11b_get_litter_value(struct gk20a *g, int value) { int ret = EINVAL; switch (value) { case GPU_LIT_NUM_GPCS: ret = proj_scal_litter_num_gpcs_v(); break; case GPU_LIT_NUM_PES_PER_GPC: ret = proj_scal_litter_num_pes_per_gpc_v(); break; case GPU_LIT_NUM_ZCULL_BANKS: ret = proj_scal_litter_num_zcull_banks_v(); break; case GPU_LIT_NUM_TPC_PER_GPC: ret = proj_scal_litter_num_tpc_per_gpc_v(); break; case GPU_LIT_NUM_SM_PER_TPC: ret = proj_scal_litter_num_sm_per_tpc_v(); break; case GPU_LIT_NUM_FBPS: ret = proj_scal_litter_num_fbps_v(); break; case GPU_LIT_GPC_BASE: ret = proj_gpc_base_v(); break; case GPU_LIT_GPC_STRIDE: ret = proj_gpc_stride_v(); break; case GPU_LIT_GPC_SHARED_BASE: ret = proj_gpc_shared_base_v(); break; case GPU_LIT_TPC_IN_GPC_BASE: ret = proj_tpc_in_gpc_base_v(); break; case GPU_LIT_TPC_IN_GPC_STRIDE: ret = proj_tpc_in_gpc_stride_v(); break; case GPU_LIT_TPC_IN_GPC_SHARED_BASE: ret = proj_tpc_in_gpc_shared_base_v(); break; case GPU_LIT_PPC_IN_GPC_STRIDE: ret = proj_ppc_in_gpc_stride_v(); break; case GPU_LIT_ROP_BASE: ret = proj_rop_base_v(); break; case GPU_LIT_ROP_STRIDE: ret = proj_rop_stride_v(); break; case GPU_LIT_ROP_SHARED_BASE: ret = proj_rop_shared_base_v(); break; case GPU_LIT_HOST_NUM_ENGINES: ret = proj_host_num_engines_v(); break; case GPU_LIT_HOST_NUM_PBDMA: ret = proj_host_num_pbdma_v(); break; case GPU_LIT_LTC_STRIDE: ret = proj_ltc_stride_v(); break; case GPU_LIT_LTS_STRIDE: ret = proj_lts_stride_v(); break; case GPU_LIT_NUM_FBPAS: ret = proj_scal_litter_num_fbpas_v(); break; case GPU_LIT_FBPA_STRIDE: ret = proj_fbpa_stride_v(); break; case GPU_LIT_SM_PRI_STRIDE: ret = proj_sm_stride_v(); break; default: break; } return ret; } static const struct gpu_ops gv11b_ops = { .ltc = { .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry, .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, .init_cbc = NULL, .init_fs_state = gv11b_ltc_init_fs_state, .init_comptags = gp10b_ltc_init_comptags, .cbc_ctrl = gm20b_ltc_cbc_ctrl, .isr = gv11b_ltc_isr, .cbc_fix_config = gv11b_ltc_cbc_fix_config, .flush = gm20b_flush_ltc, #ifdef CONFIG_DEBUG_FS .sync_debugfs = gp10b_ltc_sync_debugfs, #endif }, .clock_gating = { .slcg_bus_load_gating_prod = gv11b_slcg_bus_load_gating_prod, .slcg_ce2_load_gating_prod = gv11b_slcg_ce2_load_gating_prod, .slcg_chiplet_load_gating_prod = gv11b_slcg_chiplet_load_gating_prod, .slcg_ctxsw_firmware_load_gating_prod = gv11b_slcg_ctxsw_firmware_load_gating_prod, .slcg_fb_load_gating_prod = gv11b_slcg_fb_load_gating_prod, .slcg_fifo_load_gating_prod = gv11b_slcg_fifo_load_gating_prod, .slcg_gr_load_gating_prod = gr_gv11b_slcg_gr_load_gating_prod, .slcg_ltc_load_gating_prod = ltc_gv11b_slcg_ltc_load_gating_prod, .slcg_perf_load_gating_prod = gv11b_slcg_perf_load_gating_prod, .slcg_priring_load_gating_prod = gv11b_slcg_priring_load_gating_prod, .slcg_pmu_load_gating_prod = gv11b_slcg_pmu_load_gating_prod, .slcg_therm_load_gating_prod = gv11b_slcg_therm_load_gating_prod, .slcg_xbar_load_gating_prod = gv11b_slcg_xbar_load_gating_prod, .blcg_bus_load_gating_prod = gv11b_blcg_bus_load_gating_prod, .blcg_ce_load_gating_prod = gv11b_blcg_ce_load_gating_prod, .blcg_ctxsw_firmware_load_gating_prod = gv11b_blcg_ctxsw_firmware_load_gating_prod, .blcg_fb_load_gating_prod = gv11b_blcg_fb_load_gating_prod, .blcg_fifo_load_gating_prod = gv11b_blcg_fifo_load_gating_prod, .blcg_gr_load_gating_prod = gv11b_blcg_gr_load_gating_prod, .blcg_ltc_load_gating_prod = gv11b_blcg_ltc_load_gating_prod, .blcg_pwr_csb_load_gating_prod = gv11b_blcg_pwr_csb_load_gating_prod, .blcg_pmu_load_gating_prod = gv11b_blcg_pmu_load_gating_prod, .blcg_xbar_load_gating_prod = gv11b_blcg_xbar_load_gating_prod, .pg_gr_load_gating_prod = gr_gv11b_pg_gr_load_gating_prod, }, .mc = { .intr_enable = mc_gv11b_intr_enable, .intr_unit_config = mc_gp10b_intr_unit_config, .isr_stall = mc_gp10b_isr_stall, .intr_stall = mc_gp10b_intr_stall, .intr_stall_pause = mc_gp10b_intr_stall_pause, .intr_stall_resume = mc_gp10b_intr_stall_resume, .intr_nonstall = mc_gp10b_intr_nonstall, .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, .enable = gk20a_mc_enable, .disable = gk20a_mc_disable, .reset = gk20a_mc_reset, .boot_0 = gk20a_mc_boot_0, .is_intr1_pending = mc_gp10b_is_intr1_pending, .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending, }, .debug = { .show_dump = gk20a_debug_show_dump, }, .dbg_session_ops = { .exec_reg_ops = exec_regops_gk20a, .dbg_set_powergate = dbg_set_powergate, .check_and_set_global_reservation = nvgpu_check_and_set_global_reservation, .check_and_set_context_reservation = nvgpu_check_and_set_context_reservation, .release_profiler_reservation = nvgpu_release_profiler_reservation, .perfbuffer_enable = gk20a_perfbuf_enable_locked, .perfbuffer_disable = gk20a_perfbuf_disable_locked, }, .bus = { .init_hw = gk20a_bus_init_hw, .isr = gk20a_bus_isr, .read_ptimer = gk20a_read_ptimer, .bar1_bind = NULL, }, #if defined(CONFIG_GK20A_CYCLE_STATS) .css = { .enable_snapshot = css_hw_enable_snapshot, .disable_snapshot = css_hw_disable_snapshot, .check_data_available = css_hw_check_data_available, .set_handled_snapshots = css_hw_set_handled_snapshots, .allocate_perfmon_ids = css_gr_allocate_perfmon_ids, .release_perfmon_ids = css_gr_release_perfmon_ids, }, #endif .falcon = { .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, }, .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics, .get_litter_value = gv11b_get_litter_value, }; int gv11b_init_hal(struct gk20a *g) { struct gpu_ops *gops = &g->ops; struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; gops->ltc = gv11b_ops.ltc; gops->clock_gating = gv11b_ops.clock_gating; gops->mc = gv11b_ops.mc; gops->debug = gv11b_ops.debug; gops->dbg_session_ops = gv11b_ops.dbg_session_ops; gops->bus = gv11b_ops.bus; #if defined(CONFIG_GK20A_CYCLE_STATS) gops->css = gv11b_ops.css; #endif gops->falcon = gv11b_ops.falcon; /* Lone functions */ gops->chip_init_gpu_characteristics = gv11b_ops.chip_init_gpu_characteristics; gops->get_litter_value = gv11b_ops.get_litter_value; /* boot in non-secure modes for time beeing */ gops->privsecurity = 0; gops->securegpccs = 0; gp10b_init_priv_ring(gops); gv11b_init_gr(gops); gv11b_init_fecs_trace_ops(gops); gv11b_init_fb(gops); gv11b_init_fifo(gops); gv11b_init_ce(gops); gv11b_init_gr_ctx(gops); gv11b_init_mm(gops); gv11b_init_pmu_ops(gops); gv11b_init_regops(gops); gv11b_init_therm_ops(gops); gk20a_init_tsg_ops(gops); g->name = "gv11b"; c->twod_class = FERMI_TWOD_A; c->threed_class = VOLTA_A; c->compute_class = VOLTA_COMPUTE_A; c->gpfifo_class = VOLTA_CHANNEL_GPFIFO_A; c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B; c->dma_copy_class = VOLTA_DMA_COPY_A; return 0; }