From 9d04e970937657d11620d812c29a5d10828440fc Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 9 Nov 2017 15:12:41 -0800 Subject: gpu: nvgpu: Remove separation of t18x code Remove separation of t18x specific code and fields and the associated ifdefs. We can build T18x code in always. Change-Id: I4e8eae9c30335632a2da48b418c6138193831b4f Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1595431 Reviewed-by: mobile promotions Tested-by: mobile promotions --- include/uapi/linux/nvgpu-t18x.h | 61 ----------------------------------------- include/uapi/linux/nvgpu.h | 31 ++++++++++++++++++--- 2 files changed, 27 insertions(+), 65 deletions(-) delete mode 100644 include/uapi/linux/nvgpu-t18x.h (limited to 'include/uapi') diff --git a/include/uapi/linux/nvgpu-t18x.h b/include/uapi/linux/nvgpu-t18x.h deleted file mode 100644 index 59db77c7..00000000 --- a/include/uapi/linux/nvgpu-t18x.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * NVGPU Public Interface Header - * - * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -/* This file is meant to extend nvgpu.h, not replace it - * as such, be sure that nvgpu.h is actually the file performing the - * inclusion, to the extent that's possible. - */ -#ifndef _UAPI__LINUX_NVGPU_IOCTL_H -# error "This file is to be included within nvgpu.h only." -#endif - -#ifndef _UAPI__LINUX_NVGPU_T18X_IOCTL_H_ -#define _UAPI__LINUX_NVGPU_T18X_IOCTL_H_ - -/* - * this flag is used in struct nvgpu_alloc_gpfifo_args - * to enable re-playable faults for that channel - */ -#define NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE (1 << 2) - -/* Flags in nvgpu_alloc_obj_ctx_args.flags */ -#define NVGPU_ALLOC_OBJ_FLAGS_GFXP (1 << 1) -#define NVGPU_ALLOC_OBJ_FLAGS_CILP (1 << 2) - -/* Flags in nvgpu_preemption_mode_args.graphics_preempt_flags */ -#define NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP (1 << 1) -/* Flags in nvgpu_preemption_mode_args.compute_preempt_flags */ -#define NVGPU_COMPUTE_PREEMPTION_MODE_CILP (1 << 2) - -/* SM LRF ECC is enabled */ -#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60) -/* SM SHM ECC is enabled */ -#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM (1ULL << 61) -/* TEX ECC is enabled */ -#define NVGPU_GPU_FLAGS_ECC_ENABLED_TEX (1ULL << 62) -/* L2 ECC is enabled */ -#define NVGPU_GPU_FLAGS_ECC_ENABLED_LTC (1ULL << 63) -/* All types of ECC are enabled */ -#define NVGPU_GPU_FLAGS_ALL_ECC_ENABLED \ - (NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF | \ - NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM | \ - NVGPU_GPU_FLAGS_ECC_ENABLED_TEX | \ - NVGPU_GPU_FLAGS_ECC_ENABLED_LTC) - -/* Channel event_id in nvgpu_channel_events_ctrl_ext_args */ -#define NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED 3 -#define NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE 4 - -#endif /* _UAPI__LINUX_NVGPU_T18X_IOCTL_H_ */ diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index bf711ef8..95da072c 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h @@ -94,10 +94,6 @@ struct nvgpu_gpu_zbc_query_table_args { #define NVGPU_GPU_IMPL_GP106 0x00000006 #define NVGPU_GPU_IMPL_GP10B 0x0000000B -#ifdef CONFIG_ARCH_TEGRA_18x_SOC -#include -#endif - #ifdef CONFIG_TEGRA_19x_GPU #include #endif @@ -150,6 +146,20 @@ struct nvgpu_gpu_zbc_query_table_args { #define NVGPU_GPU_FLAGS_SUPPORT_MAP_DIRECT_KIND_CTRL (1ULL << 23) /* NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS is available */ #define NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_OPTS (1ULL << 24) +/* SM LRF ECC is enabled */ +#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60) +/* SM SHM ECC is enabled */ +#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM (1ULL << 61) +/* TEX ECC is enabled */ +#define NVGPU_GPU_FLAGS_ECC_ENABLED_TEX (1ULL << 62) +/* L2 ECC is enabled */ +#define NVGPU_GPU_FLAGS_ECC_ENABLED_LTC (1ULL << 63) +/* All types of ECC are enabled */ +#define NVGPU_GPU_FLAGS_ALL_ECC_ENABLED \ + (NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF | \ + NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM | \ + NVGPU_GPU_FLAGS_ECC_ENABLED_TEX | \ + NVGPU_GPU_FLAGS_ECC_ENABLED_LTC) struct nvgpu_gpu_characteristics { __u32 arch; @@ -1388,6 +1398,9 @@ struct nvgpu_set_nvmap_fd_args { } __packed; #define NVGPU_ALLOC_OBJ_FLAGS_LOCKBOOST_ZERO (1 << 0) +/* Flags in nvgpu_alloc_obj_ctx_args.flags */ +#define NVGPU_ALLOC_OBJ_FLAGS_GFXP (1 << 1) +#define NVGPU_ALLOC_OBJ_FLAGS_CILP (1 << 2) struct nvgpu_alloc_obj_ctx_args { __u32 class_num; /* kepler3d, 2d, compute, etc */ @@ -1398,6 +1411,11 @@ struct nvgpu_alloc_obj_ctx_args { struct nvgpu_alloc_gpfifo_args { __u32 num_entries; #define NVGPU_ALLOC_GPFIFO_FLAGS_VPR_ENABLED (1 << 0) /* set owner channel of this gpfifo as a vpr channel */ +/* + * this flag is used in struct nvgpu_alloc_gpfifo_args + * to enable re-playable faults for that channel + */ +#define NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE (1 << 2) __u32 flags; }; @@ -1592,6 +1610,8 @@ struct nvgpu_event_id_ctrl_args { #define NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_INT 0 #define NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_PAUSE 1 #define NVGPU_IOCTL_CHANNEL_EVENT_ID_BLOCKING_SYNC 2 +#define NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED 3 +#define NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE 4 #define NVGPU_IOCTL_CHANNEL_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN 5 #define NVGPU_IOCTL_CHANNEL_EVENT_ID_MAX 6 @@ -1600,11 +1620,14 @@ struct nvgpu_event_id_ctrl_args { struct nvgpu_preemption_mode_args { /* only one should be enabled at a time */ #define NVGPU_GRAPHICS_PREEMPTION_MODE_WFI (1 << 0) +#define NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP (1 << 1) __u32 graphics_preempt_mode; /* in */ /* only one should be enabled at a time */ #define NVGPU_COMPUTE_PREEMPTION_MODE_WFI (1 << 0) #define NVGPU_COMPUTE_PREEMPTION_MODE_CTA (1 << 1) +#define NVGPU_COMPUTE_PREEMPTION_MODE_CILP (1 << 2) + __u32 compute_preempt_mode; /* in */ }; -- cgit v1.2.2