From dc281d6a9ebadaeb66dab092b40b7d6f4559ee39 Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Tue, 30 Apr 2019 17:19:51 -0700 Subject: gpu: nvgpu: add SET_CTX_MMU_DEBUG_MODE ioctl Added NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE ioctl to set MMU debug mode for a given context. Added gr.set_mmu_debug_mode HAL to change NV_PGPC_PRI_MMU_DEBUG_CTRL for a given channel. HAL implementation for native case is gm20b_gr_set_mmu_debug_mode. It internally uses regops, which directly writes to the register if the context is resident, or writes to gr context otherwise. Added NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE to enable the feature. NV_PGPC_PRI_MMU_DEBUG_CTRL has to be context switched in FECS ucode, so the feature is only enabled on TU104 for now. Bug 2515097 But 2713590 Change-Id: Ib4efaf06fc47a8539b4474f94c68c20ce225263f Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/2110720 (cherry-picked from commit af2ccb811d3de06f052b1dee39bd9ffa863ac8ce) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208767 Reviewed-by: Kajetan Dutka Reviewed-by: Alex Waterman Reviewed-by: Winnie Hsu Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: Kajetan Dutka Tested-by: mobile promotions --- include/uapi/linux/nvgpu.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'include/uapi/linux/nvgpu.h') diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index 9197011b..786f8268 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h @@ -166,6 +166,8 @@ struct nvgpu_gpu_zbc_query_table_args { #define NVGPU_GPU_FLAGS_CAN_RAILGATE (1ULL << 29) /* Usermode submit is available */ #define NVGPU_GPU_FLAGS_SUPPORT_USERMODE_SUBMIT (1ULL << 30) +/* Set MMU debug mode is available */ +#define NVGPU_GPU_FLAGS_SUPPORT_SET_CTX_MMU_DEBUG_MODE (1ULL << 32) /* SM LRF ECC is enabled */ #define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60) /* SM SHM ECC is enabled */ @@ -1414,8 +1416,20 @@ struct nvgpu_dbg_gpu_set_sm_exception_type_mask_args { _IOW(NVGPU_DBG_GPU_IOCTL_MAGIC, 23, \ struct nvgpu_dbg_gpu_set_sm_exception_type_mask_args) +/* MMU Debug Mode */ +#define NVGPU_DBG_GPU_CTX_MMU_DEBUG_MODE_DISABLED 0 +#define NVGPU_DBG_GPU_CTX_MMU_DEBUG_MODE_ENABLED 1 + +struct nvgpu_dbg_gpu_set_ctx_mmu_debug_mode_args { + __u32 mode; + __u32 reserved; +}; +#define NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE \ + _IOW(NVGPU_DBG_GPU_IOCTL_MAGIC, 26, \ + struct nvgpu_dbg_gpu_set_ctx_mmu_debug_mode_args) + #define NVGPU_DBG_GPU_IOCTL_LAST \ - _IOC_NR(NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK) + _IOC_NR(NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE) #define NVGPU_DBG_GPU_IOCTL_MAX_ARG_SIZE \ sizeof(struct nvgpu_dbg_gpu_access_fb_memory_args) -- cgit v1.2.2