From 895675e1d5790e2361b22edb50d702f7dd9a8edd Mon Sep 17 00:00:00 2001 From: sujeet baranwal Date: Mon, 2 Mar 2015 15:36:22 -0800 Subject: gpu: nvgpu: Removal of regops from CUDA driver The current CUDA drivers have been using the regops to directly accessing the GPU registers from user space through the dbg node. This is a security hole and needs to be avoided. The patch alternatively implements the similar functionality in the kernel and provide an ioctl for it. Bug 200083334 Change-Id: Ic5ff5a215cbabe7a46837bc4e15efcceb0df0367 Signed-off-by: sujeet baranwal Reviewed-on: http://git-master/r/711758 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- include/uapi/linux/nvgpu.h | 42 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) (limited to 'include/uapi/linux/nvgpu.h') diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index b04ef2e3..3a7c7831 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h @@ -252,6 +252,36 @@ struct nvgpu_gpu_l2_fb_args { __u32 reserved; } __packed; +struct nvgpu_gpu_inval_icache_args { + int channel_fd; + __u32 reserved; +} __packed; + +struct nvgpu_gpu_mmu_debug_mode_args { + __u32 state; + __u32 reserved; +} __packed; + +struct nvgpu_gpu_sm_debug_mode_args { + int channel_fd; + __u32 enable; + __u64 sms; +} __packed; + +struct warpstate { + __u64 valid_warps; + __u64 trapped_warps; + __u64 paused_warps; +}; + +struct nvgpu_gpu_wait_pause_args { + __u64 pwarpstate; +}; + +struct nvgpu_gpu_tpc_exception_en_status_args { + __u64 tpc_exception_en_sm_mask; +}; + #define NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE \ _IOR(NVGPU_GPU_IOCTL_MAGIC, 1, struct nvgpu_gpu_zcull_get_ctx_size_args) #define NVGPU_GPU_IOCTL_ZCULL_GET_INFO \ @@ -276,9 +306,19 @@ struct nvgpu_gpu_l2_fb_args { _IOWR(NVGPU_GPU_IOCTL_MAGIC, 11, struct nvgpu_gpu_open_channel_args) #define NVGPU_GPU_IOCTL_FLUSH_L2 \ _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 12, struct nvgpu_gpu_l2_fb_args) +#define NVGPU_GPU_IOCTL_INVAL_ICACHE \ + _IOWR(NVGPU_GPU_IOCTL_MAGIC, 13, struct nvgpu_gpu_inval_icache_args) +#define NVGPU_GPU_IOCTL_SET_MMUDEBUG_MODE \ + _IOWR(NVGPU_GPU_IOCTL_MAGIC, 14, struct nvgpu_gpu_mmu_debug_mode_args) +#define NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE \ + _IOWR(NVGPU_GPU_IOCTL_MAGIC, 15, struct nvgpu_gpu_sm_debug_mode_args) +#define NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE \ + _IOWR(NVGPU_GPU_IOCTL_MAGIC, 16, struct nvgpu_gpu_wait_pause_args) +#define NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS \ + _IOWR(NVGPU_GPU_IOCTL_MAGIC, 17, struct nvgpu_gpu_tpc_exception_en_status_args) #define NVGPU_GPU_IOCTL_LAST \ - _IOC_NR(NVGPU_GPU_IOCTL_FLUSH_L2) + _IOC_NR(NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS) #define NVGPU_GPU_IOCTL_MAX_ARG_SIZE \ sizeof(struct nvgpu_gpu_prepare_compressible_read_args) -- cgit v1.2.2