From fb3a1d31cd84771b659050ea1aa920bdf06ffb04 Mon Sep 17 00:00:00 2001 From: Aingara Paramakuru Date: Mon, 5 Oct 2015 17:56:17 -0700 Subject: gpu: nvgpu: vgpu: fix notification handling Take a channel ref when handling a notification from the server, to prevent the channel from being closed. Also, mark the channel as faulted before calling g20a_channel_abort, to keep the semantics the same as the native driver. Bug 1653186 Change-Id: I0cb8ce7bad22a4d508eade6ff63a412296a02fc9 Signed-off-by: Aingara Paramakuru Reviewed-on: http://git-master/r/811885 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/817021 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 9 +++++++-- drivers/gpu/nvgpu/vgpu/gr_vgpu.c | 6 +++++- 2 files changed, 12 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index 84bb3646..a2ecd864 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c @@ -541,7 +541,11 @@ static void vgpu_fifo_set_ctx_mmu_error(struct gk20a *g, int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info) { struct fifo_gk20a *f = &g->fifo; - struct channel_gk20a *ch = &f->channel[info->chid]; + struct channel_gk20a *ch = gk20a_channel_get(&f->channel[info->chid]); + + gk20a_dbg_fn(""); + if (!ch) + return 0; gk20a_err(dev_from_gk20a(g), "fifo intr (%d) on ch %u", info->type, info->chid); @@ -555,14 +559,15 @@ int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info) NVGPU_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT); break; case TEGRA_VGPU_FIFO_INTR_MMU_FAULT: - gk20a_channel_abort(ch); vgpu_fifo_set_ctx_mmu_error(g, ch); + gk20a_channel_abort(ch); break; default: WARN_ON(1); break; } + gk20a_channel_put(ch); return 0; } diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c index 7dfc970e..b259a0c3 100644 --- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c @@ -851,9 +851,12 @@ int vgpu_init_gr_support(struct gk20a *g) int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info) { struct fifo_gk20a *f = &g->fifo; - struct channel_gk20a *ch = &f->channel[info->chid]; + struct channel_gk20a *ch = gk20a_channel_get(&f->channel[info->chid]); gk20a_dbg_fn(""); + if (!ch) + return 0; + if (info->type != TEGRA_VGPU_GR_INTR_NOTIFY && info->type != TEGRA_VGPU_GR_INTR_SEMAPHORE) gk20a_err(dev_from_gk20a(g), "gr intr (%d) on ch %u", @@ -899,6 +902,7 @@ int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info) break; } + gk20a_channel_put(ch); return 0; } -- cgit v1.2.2