From f81d83690f9d08be0daf8a488331fb04d9d23c46 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Mon, 26 Mar 2018 22:31:56 -0700 Subject: gpu: nvgpu: use gpc_tpc_count[gpc] for number of tpc in a gpc Using tpc_count instead of gpc_tpc_count indexed by gpc, will result in pbus error with decode error or client floorswept error codes. tpc_count represents total number of tpc while gpc_tpc_count[gpc] represents number of tpc in the indexed gpc. Bug 1998067 Change-Id: I9adfb98a6c3e209cbb02a8cd5090f6b6adc1ec4b Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1682469 Reviewed-by: Thomas Fleury Tested-by: Thomas Fleury Reviewed-by: svc-mobile-coverity Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 6 +++--- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 7 ++++--- 2 files changed, 7 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 9d85a5ef..cf63546b 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -4417,7 +4417,7 @@ void gk20a_gr_enable_gpc_exceptions(struct gk20a *g) gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f()); tpc_mask = - gr_gpcs_gpccs_gpc_exception_en_tpc_f((1 << gr->tpc_count) - 1); + gr_gpcs_gpccs_gpc_exception_en_tpc_f((1 << gr->max_tpc_per_gpc_count) - 1); gk20a_writel(g, gr_gpcs_gpccs_gpc_exception_en_r(), tpc_mask); } @@ -5792,7 +5792,7 @@ static int gk20a_gr_handle_gpc_exception(struct gk20a *g, bool *post_event, + gpc_offset); /* check if any tpc has an exception */ - for (tpc = 0; tpc < gr->tpc_count; tpc++) { + for (tpc = 0; tpc < gr->gpc_tpc_count[gpc]; tpc++) { if ((gr_gpc0_gpccs_gpc_exception_tpc_v(gpc_exception) & (1 << tpc)) == 0) continue; @@ -8674,7 +8674,7 @@ int gr_gk20a_clear_sm_errors(struct gk20a *g) for (gpc = 0; gpc < gr->gpc_count; gpc++) { /* check if any tpc has an exception */ - for (tpc = 0; tpc < gr->tpc_count; tpc++) { + for (tpc = 0; tpc < gr->gpc_tpc_count[gpc]; tpc++) { for (sm = 0; sm < sm_per_tpc; sm++) { global_esr = g->ops.gr.get_sm_hww_global_esr(g, diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 4f517fa7..e0c60efb 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -939,7 +939,8 @@ void gr_gv11b_enable_gpc_exceptions(struct gk20a *g) gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f()); tpc_mask = - gr_gpcs_gpccs_gpc_exception_en_tpc_f((1 << gr->tpc_count) - 1); + gr_gpcs_gpccs_gpc_exception_en_tpc_f( + (1 << gr->max_tpc_per_gpc_count) - 1); gk20a_writel(g, gr_gpcs_gpccs_gpc_exception_en_r(), (tpc_mask | gr_gpcs_gpccs_gpc_exception_en_gcc_f(1) | @@ -1743,7 +1744,7 @@ static int gr_gv11b_dump_gr_sm_regs(struct gk20a *g, for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { gpc_offset = gk20a_gr_gpc_offset(g, gpc); - for (tpc = 0; tpc < g->gr.tpc_count; tpc++) { + for (tpc = 0; tpc < g->gr.gpc_tpc_count[gpc]; tpc++) { tpc_offset = gk20a_gr_tpc_offset(g, tpc); for (sm = 0; sm < sm_per_tpc; sm++) { @@ -4155,7 +4156,7 @@ static int gr_gv11b_ecc_scrub_is_done(struct gk20a *g, for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { gpc_offset = gk20a_gr_gpc_offset(g, gpc); - for (tpc = 0; tpc < g->gr.tpc_count; tpc++) { + for (tpc = 0; tpc < g->gr.gpc_tpc_count[gpc]; tpc++) { tpc_offset = gk20a_gr_tpc_offset(g, tpc); do { -- cgit v1.2.2