From f21659431f47722bc7596aa72d22a268967ea696 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 1 Mar 2017 13:40:32 -0800 Subject: gpu: ngpu: add fb ops for hub isr If supported, detect and handle hub interrupt JIRA GPUT19X-7 Change-Id: I431c92160636afb2bc94ff2677614023de595681 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1313452 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gk20a.h | 2 ++ drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 7 ++++++- 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index e3dad962..d781034c 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -368,6 +368,7 @@ struct gpu_ops { bool (*is_debug_mode_enabled)(struct gk20a *g); void (*set_debug_mode)(struct gk20a *g, bool enable); void (*tlb_invalidate)(struct gk20a *g, struct mem_desc *pdb); + void (*hub_isr)(struct gk20a *g); } fb; struct { void (*slcg_bus_load_gating_prod)(struct gk20a *g, bool prod); @@ -758,6 +759,7 @@ struct gpu_ops { irqreturn_t (*isr_thread_stall)(struct gk20a *g); void (*isr_thread_nonstall)(struct gk20a *g, u32 intr); void (*isr_nonstall_cb)(struct work_struct *work); + bool (*is_intr_hub_pending)(struct gk20a *g, u32 mc_intr); u32 intr_mask_restore[4]; void (*enable)(struct gk20a *g, u32 units); void (*disable)(struct gk20a *g, u32 units); diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 4b0cbc1c..4a8dc4c1 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c @@ -131,7 +131,7 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); hw_irq_count = atomic_read(&g->hw_irq_stall_count); - gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); + gk20a_dbg(gpu_dbg_intr, "stall intr 0x%08x\n", mc_intr_0); for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) { active_engine_id = g->fifo.active_engines_list[engine_id_idx]; @@ -153,6 +153,9 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) } } } + if (g->ops.mc.is_intr_hub_pending && + g->ops.mc.is_intr_hub_pending(g, mc_intr_0)) + g->ops.fb.hub_isr(g); if (mc_intr_0 & mc_intr_pfifo_pending_f()) gk20a_fifo_isr(g); if (mc_intr_0 & mc_intr_pmu_pending_f()) @@ -167,6 +170,8 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) /* sync handled irq counter before re-enabling interrupts */ atomic_set(&g->sw_irq_stall_last_handled, hw_irq_count); + gk20a_dbg(gpu_dbg_intr, "stall intr done 0x%08x\n", mc_intr_0); + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); -- cgit v1.2.2