From f04a84b7ce976e911bf81497796016e149d17082 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 6 Feb 2017 15:57:12 -0800 Subject: gpu: nvgpu: gv11b: chip specific init_elcg_mode Added thermal registers for gv11b. Implemented chip specific init_elcg_mode. In thermal control register, engine power auto control config is removed and added new field for engine holdoff enable signal. JIRA GV11B-58 Change-Id: I412d9a232800d25efbdb0a40f14949d3f085fb0e Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1300119 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 35 ++ .../nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h | 354 ++++++++++++++++++++- 2 files changed, 388 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index daadef68..3c332bbf 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -41,6 +41,7 @@ #include #include #include +#include static bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) { @@ -1970,6 +1971,39 @@ static void gr_gv11b_write_pm_ptr(struct gk20a *g, ctxsw_prog_main_image_pm_ptr_hi_o(), va_hi); } +void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine) +{ + u32 gate_ctrl; + + gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine)); + + switch (mode) { + case ELCG_RUN: + gate_ctrl = set_field(gate_ctrl, + therm_gate_ctrl_eng_clk_m(), + therm_gate_ctrl_eng_clk_run_f()); + gate_ctrl = set_field(gate_ctrl, + therm_gate_ctrl_idle_holdoff_m(), + therm_gate_ctrl_idle_holdoff_on_f()); + break; + case ELCG_STOP: + gate_ctrl = set_field(gate_ctrl, + therm_gate_ctrl_eng_clk_m(), + therm_gate_ctrl_eng_clk_stop_f()); + break; + case ELCG_AUTO: + gate_ctrl = set_field(gate_ctrl, + therm_gate_ctrl_eng_clk_m(), + therm_gate_ctrl_eng_clk_auto_f()); + break; + default: + gk20a_err(dev_from_gk20a(g), + "invalid elcg mode %d", mode); + } + + gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl); +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -2025,5 +2059,6 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.restore_context_header = gv11b_restore_context_header; gops->gr.write_zcull_ptr = gr_gv11b_write_zcull_ptr; gops->gr.write_pm_ptr = gr_gv11b_write_pm_ptr; + gops->gr.init_elcg_mode = gr_gv11b_init_elcg_mode; } diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h index a3cfcf91..7be6d074 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -50,4 +50,356 @@ #ifndef _hw_therm_gv11b_h_ #define _hw_therm_gv11b_h_ +static inline u32 therm_use_a_r(void) +{ + return 0x00020798; +} +static inline u32 therm_use_a_ext_therm_0_enable_f(void) +{ + return 0x1; +} +static inline u32 therm_use_a_ext_therm_1_enable_f(void) +{ + return 0x2; +} +static inline u32 therm_use_a_ext_therm_2_enable_f(void) +{ + return 0x4; +} +static inline u32 therm_evt_ext_therm_0_r(void) +{ + return 0x00020700; +} +static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v) +{ + return (v & 0x3f) << 24; +} +static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void) +{ + return 0x00000001; +} +static inline u32 therm_evt_ext_therm_0_mode_f(u32 v) +{ + return (v & 0x3) << 30; +} +static inline u32 therm_evt_ext_therm_0_mode_normal_v(void) +{ + return 0x00000000; +} +static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void) +{ + return 0x00000001; +} +static inline u32 therm_evt_ext_therm_0_mode_forced_v(void) +{ + return 0x00000002; +} +static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void) +{ + return 0x00000003; +} +static inline u32 therm_evt_ext_therm_1_r(void) +{ + return 0x00020704; +} +static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v) +{ + return (v & 0x3f) << 24; +} +static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void) +{ + return 0x00000002; +} +static inline u32 therm_evt_ext_therm_1_mode_f(u32 v) +{ + return (v & 0x3) << 30; +} +static inline u32 therm_evt_ext_therm_1_mode_normal_v(void) +{ + return 0x00000000; +} +static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void) +{ + return 0x00000001; +} +static inline u32 therm_evt_ext_therm_1_mode_forced_v(void) +{ + return 0x00000002; +} +static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void) +{ + return 0x00000003; +} +static inline u32 therm_evt_ext_therm_2_r(void) +{ + return 0x00020708; +} +static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v) +{ + return (v & 0x3f) << 24; +} +static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void) +{ + return 0x00000003; +} +static inline u32 therm_evt_ext_therm_2_mode_f(u32 v) +{ + return (v & 0x3) << 30; +} +static inline u32 therm_evt_ext_therm_2_mode_normal_v(void) +{ + return 0x00000000; +} +static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void) +{ + return 0x00000001; +} +static inline u32 therm_evt_ext_therm_2_mode_forced_v(void) +{ + return 0x00000002; +} +static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void) +{ + return 0x00000003; +} +static inline u32 therm_weight_1_r(void) +{ + return 0x00020024; +} +static inline u32 therm_config1_r(void) +{ + return 0x00020050; +} +static inline u32 therm_config2_r(void) +{ + return 0x00020130; +} +static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 therm_config2_grad_enable_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 therm_gate_ctrl_r(u32 i) +{ + return 0x00020200 + i*4; +} +static inline u32 therm_gate_ctrl_eng_clk_m(void) +{ + return 0x3 << 0; +} +static inline u32 therm_gate_ctrl_eng_clk_run_f(void) +{ + return 0x0; +} +static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) +{ + return 0x1; +} +static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) +{ + return 0x2; +} +static inline u32 therm_gate_ctrl_blk_clk_m(void) +{ + return 0x3 << 2; +} +static inline u32 therm_gate_ctrl_blk_clk_run_f(void) +{ + return 0x0; +} +static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) +{ + return 0x4; +} +static inline u32 therm_gate_ctrl_idle_holdoff_m(void) +{ + return 0x1 << 4; +} +static inline u32 therm_gate_ctrl_idle_holdoff_off_f(void) +{ + return 0x0; +} +static inline u32 therm_gate_ctrl_idle_holdoff_on_f(void) +{ + return 0x10; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) +{ + return (v & 0x1f) << 8; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) +{ + return 0x1f << 8; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) +{ + return (v & 0x7) << 13; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) +{ + return 0x7 << 13; +} +static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 therm_gate_ctrl_eng_delay_before_m(void) +{ + return 0xf << 16; +} +static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) +{ + return (v & 0xf) << 20; +} +static inline u32 therm_gate_ctrl_eng_delay_after_m(void) +{ + return 0xf << 20; +} +static inline u32 therm_fecs_idle_filter_r(void) +{ + return 0x00020288; +} +static inline u32 therm_fecs_idle_filter_value_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 therm_hubmmu_idle_filter_r(void) +{ + return 0x0002028c; +} +static inline u32 therm_hubmmu_idle_filter_value_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 therm_clk_slowdown_r(u32 i) +{ + return 0x00020160 + i*4; +} +static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) +{ + return (v & 0x3f) << 16; +} +static inline u32 therm_clk_slowdown_idle_factor_m(void) +{ + return 0x3f << 16; +} +static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) +{ + return (r >> 16) & 0x3f; +} +static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) +{ + return 0x0; +} +static inline u32 therm_grad_stepping_table_r(u32 i) +{ + return 0x000202c8 + i*4; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) +{ + return 0x3f << 0; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) +{ + return 0x1; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) +{ + return 0x2; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) +{ + return 0x6; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) +{ + return 0xe; +} +static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) +{ + return (v & 0x3f) << 6; +} +static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) +{ + return 0x3f << 6; +} +static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) +{ + return (v & 0x3f) << 12; +} +static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) +{ + return 0x3f << 12; +} +static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) +{ + return (v & 0x3f) << 18; +} +static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) +{ + return 0x3f << 18; +} +static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) +{ + return (v & 0x3f) << 24; +} +static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) +{ + return 0x3f << 24; +} +static inline u32 therm_grad_stepping0_r(void) +{ + return 0x000202c0; +} +static inline u32 therm_grad_stepping0_feature_s(void) +{ + return 1; +} +static inline u32 therm_grad_stepping0_feature_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 therm_grad_stepping0_feature_m(void) +{ + return 0x1 << 0; +} +static inline u32 therm_grad_stepping0_feature_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 therm_grad_stepping0_feature_enable_f(void) +{ + return 0x1; +} +static inline u32 therm_grad_stepping1_r(void) +{ + return 0x000202c4; +} +static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 therm_clk_timing_r(u32 i) +{ + return 0x000203c0 + i*4; +} +static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 therm_clk_timing_grad_slowdown_m(void) +{ + return 0x1 << 16; +} +static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) +{ + return 0x10000; +} #endif -- cgit v1.2.2