From dffeea5deb9754686e60eafec5194b7bf7bb4e77 Mon Sep 17 00:00:00 2001 From: Vinod G Date: Thu, 17 May 2018 14:43:51 -0700 Subject: gpu: nvgpu: Code updates for MISRA violations As part of the MISRA fixes, moving all the gating_reglist files to common/clock_gating dir, the new directory structure suggested to follow. Removed unused gating_reglist files for gk20a JIRA NVGPU-646 Change-Id: I388855befcf991ee68eeffed10fe9ac456210649 Signed-off-by: Vinod G Reviewed-on: https://git-master.nvidia.com/r/1722330 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 12 +- drivers/gpu/nvgpu/Makefile.sources | 13 +- .../common/clock_gating/gm20b_gating_reglist.c | 731 ++++++++++++++++ .../common/clock_gating/gm20b_gating_reglist.h | 100 +++ .../common/clock_gating/gp106_gating_reglist.c | 679 +++++++++++++++ .../common/clock_gating/gp106_gating_reglist.h | 93 ++ .../common/clock_gating/gp10b_gating_reglist.c | 742 ++++++++++++++++ .../common/clock_gating/gp10b_gating_reglist.h | 99 +++ .../common/clock_gating/gv100_gating_reglist.c | 951 +++++++++++++++++++++ .../common/clock_gating/gv100_gating_reglist.h | 99 +++ .../common/clock_gating/gv11b_gating_reglist.c | 750 ++++++++++++++++ .../common/clock_gating/gv11b_gating_reglist.h | 99 +++ drivers/gpu/nvgpu/gk20a/gk20a_gating_reglist.c | 404 --------- drivers/gpu/nvgpu/gk20a/gk20a_gating_reglist.h | 47 - drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.c | 731 ---------------- drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.h | 100 --- drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 2 +- drivers/gpu/nvgpu/gp106/gp106_gating_reglist.c | 679 --------------- drivers/gpu/nvgpu/gp106/gp106_gating_reglist.h | 93 -- drivers/gpu/nvgpu/gp106/hal_gp106.c | 2 +- drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c | 742 ---------------- drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h | 99 --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 +- drivers/gpu/nvgpu/gv100/gv100_gating_reglist.c | 951 --------------------- drivers/gpu/nvgpu/gv100/gv100_gating_reglist.h | 99 --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 +- drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c | 750 ---------------- drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.h | 99 --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 +- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 2 +- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 2 +- 31 files changed, 4362 insertions(+), 4814 deletions(-) create mode 100644 drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.c create mode 100644 drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.h create mode 100644 drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.c create mode 100644 drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.h create mode 100644 drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.c create mode 100644 drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.h create mode 100644 drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.c create mode 100644 drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.h create mode 100644 drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.c create mode 100644 drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.h delete mode 100644 drivers/gpu/nvgpu/gk20a/gk20a_gating_reglist.c delete mode 100644 drivers/gpu/nvgpu/gk20a/gk20a_gating_reglist.h delete mode 100644 drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.c delete mode 100644 drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.h delete mode 100644 drivers/gpu/nvgpu/gp106/gp106_gating_reglist.c delete mode 100644 drivers/gpu/nvgpu/gp106/gp106_gating_reglist.h delete mode 100644 drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c delete mode 100644 drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h delete mode 100644 drivers/gpu/nvgpu/gv100/gv100_gating_reglist.c delete mode 100644 drivers/gpu/nvgpu/gv100/gv100_gating_reglist.h delete mode 100644 drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c delete mode 100644 drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.h (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 599e97e2..e180ad1d 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -2,6 +2,7 @@ GCOV_PROFILE := y ccflags-y += -I$(srctree.nvgpu)/drivers/gpu/nvgpu/include ccflags-y += -I$(srctree.nvgpu)/drivers/gpu/nvgpu +ccflags-y += -I$(srctree.nvgpu)/drivers/gpu/nvgpu/common ccflags-y += -I$(srctree.nvgpu)/include ccflags-y += -I$(srctree.nvgpu)/include/uapi ccflags-y += -I$(srctree.nvgpu-next)/drivers/gpu/nvgpu @@ -80,6 +81,11 @@ nvgpu-y := \ common/pmu/pmu_perfmon.o \ common/pmu/pmu_debug.o \ common/ltc.o \ + common/clock_gating/gm20b_gating_reglist.o \ + common/clock_gating/gp106_gating_reglist.o \ + common/clock_gating/gp10b_gating_reglist.o \ + common/clock_gating/gv100_gating_reglist.o \ + common/clock_gating/gv11b_gating_reglist.o \ gk20a/gk20a.o \ gk20a/bus_gk20a.o \ gk20a/pramin_gk20a.o \ @@ -98,7 +104,6 @@ nvgpu-y := \ gk20a/therm_gk20a.o \ gk20a/gr_ctx_gk20a_sim.o \ gk20a/gr_ctx_gk20a.o \ - gk20a/gk20a_gating_reglist.o \ gk20a/fb_gk20a.o \ gk20a/hal.o \ gk20a/tsg_gk20a.o \ @@ -112,7 +117,6 @@ nvgpu-y := \ gm20b/fb_gm20b.o \ gm20b/fifo_gm20b.o \ gm20b/gr_ctx_gm20b.o \ - gm20b/gm20b_gating_reglist.o \ gm20b/acr_gm20b.o \ gm20b/pmu_gm20b.o \ gm20b/mm_gm20b.o \ @@ -225,7 +229,6 @@ nvgpu-y += \ gp10b/pmu_gp10b.o \ gp10b/hal_gp10b.o \ gp10b/rpfb_gp10b.o \ - gp10b/gp10b_gating_reglist.o \ gp10b/regops_gp10b.o \ gp10b/therm_gp10b.o \ gp10b/fecs_trace_gp10b.o \ @@ -252,7 +255,6 @@ nvgpu-y += \ gv11b/mc_gv11b.o \ gv11b/ltc_gv11b.o \ gv11b/hal_gv11b.o \ - gv11b/gv11b_gating_reglist.o \ gv11b/gr_gv11b.o \ gv11b/fb_gv11b.o \ gv11b/fifo_gv11b.o \ @@ -276,7 +278,6 @@ nvgpu-y += \ gv100/nvlink_gv100.o \ gv100/hal_gv100.o \ gv100/pmu_gv100.o \ - gv100/gv100_gating_reglist.o \ pstate/pstate.o \ clk/clk_vin.o \ clk/clk_fll.o \ @@ -291,7 +292,6 @@ nvgpu-y += \ clk/clk.o \ gp106/clk_gp106.o \ gp106/clk_arb_gp106.o \ - gp106/gp106_gating_reglist.o \ gp106/xve_gp106.o \ gp106/therm_gp106.o \ gp106/xve_gp106.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 676ca05b..06f10c20 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -71,6 +71,11 @@ srcs := common/mm/nvgpu_allocator.c \ common/posix/nvlink.c \ common/posix/lock.c \ common/posix/stubs.c \ + common/clock_gating/gm20b_gating_reglist.c \ + common/clock_gating/gp10b_gating_reglist.c \ + common/clock_gating/gv11b_gating_reglist.c \ + common/clock_gating/gp106_gating_reglist.c \ + common/clock_gating/gv100_gating_reglist.c \ boardobj/boardobj.c \ boardobj/boardobjgrp.c \ boardobj/boardobjgrpmask.c \ @@ -120,7 +125,6 @@ srcs := common/mm/nvgpu_allocator.c \ gk20a/therm_gk20a.c \ gk20a/gr_ctx_gk20a_sim.c \ gk20a/gr_ctx_gk20a.c \ - gk20a/gk20a_gating_reglist.c \ gk20a/fb_gk20a.c \ gk20a/hal.c \ gk20a/tsg_gk20a.c \ @@ -133,7 +137,6 @@ srcs := common/mm/nvgpu_allocator.c \ gm20b/fb_gm20b.c \ gm20b/fifo_gm20b.c \ gm20b/gr_ctx_gm20b.c \ - gm20b/gm20b_gating_reglist.c \ gm20b/acr_gm20b.c \ gm20b/pmu_gm20b.c \ gm20b/mm_gm20b.c \ @@ -151,7 +154,6 @@ srcs := common/mm/nvgpu_allocator.c \ gp10b/pmu_gp10b.c \ gp10b/hal_gp10b.c \ gp10b/rpfb_gp10b.c \ - gp10b/gp10b_gating_reglist.c \ gp10b/regops_gp10b.c \ gp10b/therm_gp10b.c \ gp10b/fecs_trace_gp10b.c \ @@ -163,7 +165,6 @@ srcs := common/mm/nvgpu_allocator.c \ gv11b/mc_gv11b.c \ gv11b/ltc_gv11b.c \ gv11b/hal_gv11b.c \ - gv11b/gv11b_gating_reglist.c \ gv11b/gr_gv11b.c \ gv11b/fb_gv11b.c \ gv11b/fifo_gv11b.c \ @@ -191,7 +192,6 @@ srcs := common/mm/nvgpu_allocator.c \ gp106/fuse_gp106.c \ gp106/clk_gp106.c \ gp106/clk_arb_gp106.c \ - gp106/gp106_gating_reglist.c \ gp106/xve_gp106.c \ gp106/therm_gp106.c \ gv100/mm_gv100.c \ @@ -205,5 +205,4 @@ srcs := common/mm/nvgpu_allocator.c \ gv100/mc_gv100.c \ gv100/nvlink_gv100.c \ gv100/hal_gv100.c \ - gv100/pmu_gv100.c \ - gv100/gv100_gating_reglist.c + gv100/pmu_gv100.c diff --git a/drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.c b/drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.c new file mode 100644 index 00000000..0ebb2d0d --- /dev/null +++ b/drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.c @@ -0,0 +1,731 @@ +/* + * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This file is autogenerated. Do not edit. + */ + +#ifndef __gm20b_gating_reglist_h__ +#define __gm20b_gating_reglist_h__ + +#include "gm20b_gating_reglist.h" +#include + +struct gating_desc { + u32 addr; + u32 prod; + u32 disable; +}; +/* slcg bus */ +static const struct gating_desc gm20b_slcg_bus[] = { + {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, +}; + +/* slcg ce2 */ +static const struct gating_desc gm20b_slcg_ce2[] = { + {.addr = 0x00106f28, .prod = 0x00000000, .disable = 0x000007fe}, +}; + +/* slcg chiplet */ +static const struct gating_desc gm20b_slcg_chiplet[] = { + {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, +}; + +/* slcg fb */ +static const struct gating_desc gm20b_slcg_fb[] = { + {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, +}; + +/* slcg fifo */ +static const struct gating_desc gm20b_slcg_fifo[] = { + {.addr = 0x000026ac, .prod = 0x00000100, .disable = 0x0001fffe}, +}; + +/* slcg gr */ +static const struct gating_desc gm20b_slcg_gr[] = { + {.addr = 0x004041f4, .prod = 0x00000002, .disable = 0x03fffffe}, + {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x0003fffe}, + {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, + {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, + {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x0000007e}, + {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x0003fffe}, + {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, + {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, + {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x0000003e}, + {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, + {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00418c74, .prod = 0xffffffc0, .disable = 0xfffffffe}, + {.addr = 0x00418cf4, .prod = 0xfffffffc, .disable = 0xfffffffe}, + {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, + {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, + {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, + {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, + {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00419d64, .prod = 0x00000000, .disable = 0x000001ff}, + {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e}, + {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e}, + {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e}, + {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e}, + {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e}, + {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e}, + {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e}, + {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, + {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe}, + {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe}, + {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, + {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe}, + {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe}, + {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe}, + {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe}, + {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, + {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, + {.addr = 0x0041bed4, .prod = 0xfffffff6, .disable = 0xfffffffe}, + {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x0040881c, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00408a8c, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00408a94, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00408a9c, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00408aa4, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00408aac, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x000001ff}, +}; + +/* slcg ltc */ +static const struct gating_desc gm20b_slcg_ltc[] = { + {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, +}; + +/* slcg perf */ +static const struct gating_desc gm20b_slcg_perf[] = { + {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000}, + {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000}, + {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000}, + {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000}, +}; + +/* slcg PriRing */ +static const struct gating_desc gm20b_slcg_priring[] = { + {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, +}; + +/* slcg pwr_csb */ +static const struct gating_desc gm20b_slcg_pwr_csb[] = { + {.addr = 0x0000017c, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, + {.addr = 0x00000a74, .prod = 0x00000000, .disable = 0x00007ffe}, + {.addr = 0x000016b8, .prod = 0x00000000, .disable = 0x0000000f}, +}; + +/* slcg pmu */ +static const struct gating_desc gm20b_slcg_pmu[] = { + {.addr = 0x0010a17c, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe}, + {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, +}; + +/* therm gr */ +static const struct gating_desc gm20b_slcg_therm[] = { + {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, +}; + +/* slcg Xbar */ +static const struct gating_desc gm20b_slcg_xbar[] = { + {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, + {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, +}; + +/* blcg bus */ +static const struct gating_desc gm20b_blcg_bus[] = { + {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, +}; + +/* blcg ctxsw prog */ +static const struct gating_desc gm20b_blcg_ctxsw_prog[] = { +}; + +/* blcg fb */ +static const struct gating_desc gm20b_blcg_fb[] = { + {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, + {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00100c98, .prod = 0x00000242, .disable = 0x00000000}, +}; + +/* blcg fifo */ +static const struct gating_desc gm20b_blcg_fifo[] = { + {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000}, +}; + +/* blcg gr */ +static const struct gating_desc gm20b_blcg_gr[] = { + {.addr = 0x004041f0, .prod = 0x00004046, .disable = 0x00000000}, + {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, + {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, + {.addr = 0x004078c0, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x00406000, .prod = 0x00004044, .disable = 0x00000000}, + {.addr = 0x00405860, .prod = 0x00004042, .disable = 0x00000000}, + {.addr = 0x0040590c, .prod = 0x00004044, .disable = 0x00000000}, + {.addr = 0x00408040, .prod = 0x00004044, .disable = 0x00000000}, + {.addr = 0x00407000, .prod = 0x00004041, .disable = 0x00000000}, + {.addr = 0x00405bf0, .prod = 0x00004044, .disable = 0x00000000}, + {.addr = 0x0041a890, .prod = 0x0000007f, .disable = 0x00000000}, + {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, + {.addr = 0x00418500, .prod = 0x00004044, .disable = 0x00000000}, + {.addr = 0x00418608, .prod = 0x00004042, .disable = 0x00000000}, + {.addr = 0x00418688, .prod = 0x00004042, .disable = 0x00000000}, + {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x00418828, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x00418bbc, .prod = 0x00004042, .disable = 0x00000000}, + {.addr = 0x00418970, .prod = 0x00004042, .disable = 0x00000000}, + {.addr = 0x00418c70, .prod = 0x00004044, .disable = 0x00000000}, + {.addr = 0x00418cf0, .prod = 0x00004044, .disable = 0x00000000}, + {.addr = 0x00418d70, .prod = 0x00004044, .disable = 0x00000000}, + {.addr = 0x00418f0c, .prod = 0x00004044, .disable = 0x00000000}, + {.addr = 0x00418e0c, .prod = 0x00004044, .disable = 0x00000000}, + {.addr = 0x00419020, .prod = 0x00004042, .disable = 0x00000000}, + {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x00418898, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x00419a40, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x00419a48, .prod = 0x00004042, .disable = 0x00000000}, + {.addr = 0x00419a50, .prod = 0x00004042, .disable = 0x00000000}, + {.addr = 0x00419a58, .prod = 0x00004042, .disable = 0x00000000}, + {.addr = 0x00419a60, .prod = 0x00004042, .disable = 0x00000000}, + {.addr = 0x00419a68, .prod = 0x00004042, .disable = 0x00000000}, + {.addr = 0x00419a70, .prod = 0x00004042, .disable = 0x00000000}, + {.addr = 0x00419a78, .prod = 0x00004042, .disable = 0x00000000}, + {.addr = 0x00419a80, .prod = 0x00004042, .disable = 0x00000000}, + {.addr = 0x00419868, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000}, + {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000}, + {.addr = 0x00419c70, .prod = 0x00004044, .disable = 0x00000000}, + {.addr = 0x00419fd0, .prod = 0x00004044, .disable = 0x00000000}, + {.addr = 0x00419fd8, .prod = 0x00004046, .disable = 0x00000000}, + {.addr = 0x00419fe0, .prod = 0x00004044, .disable = 0x00000000}, + {.addr = 0x00419fe8, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x00419ff0, .prod = 0x00004045, .disable = 0x00000000}, + {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000}, + {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000}, + {.addr = 0x0041be28, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x0041bfe8, .prod = 0x00004044, .disable = 0x00000000}, + {.addr = 0x0041bed0, .prod = 0x00004044, .disable = 0x00000000}, + {.addr = 0x00408810, .prod = 0x00004042, .disable = 0x00000000}, + {.addr = 0x00408818, .prod = 0x00004042, .disable = 0x00000000}, + {.addr = 0x00408a80, .prod = 0x00004042, .disable = 0x00000000}, + {.addr = 0x00408a88, .prod = 0x00004042, .disable = 0x00000000}, + {.addr = 0x00408a90, .prod = 0x00004042, .disable = 0x00000000}, + {.addr = 0x00408a98, .prod = 0x00004042, .disable = 0x00000000}, + {.addr = 0x00408aa0, .prod = 0x00004042, .disable = 0x00000000}, + {.addr = 0x00408aa8, .prod = 0x00004042, .disable = 0x00000000}, + {.addr = 0x004089a8, .prod = 0x00004042, .disable = 0x00000000}, + {.addr = 0x004089b0, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x004089b8, .prod = 0x00004042, .disable = 0x00000000}, +}; + +/* blcg ltc */ +static const struct gating_desc gm20b_blcg_ltc[] = { + {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, +}; + +/* blcg pwr_csb */ +static const struct gating_desc gm20b_blcg_pwr_csb[] = { + {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, +}; + +/* blcg pmu */ +static const struct gating_desc gm20b_blcg_pmu[] = { + {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, +}; + +/* blcg Xbar */ +static const struct gating_desc gm20b_blcg_xbar[] = { + {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, +}; + +/* pg gr */ +static const struct gating_desc gm20b_pg_gr[] = { +}; + +/* inline functions */ +void gm20b_slcg_bus_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gm20b_slcg_bus) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gm20b_slcg_bus[i].addr, + gm20b_slcg_bus[i].prod); + else + gk20a_writel(g, gm20b_slcg_bus[i].addr, + gm20b_slcg_bus[i].disable); + } +} + +void gm20b_slcg_ce2_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gm20b_slcg_ce2) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gm20b_slcg_ce2[i].addr, + gm20b_slcg_ce2[i].prod); + else + gk20a_writel(g, gm20b_slcg_ce2[i].addr, + gm20b_slcg_ce2[i].disable); + } +} + +void gm20b_slcg_chiplet_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gm20b_slcg_chiplet) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gm20b_slcg_chiplet[i].addr, + gm20b_slcg_chiplet[i].prod); + else + gk20a_writel(g, gm20b_slcg_chiplet[i].addr, + gm20b_slcg_chiplet[i].disable); + } +} + +void gm20b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod) +{ +} + +void gm20b_slcg_fb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gm20b_slcg_fb) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gm20b_slcg_fb[i].addr, + gm20b_slcg_fb[i].prod); + else + gk20a_writel(g, gm20b_slcg_fb[i].addr, + gm20b_slcg_fb[i].disable); + } +} + +void gm20b_slcg_fifo_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gm20b_slcg_fifo) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gm20b_slcg_fifo[i].addr, + gm20b_slcg_fifo[i].prod); + else + gk20a_writel(g, gm20b_slcg_fifo[i].addr, + gm20b_slcg_fifo[i].disable); + } +} + +void gr_gm20b_slcg_gr_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gm20b_slcg_gr) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gm20b_slcg_gr[i].addr, + gm20b_slcg_gr[i].prod); + else + gk20a_writel(g, gm20b_slcg_gr[i].addr, + gm20b_slcg_gr[i].disable); + } +} + +void ltc_gm20b_slcg_ltc_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gm20b_slcg_ltc) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gm20b_slcg_ltc[i].addr, + gm20b_slcg_ltc[i].prod); + else + gk20a_writel(g, gm20b_slcg_ltc[i].addr, + gm20b_slcg_ltc[i].disable); + } +} + +void gm20b_slcg_perf_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gm20b_slcg_perf) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gm20b_slcg_perf[i].addr, + gm20b_slcg_perf[i].prod); + else + gk20a_writel(g, gm20b_slcg_perf[i].addr, + gm20b_slcg_perf[i].disable); + } +} + +void gm20b_slcg_priring_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gm20b_slcg_priring) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gm20b_slcg_priring[i].addr, + gm20b_slcg_priring[i].prod); + else + gk20a_writel(g, gm20b_slcg_priring[i].addr, + gm20b_slcg_priring[i].disable); + } +} + +void gm20b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gm20b_slcg_pwr_csb) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gm20b_slcg_pwr_csb[i].addr, + gm20b_slcg_pwr_csb[i].prod); + else + gk20a_writel(g, gm20b_slcg_pwr_csb[i].addr, + gm20b_slcg_pwr_csb[i].disable); + } +} + +void gm20b_slcg_pmu_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gm20b_slcg_pmu) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gm20b_slcg_pmu[i].addr, + gm20b_slcg_pmu[i].prod); + else + gk20a_writel(g, gm20b_slcg_pmu[i].addr, + gm20b_slcg_pmu[i].disable); + } +} + +void gm20b_slcg_therm_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gm20b_slcg_therm) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gm20b_slcg_therm[i].addr, + gm20b_slcg_therm[i].prod); + else + gk20a_writel(g, gm20b_slcg_therm[i].addr, + gm20b_slcg_therm[i].disable); + } +} + +void gm20b_slcg_xbar_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gm20b_slcg_xbar) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gm20b_slcg_xbar[i].addr, + gm20b_slcg_xbar[i].prod); + else + gk20a_writel(g, gm20b_slcg_xbar[i].addr, + gm20b_slcg_xbar[i].disable); + } +} + +void gm20b_blcg_bus_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gm20b_blcg_bus) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gm20b_blcg_bus[i].addr, + gm20b_blcg_bus[i].prod); + else + gk20a_writel(g, gm20b_blcg_bus[i].addr, + gm20b_blcg_bus[i].disable); + } +} + +void gm20b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gm20b_blcg_ctxsw_prog) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gm20b_blcg_ctxsw_prog[i].addr, + gm20b_blcg_ctxsw_prog[i].prod); + else + gk20a_writel(g, gm20b_blcg_ctxsw_prog[i].addr, + gm20b_blcg_ctxsw_prog[i].disable); + } +} + +void gm20b_blcg_fb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gm20b_blcg_fb) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gm20b_blcg_fb[i].addr, + gm20b_blcg_fb[i].prod); + else + gk20a_writel(g, gm20b_blcg_fb[i].addr, + gm20b_blcg_fb[i].disable); + } +} + +void gm20b_blcg_fifo_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gm20b_blcg_fifo) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gm20b_blcg_fifo[i].addr, + gm20b_blcg_fifo[i].prod); + else + gk20a_writel(g, gm20b_blcg_fifo[i].addr, + gm20b_blcg_fifo[i].disable); + } +} + +void gm20b_blcg_gr_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gm20b_blcg_gr) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gm20b_blcg_gr[i].addr, + gm20b_blcg_gr[i].prod); + else + gk20a_writel(g, gm20b_blcg_gr[i].addr, + gm20b_blcg_gr[i].disable); + } +} + +void gm20b_blcg_ltc_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gm20b_blcg_ltc) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gm20b_blcg_ltc[i].addr, + gm20b_blcg_ltc[i].prod); + else + gk20a_writel(g, gm20b_blcg_ltc[i].addr, + gm20b_blcg_ltc[i].disable); + } +} + +void gm20b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gm20b_blcg_pwr_csb) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gm20b_blcg_pwr_csb[i].addr, + gm20b_blcg_pwr_csb[i].prod); + else + gk20a_writel(g, gm20b_blcg_pwr_csb[i].addr, + gm20b_blcg_pwr_csb[i].disable); + } +} + +void gm20b_blcg_pmu_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gm20b_blcg_pmu) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gm20b_blcg_pmu[i].addr, + gm20b_blcg_pmu[i].prod); + else + gk20a_writel(g, gm20b_blcg_pmu[i].addr, + gm20b_blcg_pmu[i].disable); + } +} + +void gm20b_blcg_xbar_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gm20b_blcg_xbar) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gm20b_blcg_xbar[i].addr, + gm20b_blcg_xbar[i].prod); + else + gk20a_writel(g, gm20b_blcg_xbar[i].addr, + gm20b_blcg_xbar[i].disable); + } +} + +void gr_gm20b_pg_gr_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gm20b_pg_gr) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gm20b_pg_gr[i].addr, + gm20b_pg_gr[i].prod); + else + gk20a_writel(g, gm20b_pg_gr[i].addr, + gm20b_pg_gr[i].disable); + } +} + +#endif /* __gm20b_gating_reglist_h__ */ diff --git a/drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.h b/drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.h new file mode 100644 index 00000000..557f5689 --- /dev/null +++ b/drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.h @@ -0,0 +1,100 @@ +/* + * drivers/video/tegra/host/gm20b/gm20b_gating_reglist.h + * + * Copyright (c) 2014-2015, NVIDIA Corporation. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This file is autogenerated. Do not edit. + */ + +#include "gk20a/gk20a.h" + +void gm20b_slcg_bus_load_gating_prod(struct gk20a *g, + bool prod); + +void gm20b_slcg_ce2_load_gating_prod(struct gk20a *g, + bool prod); + +void gm20b_slcg_chiplet_load_gating_prod(struct gk20a *g, + bool prod); + +void gm20b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod); + +void gm20b_slcg_fb_load_gating_prod(struct gk20a *g, + bool prod); + +void gm20b_slcg_fifo_load_gating_prod(struct gk20a *g, + bool prod); + +void gr_gm20b_slcg_gr_load_gating_prod(struct gk20a *g, + bool prod); + +void ltc_gm20b_slcg_ltc_load_gating_prod(struct gk20a *g, + bool prod); + +void gm20b_slcg_perf_load_gating_prod(struct gk20a *g, + bool prod); + +void gm20b_slcg_priring_load_gating_prod(struct gk20a *g, + bool prod); + +void gm20b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, + bool prod); + +void gm20b_slcg_pmu_load_gating_prod(struct gk20a *g, + bool prod); + +void gm20b_slcg_therm_load_gating_prod(struct gk20a *g, + bool prod); + +void gm20b_slcg_xbar_load_gating_prod(struct gk20a *g, + bool prod); + +void gm20b_blcg_bus_load_gating_prod(struct gk20a *g, + bool prod); + +void gm20b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod); + +void gm20b_blcg_fb_load_gating_prod(struct gk20a *g, + bool prod); + +void gm20b_blcg_fifo_load_gating_prod(struct gk20a *g, + bool prod); + +void gm20b_blcg_gr_load_gating_prod(struct gk20a *g, + bool prod); + +void gm20b_blcg_ltc_load_gating_prod(struct gk20a *g, + bool prod); + +void gm20b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, + bool prod); + +void gm20b_blcg_pmu_load_gating_prod(struct gk20a *g, + bool prod); + +void gm20b_blcg_xbar_load_gating_prod(struct gk20a *g, + bool prod); + +void gr_gm20b_pg_gr_load_gating_prod(struct gk20a *g, + bool prod); + diff --git a/drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.c b/drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.c new file mode 100644 index 00000000..169a1fee --- /dev/null +++ b/drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.c @@ -0,0 +1,679 @@ +/* + * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This file is autogenerated. Do not edit. + */ + +#ifndef __gp106_gating_reglist_h__ +#define __gp106_gating_reglist_h__ + +#include "gp106_gating_reglist.h" +#include + +struct gating_desc { + u32 addr; + u32 prod; + u32 disable; +}; +/* slcg bus */ +static const struct gating_desc gp106_slcg_bus[] = { + {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, +}; + +/* slcg ce2 */ +static const struct gating_desc gp106_slcg_ce2[] = { + {.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe}, +}; + +/* slcg chiplet */ +static const struct gating_desc gp106_slcg_chiplet[] = { + {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010c0fc, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010d0fc, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, +}; + +/* slcg fb */ +static const struct gating_desc gp106_slcg_fb[] = { + {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, +}; + +/* slcg fifo */ +static const struct gating_desc gp106_slcg_fifo[] = { + {.addr = 0x000026ac, .prod = 0x00000000, .disable = 0x0001fffe}, +}; + +/* slcg gr */ +static const struct gating_desc gp106_slcg_gr[] = { + {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe}, + {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe}, + {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, + {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, + {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x03fffffe}, + {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, + {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, + {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe}, + {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, + {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe}, + {.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe}, + {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, + {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, + {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, + {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, + {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x0000ffff}, + {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e}, + {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e}, + {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e}, + {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e}, + {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e}, + {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e}, + {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e}, + {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, + {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe}, + {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe}, + {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, + {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe}, + {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe}, + {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe}, + {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe}, + {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, + {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, + {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, + {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x0000ffff}, +}; + +/* slcg ltc */ +static const struct gating_desc gp106_slcg_ltc[] = { + {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, +}; + +/* slcg perf */ +static const struct gating_desc gp106_slcg_perf[] = { + {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000}, + {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000}, + {.addr = 0x001bc218, .prod = 0x000001ff, .disable = 0x00000000}, + {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000}, + {.addr = 0x001b8218, .prod = 0x000001ff, .disable = 0x00000000}, + {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000}, +}; + +/* slcg PriRing */ +static const struct gating_desc gp106_slcg_priring[] = { + {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, +}; + +/* slcg pmu */ +static const struct gating_desc gp106_slcg_pmu[] = { + {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe}, + {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, +}; + +/* therm gr */ +static const struct gating_desc gp106_slcg_therm[] = { + {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, +}; + +/* slcg Xbar */ +static const struct gating_desc gp106_slcg_xbar[] = { + {.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe}, + {.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe}, + {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, + {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, + {.addr = 0x0013cc24, .prod = 0x00000000, .disable = 0x1ffffffe}, +}; + +/* blcg bus */ +static const struct gating_desc gp106_blcg_bus[] = { + {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, +}; + +/* blcg ce */ +static const struct gating_desc gp106_blcg_ce[] = { + {.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000}, +}; + +/* blcg fb */ +static const struct gating_desc gp106_blcg_fb[] = { + {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, + {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, +}; + +/* blcg fifo */ +static const struct gating_desc gp106_blcg_fifo[] = { + {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000}, +}; + +/* blcg gr */ +static const struct gating_desc gp106_blcg_gr[] = { + {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, + {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, + {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, + {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, + {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, + {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, + {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, + {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, + {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, + {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00418e0c, .prod = 0x00008444, .disable = 0x00000000}, + {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, + {.addr = 0x00419a40, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419a48, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419a50, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419a58, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419a60, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419a68, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419a70, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419a78, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419a80, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000}, + {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000}, + {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000}, + {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00419fd0, .prod = 0x0000c044, .disable = 0x00000000}, + {.addr = 0x00419fd8, .prod = 0x0000c046, .disable = 0x00000000}, + {.addr = 0x00419fe0, .prod = 0x0000c044, .disable = 0x00000000}, + {.addr = 0x00419fe8, .prod = 0x0000c042, .disable = 0x00000000}, + {.addr = 0x00419ff0, .prod = 0x0000c045, .disable = 0x00000000}, + {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000}, + {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000}, + {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, + {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, +}; + +/* blcg ltc */ +static const struct gating_desc gp106_blcg_ltc[] = { + {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, +}; + +/* blcg pmu */ +static const struct gating_desc gp106_blcg_pmu[] = { + {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, +}; + +/* blcg Xbar */ +static const struct gating_desc gp106_blcg_xbar[] = { + {.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000}, + {.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000}, + {.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000}, + {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x0013cc20, .prod = 0x00000042, .disable = 0x00000000}, +}; + +/* pg gr */ +static const struct gating_desc gp106_pg_gr[] = { +}; + +/* inline functions */ +void gp106_slcg_bus_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp106_slcg_bus) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp106_slcg_bus[i].addr, + gp106_slcg_bus[i].prod); + else + gk20a_writel(g, gp106_slcg_bus[i].addr, + gp106_slcg_bus[i].disable); + } +} + +void gp106_slcg_ce2_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp106_slcg_ce2) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp106_slcg_ce2[i].addr, + gp106_slcg_ce2[i].prod); + else + gk20a_writel(g, gp106_slcg_ce2[i].addr, + gp106_slcg_ce2[i].disable); + } +} + +void gp106_slcg_chiplet_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp106_slcg_chiplet) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp106_slcg_chiplet[i].addr, + gp106_slcg_chiplet[i].prod); + else + gk20a_writel(g, gp106_slcg_chiplet[i].addr, + gp106_slcg_chiplet[i].disable); + } +} + +void gp106_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod) +{ +} + +void gp106_slcg_fb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp106_slcg_fb) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp106_slcg_fb[i].addr, + gp106_slcg_fb[i].prod); + else + gk20a_writel(g, gp106_slcg_fb[i].addr, + gp106_slcg_fb[i].disable); + } +} + +void gp106_slcg_fifo_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp106_slcg_fifo) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp106_slcg_fifo[i].addr, + gp106_slcg_fifo[i].prod); + else + gk20a_writel(g, gp106_slcg_fifo[i].addr, + gp106_slcg_fifo[i].disable); + } +} + +void gr_gp106_slcg_gr_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp106_slcg_gr) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp106_slcg_gr[i].addr, + gp106_slcg_gr[i].prod); + else + gk20a_writel(g, gp106_slcg_gr[i].addr, + gp106_slcg_gr[i].disable); + } +} + +void ltc_gp106_slcg_ltc_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp106_slcg_ltc) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp106_slcg_ltc[i].addr, + gp106_slcg_ltc[i].prod); + else + gk20a_writel(g, gp106_slcg_ltc[i].addr, + gp106_slcg_ltc[i].disable); + } +} + +void gp106_slcg_perf_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp106_slcg_perf) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp106_slcg_perf[i].addr, + gp106_slcg_perf[i].prod); + else + gk20a_writel(g, gp106_slcg_perf[i].addr, + gp106_slcg_perf[i].disable); + } +} + +void gp106_slcg_priring_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp106_slcg_priring) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp106_slcg_priring[i].addr, + gp106_slcg_priring[i].prod); + else + gk20a_writel(g, gp106_slcg_priring[i].addr, + gp106_slcg_priring[i].disable); + } +} + +void gp106_slcg_pmu_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp106_slcg_pmu) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp106_slcg_pmu[i].addr, + gp106_slcg_pmu[i].prod); + else + gk20a_writel(g, gp106_slcg_pmu[i].addr, + gp106_slcg_pmu[i].disable); + } +} + +void gp106_slcg_therm_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp106_slcg_therm) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp106_slcg_therm[i].addr, + gp106_slcg_therm[i].prod); + else + gk20a_writel(g, gp106_slcg_therm[i].addr, + gp106_slcg_therm[i].disable); + } +} + +void gp106_slcg_xbar_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp106_slcg_xbar) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp106_slcg_xbar[i].addr, + gp106_slcg_xbar[i].prod); + else + gk20a_writel(g, gp106_slcg_xbar[i].addr, + gp106_slcg_xbar[i].disable); + } +} + +void gp106_blcg_bus_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp106_blcg_bus) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp106_blcg_bus[i].addr, + gp106_blcg_bus[i].prod); + else + gk20a_writel(g, gp106_blcg_bus[i].addr, + gp106_blcg_bus[i].disable); + } +} + +void gp106_blcg_ce_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp106_blcg_ce) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp106_blcg_ce[i].addr, + gp106_blcg_ce[i].prod); + else + gk20a_writel(g, gp106_blcg_ce[i].addr, + gp106_blcg_ce[i].disable); + } +} + +void gp106_blcg_fb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp106_blcg_fb) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp106_blcg_fb[i].addr, + gp106_blcg_fb[i].prod); + else + gk20a_writel(g, gp106_blcg_fb[i].addr, + gp106_blcg_fb[i].disable); + } +} + +void gp106_blcg_fifo_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp106_blcg_fifo) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp106_blcg_fifo[i].addr, + gp106_blcg_fifo[i].prod); + else + gk20a_writel(g, gp106_blcg_fifo[i].addr, + gp106_blcg_fifo[i].disable); + } +} + +void gp106_blcg_gr_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp106_blcg_gr) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp106_blcg_gr[i].addr, + gp106_blcg_gr[i].prod); + else + gk20a_writel(g, gp106_blcg_gr[i].addr, + gp106_blcg_gr[i].disable); + } +} + +void gp106_blcg_ltc_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp106_blcg_ltc) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp106_blcg_ltc[i].addr, + gp106_blcg_ltc[i].prod); + else + gk20a_writel(g, gp106_blcg_ltc[i].addr, + gp106_blcg_ltc[i].disable); + } +} + +void gp106_blcg_pmu_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp106_blcg_pmu) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp106_blcg_pmu[i].addr, + gp106_blcg_pmu[i].prod); + else + gk20a_writel(g, gp106_blcg_pmu[i].addr, + gp106_blcg_pmu[i].disable); + } +} + +void gp106_blcg_xbar_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp106_blcg_xbar) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp106_blcg_xbar[i].addr, + gp106_blcg_xbar[i].prod); + else + gk20a_writel(g, gp106_blcg_xbar[i].addr, + gp106_blcg_xbar[i].disable); + } +} + +void gr_gp106_pg_gr_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp106_pg_gr) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp106_pg_gr[i].addr, + gp106_pg_gr[i].prod); + else + gk20a_writel(g, gp106_pg_gr[i].addr, + gp106_pg_gr[i].disable); + } +} + +#endif /* __gp106_gating_reglist_h__ */ diff --git a/drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.h b/drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.h new file mode 100644 index 00000000..773abde6 --- /dev/null +++ b/drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2015-2016, NVIDIA Corporation. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gk20a/gk20a.h" + +void gp106_slcg_bus_load_gating_prod(struct gk20a *g, + bool prod); + +void gp106_slcg_ce2_load_gating_prod(struct gk20a *g, + bool prod); + +void gp106_slcg_chiplet_load_gating_prod(struct gk20a *g, + bool prod); + +void gp106_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod); + +void gp106_slcg_fb_load_gating_prod(struct gk20a *g, + bool prod); + +void gp106_slcg_fifo_load_gating_prod(struct gk20a *g, + bool prod); + +void gr_gp106_slcg_gr_load_gating_prod(struct gk20a *g, + bool prod); + +void ltc_gp106_slcg_ltc_load_gating_prod(struct gk20a *g, + bool prod); + +void gp106_slcg_perf_load_gating_prod(struct gk20a *g, + bool prod); + +void gp106_slcg_priring_load_gating_prod(struct gk20a *g, + bool prod); + +void gp106_slcg_pmu_load_gating_prod(struct gk20a *g, + bool prod); + +void gp106_slcg_therm_load_gating_prod(struct gk20a *g, + bool prod); + +void gp106_slcg_xbar_load_gating_prod(struct gk20a *g, + bool prod); + +void gp106_blcg_bus_load_gating_prod(struct gk20a *g, + bool prod); + +void gp106_blcg_ce_load_gating_prod(struct gk20a *g, + bool prod); + +void gp106_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod); + +void gp106_blcg_fb_load_gating_prod(struct gk20a *g, + bool prod); + +void gp106_blcg_fifo_load_gating_prod(struct gk20a *g, + bool prod); + +void gp106_blcg_gr_load_gating_prod(struct gk20a *g, + bool prod); + +void gp106_blcg_ltc_load_gating_prod(struct gk20a *g, + bool prod); + +void gp106_blcg_pmu_load_gating_prod(struct gk20a *g, + bool prod); + +void gp106_blcg_xbar_load_gating_prod(struct gk20a *g, + bool prod); + +void gr_gp106_pg_gr_load_gating_prod(struct gk20a *g, + bool prod); + diff --git a/drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.c b/drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.c new file mode 100644 index 00000000..4355f698 --- /dev/null +++ b/drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.c @@ -0,0 +1,742 @@ +/* + * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This file is autogenerated. Do not edit. + */ + +#ifndef __gp10b_gating_reglist_h__ +#define __gp10b_gating_reglist_h__ + +#include "gp10b_gating_reglist.h" +#include + +struct gating_desc { + u32 addr; + u32 prod; + u32 disable; +}; +/* slcg bus */ +static const struct gating_desc gp10b_slcg_bus[] = { + {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, +}; + +/* slcg ce2 */ +static const struct gating_desc gp10b_slcg_ce2[] = { + {.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe}, +}; + +/* slcg chiplet */ +static const struct gating_desc gp10b_slcg_chiplet[] = { + {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, +}; + +/* slcg fb */ +static const struct gating_desc gp10b_slcg_fb[] = { + {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, +}; + +/* slcg fifo */ +static const struct gating_desc gp10b_slcg_fifo[] = { + {.addr = 0x000026ac, .prod = 0x00000f40, .disable = 0x0001fffe}, +}; + +/* slcg gr */ +static const struct gating_desc gp10b_slcg_gr[] = { + {.addr = 0x004041f4, .prod = 0x00000002, .disable = 0x03fffffe}, + {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe}, + {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00406004, .prod = 0x00000200, .disable = 0x0001fffe}, + {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, + {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, + {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x03fffffe}, + {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, + {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, + {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x0000003e}, + {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, + {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00418c74, .prod = 0xffffffc0, .disable = 0xfffffffe}, + {.addr = 0x00418cf4, .prod = 0xfffffffc, .disable = 0xfffffffe}, + {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, + {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, + {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, + {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, + {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x0000ffff}, + {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e}, + {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e}, + {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e}, + {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e}, + {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e}, + {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e}, + {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e}, + {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, + {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe}, + {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe}, + {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, + {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe}, + {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe}, + {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe}, + {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe}, + {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, + {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, + {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, + {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x0000ffff}, +}; + +/* slcg ltc */ +static const struct gating_desc gp10b_slcg_ltc[] = { + {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, +}; + +/* slcg perf */ +static const struct gating_desc gp10b_slcg_perf[] = { + {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000}, + {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000}, + {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000}, + {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000}, +}; + +/* slcg PriRing */ +static const struct gating_desc gp10b_slcg_priring[] = { + {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, +}; + +/* slcg pwr_csb */ +static const struct gating_desc gp10b_slcg_pwr_csb[] = { + {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, + {.addr = 0x00000a74, .prod = 0x00004000, .disable = 0x00007ffe}, + {.addr = 0x000016b8, .prod = 0x00000000, .disable = 0x0000000f}, +}; + +/* slcg pmu */ +static const struct gating_desc gp10b_slcg_pmu[] = { + {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x0010aa74, .prod = 0x00004000, .disable = 0x00007ffe}, + {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, +}; + +/* therm gr */ +static const struct gating_desc gp10b_slcg_therm[] = { + {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, +}; + +/* slcg Xbar */ +static const struct gating_desc gp10b_slcg_xbar[] = { + {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, + {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, +}; + +/* blcg bus */ +static const struct gating_desc gp10b_blcg_bus[] = { + {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, +}; + +/* blcg ce */ +static const struct gating_desc gp10b_blcg_ce[] = { + {.addr = 0x00104200, .prod = 0x00008242, .disable = 0x00000000}, +}; + +/* blcg ctxsw prog */ +static const struct gating_desc gp10b_blcg_ctxsw_prog[] = { +}; + +/* blcg fb */ +static const struct gating_desc gp10b_blcg_fb[] = { + {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, + {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, +}; + +/* blcg fifo */ +static const struct gating_desc gp10b_blcg_fifo[] = { + {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000}, +}; + +/* blcg gr */ +static const struct gating_desc gp10b_blcg_gr[] = { + {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, + {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, + {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, + {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, + {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, + /* fix priv error */ + /*{.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000},*/ + {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, + {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, + {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, + {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, + {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00418e0c, .prod = 0x00008444, .disable = 0x00000000}, + {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, + {.addr = 0x00419a40, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419a48, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419a50, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419a58, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419a60, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419a68, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419a70, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419a78, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419a80, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000}, + {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000}, + {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000}, + {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00419fd0, .prod = 0x0000c044, .disable = 0x00000000}, + {.addr = 0x00419fd8, .prod = 0x0000c046, .disable = 0x00000000}, + {.addr = 0x00419fe0, .prod = 0x0000c044, .disable = 0x00000000}, + {.addr = 0x00419fe8, .prod = 0x0000c042, .disable = 0x00000000}, + {.addr = 0x00419ff0, .prod = 0x0000c045, .disable = 0x00000000}, + {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000}, + {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000}, + {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, + {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, +}; + +/* blcg ltc */ +static const struct gating_desc gp10b_blcg_ltc[] = { + {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, +}; + +/* blcg pwr_csb */ +static const struct gating_desc gp10b_blcg_pwr_csb[] = { + {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, +}; + +/* blcg pmu */ +static const struct gating_desc gp10b_blcg_pmu[] = { + {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, +}; + +/* blcg Xbar */ +static const struct gating_desc gp10b_blcg_xbar[] = { + {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, +}; + +/* pg gr */ +static const struct gating_desc gp10b_pg_gr[] = { +}; + +/* inline functions */ +void gp10b_slcg_bus_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_bus) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_bus[i].addr, + gp10b_slcg_bus[i].prod); + else + gk20a_writel(g, gp10b_slcg_bus[i].addr, + gp10b_slcg_bus[i].disable); + } +} + +void gp10b_slcg_ce2_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_ce2) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_ce2[i].addr, + gp10b_slcg_ce2[i].prod); + else + gk20a_writel(g, gp10b_slcg_ce2[i].addr, + gp10b_slcg_ce2[i].disable); + } +} + +void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_chiplet) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_chiplet[i].addr, + gp10b_slcg_chiplet[i].prod); + else + gk20a_writel(g, gp10b_slcg_chiplet[i].addr, + gp10b_slcg_chiplet[i].disable); + } +} + +void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod) +{ +} + +void gp10b_slcg_fb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_fb) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_fb[i].addr, + gp10b_slcg_fb[i].prod); + else + gk20a_writel(g, gp10b_slcg_fb[i].addr, + gp10b_slcg_fb[i].disable); + } +} + +void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_fifo) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_fifo[i].addr, + gp10b_slcg_fifo[i].prod); + else + gk20a_writel(g, gp10b_slcg_fifo[i].addr, + gp10b_slcg_fifo[i].disable); + } +} + +void gr_gp10b_slcg_gr_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_gr) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_gr[i].addr, + gp10b_slcg_gr[i].prod); + else + gk20a_writel(g, gp10b_slcg_gr[i].addr, + gp10b_slcg_gr[i].disable); + } +} + +void ltc_gp10b_slcg_ltc_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_ltc) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_ltc[i].addr, + gp10b_slcg_ltc[i].prod); + else + gk20a_writel(g, gp10b_slcg_ltc[i].addr, + gp10b_slcg_ltc[i].disable); + } +} + +void gp10b_slcg_perf_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_perf) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_perf[i].addr, + gp10b_slcg_perf[i].prod); + else + gk20a_writel(g, gp10b_slcg_perf[i].addr, + gp10b_slcg_perf[i].disable); + } +} + +void gp10b_slcg_priring_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_priring) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_priring[i].addr, + gp10b_slcg_priring[i].prod); + else + gk20a_writel(g, gp10b_slcg_priring[i].addr, + gp10b_slcg_priring[i].disable); + } +} + +void gp10b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_pwr_csb) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr, + gp10b_slcg_pwr_csb[i].prod); + else + gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr, + gp10b_slcg_pwr_csb[i].disable); + } +} + +void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_pmu) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_pmu[i].addr, + gp10b_slcg_pmu[i].prod); + else + gk20a_writel(g, gp10b_slcg_pmu[i].addr, + gp10b_slcg_pmu[i].disable); + } +} + +void gp10b_slcg_therm_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_therm) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_therm[i].addr, + gp10b_slcg_therm[i].prod); + else + gk20a_writel(g, gp10b_slcg_therm[i].addr, + gp10b_slcg_therm[i].disable); + } +} + +void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_xbar) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_xbar[i].addr, + gp10b_slcg_xbar[i].prod); + else + gk20a_writel(g, gp10b_slcg_xbar[i].addr, + gp10b_slcg_xbar[i].disable); + } +} + +void gp10b_blcg_bus_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_blcg_bus) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_blcg_bus[i].addr, + gp10b_blcg_bus[i].prod); + else + gk20a_writel(g, gp10b_blcg_bus[i].addr, + gp10b_blcg_bus[i].disable); + } +} + +void gp10b_blcg_ce_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_blcg_ce) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_blcg_ce[i].addr, + gp10b_blcg_ce[i].prod); + else + gk20a_writel(g, gp10b_blcg_ce[i].addr, + gp10b_blcg_ce[i].disable); + } +} + +void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_blcg_ctxsw_prog) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr, + gp10b_blcg_ctxsw_prog[i].prod); + else + gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr, + gp10b_blcg_ctxsw_prog[i].disable); + } +} + +void gp10b_blcg_fb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_blcg_fb) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_blcg_fb[i].addr, + gp10b_blcg_fb[i].prod); + else + gk20a_writel(g, gp10b_blcg_fb[i].addr, + gp10b_blcg_fb[i].disable); + } +} + +void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_blcg_fifo) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_blcg_fifo[i].addr, + gp10b_blcg_fifo[i].prod); + else + gk20a_writel(g, gp10b_blcg_fifo[i].addr, + gp10b_blcg_fifo[i].disable); + } +} + +void gp10b_blcg_gr_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_blcg_gr) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_blcg_gr[i].addr, + gp10b_blcg_gr[i].prod); + else + gk20a_writel(g, gp10b_blcg_gr[i].addr, + gp10b_blcg_gr[i].disable); + } +} + +void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_blcg_ltc) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_blcg_ltc[i].addr, + gp10b_blcg_ltc[i].prod); + else + gk20a_writel(g, gp10b_blcg_ltc[i].addr, + gp10b_blcg_ltc[i].disable); + } +} + +void gp10b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_blcg_pwr_csb) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr, + gp10b_blcg_pwr_csb[i].prod); + else + gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr, + gp10b_blcg_pwr_csb[i].disable); + } +} + +void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_blcg_pmu) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_blcg_pmu[i].addr, + gp10b_blcg_pmu[i].prod); + else + gk20a_writel(g, gp10b_blcg_pmu[i].addr, + gp10b_blcg_pmu[i].disable); + } +} + +void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_blcg_xbar) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_blcg_xbar[i].addr, + gp10b_blcg_xbar[i].prod); + else + gk20a_writel(g, gp10b_blcg_xbar[i].addr, + gp10b_blcg_xbar[i].disable); + } +} + +void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_pg_gr) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_pg_gr[i].addr, + gp10b_pg_gr[i].prod); + else + gk20a_writel(g, gp10b_pg_gr[i].addr, + gp10b_pg_gr[i].disable); + } +} + +#endif /* __gp10b_gating_reglist_h__ */ diff --git a/drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.h b/drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.h new file mode 100644 index 00000000..7dbc6cac --- /dev/null +++ b/drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2015-2016, NVIDIA Corporation. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gk20a/gk20a.h" + +void gp10b_slcg_bus_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_slcg_ce2_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_slcg_fb_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g, + bool prod); + +void gr_gp10b_slcg_gr_load_gating_prod(struct gk20a *g, + bool prod); + +void ltc_gp10b_slcg_ltc_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_slcg_perf_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_slcg_priring_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_slcg_therm_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_blcg_bus_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_blcg_ce_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_blcg_fb_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_blcg_gr_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g, + bool prod); + +void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g, + bool prod); + diff --git a/drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.c b/drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.c new file mode 100644 index 00000000..60ec0282 --- /dev/null +++ b/drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.c @@ -0,0 +1,951 @@ +/* + * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * This file is autogenerated. Do not edit. + */ + +#ifndef __gv100_gating_reglist_h__ +#define __gv100_gating_reglist_h__ + +#include +#include "gv100_gating_reglist.h" + +struct gating_desc { + u32 addr; + u32 prod; + u32 disable; +}; +/* slcg bus */ +static const struct gating_desc gv100_slcg_bus[] = { + {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, +}; + +/* slcg ce2 */ +static const struct gating_desc gv100_slcg_ce2[] = { + {.addr = 0x00104204, .prod = 0x00000040, .disable = 0x000007fe}, +}; + +/* slcg chiplet */ +static const struct gating_desc gv100_slcg_chiplet[] = { + {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010c17c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010c27c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010c37c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010c47c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010c57c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010d17c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010d27c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010d37c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010d47c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010d57c, .prod = 0x00000000, .disable = 0x00000007}, + /* fix priv error */ + /*{.addr = 0x0010d67c, .prod = 0x00000000, .disable = 0x00000007},*/ + /*{.addr = 0x0010d77c, .prod = 0x00000000, .disable = 0x00000007},*/ + {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, +}; + +/* slcg fb */ +static const struct gating_desc gv100_slcg_fb[] = { + {.addr = 0x00100d14, .prod = 0x00000020, .disable = 0xfffffffe}, + {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x001facb4, .prod = 0x00000000, .disable = 0x000001fe}, +}; + +/* slcg fifo */ +static const struct gating_desc gv100_slcg_fifo[] = { + {.addr = 0x000026ec, .prod = 0x00000000, .disable = 0x0001fffe}, +}; + +/* slcg gr */ +static const struct gating_desc gv100_slcg_gr[] = { + {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe}, + {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x00409894, .prod = 0x00000000, .disable = 0x0000fffe}, + {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00406004, .prod = 0x00000200, .disable = 0x0001fffe}, + {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, + {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, + {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00405bf4, .prod = 0x00000000, .disable = 0x00000002}, + {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x0041a894, .prod = 0x00000000, .disable = 0x0000fffe}, + {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, + {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, + {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe}, + {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, + {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe}, + {.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe}, + {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, + {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, + {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, + {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, + {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x000000ff}, + {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, + {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, + /* fix priv error */ + /*{.addr = 0x00419c84, .prod = 0x0003fffe, .disable = 0x0003fffe},*/ + {.addr = 0x00419c8c, .prod = 0xffffff84, .disable = 0xfffffffe}, + {.addr = 0x00419c94, .prod = 0x00000240, .disable = 0x00007ffe}, + {.addr = 0x00419ca4, .prod = 0x00003ffe, .disable = 0x00003ffe}, + {.addr = 0x00419cac, .prod = 0x0001fffe, .disable = 0x0001fffe}, + {.addr = 0x00419a44, .prod = 0x00000008, .disable = 0x0000000e}, + {.addr = 0x00419a4c, .prod = 0x000001f8, .disable = 0x000001fe}, + {.addr = 0x00419a54, .prod = 0x0000003c, .disable = 0x0000003e}, + {.addr = 0x00419a5c, .prod = 0x0000000c, .disable = 0x0000000e}, + {.addr = 0x00419a64, .prod = 0x00000186, .disable = 0x000001fe}, + {.addr = 0x00419a7c, .prod = 0x0000003c, .disable = 0x0000003e}, + {.addr = 0x00419a84, .prod = 0x0000000c, .disable = 0x0000000e}, + {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, + {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, + {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, + {.addr = 0x00412814, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00412a84, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x004129ac, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00412a24, .prod = 0x00000000, .disable = 0x000000ff}, + {.addr = 0x00412c14, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00412e84, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00412dac, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00412e24, .prod = 0x00000000, .disable = 0x000000ff}, + /* fix priv error */ + /*{.addr = 0x00413014, .prod = 0x00000000, .disable = 0x0001fffe},*/ + /*{.addr = 0x00413284, .prod = 0x00000000, .disable = 0x0001fffe},*/ + /*{.addr = 0x004131ac, .prod = 0x00000000, .disable = 0x0001fffe},*/ + /*{.addr = 0x00413224, .prod = 0x00000000, .disable = 0x000000ff},*/ + /*{.addr = 0x00413414, .prod = 0x00000000, .disable = 0x0001fffe},*/ + /*{.addr = 0x00413684, .prod = 0x00000000, .disable = 0x0001fffe},*/ + /*{.addr = 0x004135ac, .prod = 0x00000000, .disable = 0x0001fffe},*/ + /*{.addr = 0x00413624, .prod = 0x00000000, .disable = 0x000000ff},*/ + /*{.addr = 0x00413814, .prod = 0x00000000, .disable = 0x0001fffe},*/ + /*{.addr = 0x00413a84, .prod = 0x00000000, .disable = 0x0001fffe},*/ + /*{.addr = 0x004139ac, .prod = 0x00000000, .disable = 0x0001fffe},*/ + /*{.addr = 0x00413a24, .prod = 0x00000000, .disable = 0x000000ff},*/ + /*{.addr = 0x00413c14, .prod = 0x00000000, .disable = 0x0001fffe},*/ + /*{.addr = 0x00413e84, .prod = 0x00000000, .disable = 0x0001fffe},*/ + /*{.addr = 0x00413dac, .prod = 0x00000000, .disable = 0x0001fffe},*/ + /*{.addr = 0x00413e24, .prod = 0x00000000, .disable = 0x000000ff},*/ + {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x000000ff}, +}; + +/* slcg ltc */ +static const struct gating_desc gv100_slcg_ltc[] = { + {.addr = 0x00154050, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x0015455c, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x0015475c, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x0015495c, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x00154b5c, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x0015435c, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x00156050, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x0015655c, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x0015675c, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x0015695c, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x00156b5c, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x0015635c, .prod = 0x00000000, .disable = 0xfffffffe}, + /* fix priv error */ + /*{.addr = 0x00158050, .prod = 0x00000000, .disable = 0xfffffffe},*/ + /*{.addr = 0x0015855c, .prod = 0x00000000, .disable = 0xfffffffe},*/ + /*{.addr = 0x0015875c, .prod = 0x00000000, .disable = 0xfffffffe},*/ + /*{.addr = 0x0015895c, .prod = 0x00000000, .disable = 0xfffffffe},*/ + /*{.addr = 0x00158b5c, .prod = 0x00000000, .disable = 0xfffffffe},*/ + /*{.addr = 0x0015835c, .prod = 0x00000000, .disable = 0xfffffffe},*/ + /*{.addr = 0x0015a050, .prod = 0x00000000, .disable = 0xfffffffe},*/ + /*{.addr = 0x0015a55c, .prod = 0x00000000, .disable = 0xfffffffe},*/ + /*{.addr = 0x0015a75c, .prod = 0x00000000, .disable = 0xfffffffe},*/ + /*{.addr = 0x0015a95c, .prod = 0x00000000, .disable = 0xfffffffe},*/ + /*{.addr = 0x0015ab5c, .prod = 0x00000000, .disable = 0xfffffffe},*/ + /*{.addr = 0x0015a35c, .prod = 0x00000000, .disable = 0xfffffffe},*/ + /*{.addr = 0x0015c050, .prod = 0x00000000, .disable = 0xfffffffe},*/ + /*{.addr = 0x0015c55c, .prod = 0x00000000, .disable = 0xfffffffe},*/ + /*{.addr = 0x0015c75c, .prod = 0x00000000, .disable = 0xfffffffe},*/ + /*{.addr = 0x0015c95c, .prod = 0x00000000, .disable = 0xfffffffe},*/ + /*{.addr = 0x0015cb5c, .prod = 0x00000000, .disable = 0xfffffffe},*/ + /*{.addr = 0x0015c35c, .prod = 0x00000000, .disable = 0xfffffffe},*/ + /*{.addr = 0x0015e050, .prod = 0x00000000, .disable = 0xfffffffe},*/ + /*{.addr = 0x0015e55c, .prod = 0x00000000, .disable = 0xfffffffe},*/ + /*{.addr = 0x0015e75c, .prod = 0x00000000, .disable = 0xfffffffe},*/ + /*{.addr = 0x0015e95c, .prod = 0x00000000, .disable = 0xfffffffe},*/ + /*{.addr = 0x0015eb5c, .prod = 0x00000000, .disable = 0xfffffffe},*/ + /*{.addr = 0x0015e35c, .prod = 0x00000000, .disable = 0xfffffffe},*/ + {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, +}; + +/* slcg perf */ +static const struct gating_desc gv100_slcg_perf[] = { + {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00246218, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00246418, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00246618, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00246818, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00246a18, .prod = 0xffffffff, .disable = 0x00000000}, + /* fix priv error */ + /*{.addr = 0x00246c18, .prod = 0xffffffff, .disable = 0x00000000},*/ + /*{.addr = 0x00246e18, .prod = 0xffffffff, .disable = 0x00000000},*/ + {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00246218, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00246418, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00246618, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00246818, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00246a18, .prod = 0xffffffff, .disable = 0x00000000}, + /* fix priv error */ + /*{.addr = 0x00246c18, .prod = 0xffffffff, .disable = 0x00000000},*/ + /*{.addr = 0x00246e18, .prod = 0xffffffff, .disable = 0x00000000},*/ + {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00244218, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00244418, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00244618, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00244818, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00244a18, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00244218, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00244418, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00244618, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00244818, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00244a18, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x0024a124, .prod = 0x00000001, .disable = 0x00000000}, +}; + +/* slcg PriRing */ +static const struct gating_desc gv100_slcg_priring[] = { + {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, +}; + +/* slcg pwr_csb */ +static const struct gating_desc gv100_slcg_pwr_csb[] = { + {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, + {.addr = 0x00000a74, .prod = 0x00000000, .disable = 0x00007ffe}, + {.addr = 0x000016b8, .prod = 0x00000008, .disable = 0x0000000f}, +}; + +/* slcg pmu */ +static const struct gating_desc gv100_slcg_pmu[] = { + {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe}, + {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, +}; + +/* therm gr */ +static const struct gating_desc gv100_slcg_therm[] = { + {.addr = 0x000206b8, .prod = 0x00000008, .disable = 0x0000000f}, +}; + +/* slcg Xbar */ +static const struct gating_desc gv100_slcg_xbar[] = { + {.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe}, + {.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe}, + {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, + {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, + {.addr = 0x0013cc24, .prod = 0x00000000, .disable = 0x1ffffffe}, + {.addr = 0x0013cc44, .prod = 0x00000000, .disable = 0x1ffffffe}, + {.addr = 0x0013cc64, .prod = 0x00000000, .disable = 0x1ffffffe}, + {.addr = 0x0013cc84, .prod = 0x00000000, .disable = 0x1ffffffe}, + {.addr = 0x0013cca4, .prod = 0x00000000, .disable = 0x1ffffffe}, +}; + +/* blcg bus */ +static const struct gating_desc gv100_blcg_bus[] = { + {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, +}; + +/* blcg ce */ +static const struct gating_desc gv100_blcg_ce[] = { + {.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000}, +}; + +/* blcg ctxsw prog */ +static const struct gating_desc gv100_blcg_ctxsw_prog[] = { +}; + +/* blcg fb */ +static const struct gating_desc gv100_blcg_fb[] = { + {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, + {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, + /* fix priv error */ + /*{.addr = 0x00100d1c, .prod = 0x00000042, .disable = 0x00000000},*/ + {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, + {.addr = 0x001facb0, .prod = 0x00004242, .disable = 0x00000000}, +}; + +/* blcg fifo */ +static const struct gating_desc gv100_blcg_fifo[] = { + {.addr = 0x000026e0, .prod = 0x0000c242, .disable = 0x00000000}, +}; + +/* blcg gr */ +static const struct gating_desc gv100_blcg_gr[] = { + {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, + {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, + {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, + {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, + {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, + {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, + {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, + {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, + {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, + {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00418e0c, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, + {.addr = 0x00419868, .prod = 0x00008243, .disable = 0x00000000}, + {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00419c80, .prod = 0x00004048, .disable = 0x00000000}, + {.addr = 0x00419c88, .prod = 0x00004048, .disable = 0x00000000}, + {.addr = 0x00419c90, .prod = 0x0000004a, .disable = 0x00000000}, + {.addr = 0x00419c98, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x00419ca0, .prod = 0x00000043, .disable = 0x00000000}, + {.addr = 0x00419ca8, .prod = 0x00000003, .disable = 0x00000000}, + {.addr = 0x00419cb0, .prod = 0x00000002, .disable = 0x00000000}, + {.addr = 0x00419a40, .prod = 0x00000545, .disable = 0x00000000}, + {.addr = 0x00419a48, .prod = 0x00004545, .disable = 0x00000000}, + {.addr = 0x00419a50, .prod = 0x00004545, .disable = 0x00000000}, + {.addr = 0x00419a58, .prod = 0x00004545, .disable = 0x00000000}, + {.addr = 0x00419a60, .prod = 0x00000505, .disable = 0x00000000}, + {.addr = 0x00419a68, .prod = 0x00000505, .disable = 0x00000000}, + {.addr = 0x00419a78, .prod = 0x00000505, .disable = 0x00000000}, + {.addr = 0x00419a80, .prod = 0x00004545, .disable = 0x00000000}, + {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, + {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00412810, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00412a80, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x004129a8, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00412c10, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00412e80, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00412da8, .prod = 0x0000c242, .disable = 0x00000000}, + /* fix priv error */ + /*{.addr = 0x00413010, .prod = 0x0000c242, .disable = 0x00000000},*/ + /*{.addr = 0x00413280, .prod = 0x0000c242, .disable = 0x00000000},*/ + /*{.addr = 0x004131a8, .prod = 0x0000c242, .disable = 0x00000000},*/ + /*{.addr = 0x00413410, .prod = 0x0000c242, .disable = 0x00000000},*/ + /*{.addr = 0x00413680, .prod = 0x0000c242, .disable = 0x00000000},*/ + /*{.addr = 0x004135a8, .prod = 0x0000c242, .disable = 0x00000000},*/ + /*{.addr = 0x00413810, .prod = 0x0000c242, .disable = 0x00000000},*/ + /*{.addr = 0x00413a80, .prod = 0x0000c242, .disable = 0x00000000},*/ + /*{.addr = 0x004139a8, .prod = 0x0000c242, .disable = 0x00000000},*/ + /*{.addr = 0x00413c10, .prod = 0x0000c242, .disable = 0x00000000},*/ + /*{.addr = 0x00413e80, .prod = 0x0000c242, .disable = 0x00000000},*/ + /*{.addr = 0x00413da8, .prod = 0x0000c242, .disable = 0x00000000},*/ + {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, +}; + +/* blcg ltc */ +static const struct gating_desc gv100_blcg_ltc[] = { + {.addr = 0x00154030, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x00154040, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x001545e0, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x001545c8, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x001547e0, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x001547c8, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x001549e0, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x001549c8, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x00154be0, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x00154bc8, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x001543e0, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x001543c8, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x00156030, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x00156040, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x001565e0, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x001565c8, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x001567e0, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x001567c8, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x001569e0, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x001569c8, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x00156be0, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x00156bc8, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x001563e0, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x001563c8, .prod = 0x00000044, .disable = 0x00000000}, + /* fix priv error */ + /*{.addr = 0x00158030, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x00158040, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x001585e0, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x001585c8, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x001587e0, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x001587c8, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x001589e0, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x001589c8, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x00158be0, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x00158bc8, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x001583e0, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x001583c8, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015a030, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015a040, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015a5e0, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015a5c8, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015a7e0, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015a7c8, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015a9e0, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015a9c8, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015abe0, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015abc8, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015a3e0, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015a3c8, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015c030, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015c040, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015c5e0, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015c5c8, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015c7e0, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015c7c8, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015c9e0, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015c9c8, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015cbe0, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015cbc8, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015c3e0, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015c3c8, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015e030, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015e040, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015e5e0, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015e5c8, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015e7e0, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015e7c8, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015e9e0, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015e9c8, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015ebe0, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015ebc8, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015e3e0, .prod = 0x00000044, .disable = 0x00000000},*/ + /*{.addr = 0x0015e3c8, .prod = 0x00000044, .disable = 0x00000000},*/ + {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, +}; + +/* blcg pwr_csb */ +static const struct gating_desc gv100_blcg_pwr_csb[] = { + {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, +}; + +/* blcg pmu */ +static const struct gating_desc gv100_blcg_pmu[] = { + {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, +}; + +/* blcg Xbar */ +static const struct gating_desc gv100_blcg_xbar[] = { + {.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000}, + {.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000}, + {.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000}, + {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x0013cc20, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x0013cc40, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x0013cc60, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x0013cc80, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x0013cca0, .prod = 0x00000042, .disable = 0x00000000}, +}; + +/* pg gr */ +static const struct gating_desc gv100_pg_gr[] = { +}; + +/* inline functions */ +void gv100_slcg_bus_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv100_slcg_bus) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv100_slcg_bus[i].addr, + gv100_slcg_bus[i].prod); + else + gk20a_writel(g, gv100_slcg_bus[i].addr, + gv100_slcg_bus[i].disable); + } +} + +void gv100_slcg_ce2_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv100_slcg_ce2) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv100_slcg_ce2[i].addr, + gv100_slcg_ce2[i].prod); + else + gk20a_writel(g, gv100_slcg_ce2[i].addr, + gv100_slcg_ce2[i].disable); + } +} + +void gv100_slcg_chiplet_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv100_slcg_chiplet) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv100_slcg_chiplet[i].addr, + gv100_slcg_chiplet[i].prod); + else + gk20a_writel(g, gv100_slcg_chiplet[i].addr, + gv100_slcg_chiplet[i].disable); + } +} + +void gv100_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod) +{ +} + +void gv100_slcg_fb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv100_slcg_fb) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv100_slcg_fb[i].addr, + gv100_slcg_fb[i].prod); + else + gk20a_writel(g, gv100_slcg_fb[i].addr, + gv100_slcg_fb[i].disable); + } +} + +void gv100_slcg_fifo_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv100_slcg_fifo) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv100_slcg_fifo[i].addr, + gv100_slcg_fifo[i].prod); + else + gk20a_writel(g, gv100_slcg_fifo[i].addr, + gv100_slcg_fifo[i].disable); + } +} + +void gr_gv100_slcg_gr_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv100_slcg_gr) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv100_slcg_gr[i].addr, + gv100_slcg_gr[i].prod); + else + gk20a_writel(g, gv100_slcg_gr[i].addr, + gv100_slcg_gr[i].disable); + } +} + +void ltc_gv100_slcg_ltc_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv100_slcg_ltc) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv100_slcg_ltc[i].addr, + gv100_slcg_ltc[i].prod); + else + gk20a_writel(g, gv100_slcg_ltc[i].addr, + gv100_slcg_ltc[i].disable); + } +} + +void gv100_slcg_perf_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv100_slcg_perf) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv100_slcg_perf[i].addr, + gv100_slcg_perf[i].prod); + else + gk20a_writel(g, gv100_slcg_perf[i].addr, + gv100_slcg_perf[i].disable); + } +} + +void gv100_slcg_priring_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv100_slcg_priring) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv100_slcg_priring[i].addr, + gv100_slcg_priring[i].prod); + else + gk20a_writel(g, gv100_slcg_priring[i].addr, + gv100_slcg_priring[i].disable); + } +} + +void gv100_slcg_pwr_csb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv100_slcg_pwr_csb) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv100_slcg_pwr_csb[i].addr, + gv100_slcg_pwr_csb[i].prod); + else + gk20a_writel(g, gv100_slcg_pwr_csb[i].addr, + gv100_slcg_pwr_csb[i].disable); + } +} + +void gv100_slcg_pmu_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv100_slcg_pmu) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv100_slcg_pmu[i].addr, + gv100_slcg_pmu[i].prod); + else + gk20a_writel(g, gv100_slcg_pmu[i].addr, + gv100_slcg_pmu[i].disable); + } +} + +void gv100_slcg_therm_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv100_slcg_therm) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv100_slcg_therm[i].addr, + gv100_slcg_therm[i].prod); + else + gk20a_writel(g, gv100_slcg_therm[i].addr, + gv100_slcg_therm[i].disable); + } +} + +void gv100_slcg_xbar_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv100_slcg_xbar) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv100_slcg_xbar[i].addr, + gv100_slcg_xbar[i].prod); + else + gk20a_writel(g, gv100_slcg_xbar[i].addr, + gv100_slcg_xbar[i].disable); + } +} + +void gv100_blcg_bus_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv100_blcg_bus) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv100_blcg_bus[i].addr, + gv100_blcg_bus[i].prod); + else + gk20a_writel(g, gv100_blcg_bus[i].addr, + gv100_blcg_bus[i].disable); + } +} + +void gv100_blcg_ce_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv100_blcg_ce) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv100_blcg_ce[i].addr, + gv100_blcg_ce[i].prod); + else + gk20a_writel(g, gv100_blcg_ce[i].addr, + gv100_blcg_ce[i].disable); + } +} + +void gv100_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv100_blcg_ctxsw_prog) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv100_blcg_ctxsw_prog[i].addr, + gv100_blcg_ctxsw_prog[i].prod); + else + gk20a_writel(g, gv100_blcg_ctxsw_prog[i].addr, + gv100_blcg_ctxsw_prog[i].disable); + } +} + +void gv100_blcg_fb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv100_blcg_fb) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv100_blcg_fb[i].addr, + gv100_blcg_fb[i].prod); + else + gk20a_writel(g, gv100_blcg_fb[i].addr, + gv100_blcg_fb[i].disable); + } +} + +void gv100_blcg_fifo_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv100_blcg_fifo) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv100_blcg_fifo[i].addr, + gv100_blcg_fifo[i].prod); + else + gk20a_writel(g, gv100_blcg_fifo[i].addr, + gv100_blcg_fifo[i].disable); + } +} + +void gv100_blcg_gr_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv100_blcg_gr) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv100_blcg_gr[i].addr, + gv100_blcg_gr[i].prod); + else + gk20a_writel(g, gv100_blcg_gr[i].addr, + gv100_blcg_gr[i].disable); + } +} + +void gv100_blcg_ltc_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv100_blcg_ltc) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv100_blcg_ltc[i].addr, + gv100_blcg_ltc[i].prod); + else + gk20a_writel(g, gv100_blcg_ltc[i].addr, + gv100_blcg_ltc[i].disable); + } +} + +void gv100_blcg_pwr_csb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv100_blcg_pwr_csb) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv100_blcg_pwr_csb[i].addr, + gv100_blcg_pwr_csb[i].prod); + else + gk20a_writel(g, gv100_blcg_pwr_csb[i].addr, + gv100_blcg_pwr_csb[i].disable); + } +} + +void gv100_blcg_pmu_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv100_blcg_pmu) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv100_blcg_pmu[i].addr, + gv100_blcg_pmu[i].prod); + else + gk20a_writel(g, gv100_blcg_pmu[i].addr, + gv100_blcg_pmu[i].disable); + } +} + +void gv100_blcg_xbar_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv100_blcg_xbar) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv100_blcg_xbar[i].addr, + gv100_blcg_xbar[i].prod); + else + gk20a_writel(g, gv100_blcg_xbar[i].addr, + gv100_blcg_xbar[i].disable); + } +} + +void gr_gv100_pg_gr_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv100_pg_gr) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv100_pg_gr[i].addr, + gv100_pg_gr[i].prod); + else + gk20a_writel(g, gv100_pg_gr[i].addr, + gv100_pg_gr[i].disable); + } +} + +#endif /* __gv100_gating_reglist_h__ */ diff --git a/drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.h b/drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.h new file mode 100644 index 00000000..fa231d26 --- /dev/null +++ b/drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2018, NVIDIA Corporation. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gk20a/gk20a.h" + +void gv100_slcg_bus_load_gating_prod(struct gk20a *g, + bool prod); + +void gv100_slcg_ce2_load_gating_prod(struct gk20a *g, + bool prod); + +void gv100_slcg_chiplet_load_gating_prod(struct gk20a *g, + bool prod); + +void gv100_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod); + +void gv100_slcg_fb_load_gating_prod(struct gk20a *g, + bool prod); + +void gv100_slcg_fifo_load_gating_prod(struct gk20a *g, + bool prod); + +void gr_gv100_slcg_gr_load_gating_prod(struct gk20a *g, + bool prod); + +void ltc_gv100_slcg_ltc_load_gating_prod(struct gk20a *g, + bool prod); + +void gv100_slcg_perf_load_gating_prod(struct gk20a *g, + bool prod); + +void gv100_slcg_priring_load_gating_prod(struct gk20a *g, + bool prod); + +void gv100_slcg_pwr_csb_load_gating_prod(struct gk20a *g, + bool prod); + +void gv100_slcg_pmu_load_gating_prod(struct gk20a *g, + bool prod); + +void gv100_slcg_therm_load_gating_prod(struct gk20a *g, + bool prod); + +void gv100_slcg_xbar_load_gating_prod(struct gk20a *g, + bool prod); + +void gv100_blcg_bus_load_gating_prod(struct gk20a *g, + bool prod); + +void gv100_blcg_ce_load_gating_prod(struct gk20a *g, + bool prod); + +void gv100_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod); + +void gv100_blcg_fb_load_gating_prod(struct gk20a *g, + bool prod); + +void gv100_blcg_fifo_load_gating_prod(struct gk20a *g, + bool prod); + +void gv100_blcg_gr_load_gating_prod(struct gk20a *g, + bool prod); + +void gv100_blcg_ltc_load_gating_prod(struct gk20a *g, + bool prod); + +void gv100_blcg_pwr_csb_load_gating_prod(struct gk20a *g, + bool prod); + +void gv100_blcg_pmu_load_gating_prod(struct gk20a *g, + bool prod); + +void gv100_blcg_xbar_load_gating_prod(struct gk20a *g, + bool prod); + +void gr_gv100_pg_gr_load_gating_prod(struct gk20a *g, + bool prod); + diff --git a/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.c b/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.c new file mode 100644 index 00000000..4dbc87d5 --- /dev/null +++ b/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.c @@ -0,0 +1,750 @@ +/* + * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This file is autogenerated. Do not edit. + */ + +#ifndef __gv11b_gating_reglist_h__ +#define __gv11b_gating_reglist_h__ + +#include +#include "gv11b_gating_reglist.h" +#include + +struct gating_desc { + u32 addr; + u32 prod; + u32 disable; +}; +/* slcg bus */ +static const struct gating_desc gv11b_slcg_bus[] = { + {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, +}; + +/* slcg ce2 */ +static const struct gating_desc gv11b_slcg_ce2[] = { + {.addr = 0x00104204, .prod = 0x00000040, .disable = 0x000007fe}, +}; + +/* slcg chiplet */ +static const struct gating_desc gv11b_slcg_chiplet[] = { + {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, +}; + +/* slcg fb */ +static const struct gating_desc gv11b_slcg_fb[] = { + {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, +}; + +/* slcg fifo */ +static const struct gating_desc gv11b_slcg_fifo[] = { + {.addr = 0x000026ec, .prod = 0x00000000, .disable = 0x0001fffe}, +}; + +/* slcg gr */ +static const struct gating_desc gv11b_slcg_gr[] = { + {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe}, + {.addr = 0x00409134, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x00409894, .prod = 0x00000000, .disable = 0x0000fffe}, + {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00406004, .prod = 0x00000200, .disable = 0x0001fffe}, + {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, + {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, + /* fix priv error */ + /*{.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe},*/ + /*{.addr = 0x00405bf4, .prod = 0x00000000, .disable = 0x00000002},*/ + {.addr = 0x0041a134, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x0041a894, .prod = 0x00000000, .disable = 0x0000fffe}, + {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, + /* fix priv error */ + /*{.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe},*/ + {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, + {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe}, + {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, + {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, + /* fix priv error */ + /*{.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe},*/ + {.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe}, + {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, + {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, + {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, + {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, + {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x000000ff}, + {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, + {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, + {.addr = 0x00419c8c, .prod = 0xffffff84, .disable = 0xfffffffe}, + {.addr = 0x00419c94, .prod = 0x00080040, .disable = 0x000ffffe}, + {.addr = 0x00419ca4, .prod = 0x00003ffe, .disable = 0x00003ffe}, + {.addr = 0x00419cac, .prod = 0x0001fffe, .disable = 0x0001fffe}, + {.addr = 0x00419a44, .prod = 0x00000008, .disable = 0x0000000e}, + {.addr = 0x00419a4c, .prod = 0x000001f8, .disable = 0x000001fe}, + {.addr = 0x00419a54, .prod = 0x0000003c, .disable = 0x0000003e}, + {.addr = 0x00419a5c, .prod = 0x0000000c, .disable = 0x0000000e}, + {.addr = 0x00419a64, .prod = 0x000001ba, .disable = 0x000001fe}, + {.addr = 0x00419a7c, .prod = 0x0000003c, .disable = 0x0000003e}, + {.addr = 0x00419a84, .prod = 0x0000000c, .disable = 0x0000000e}, + {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, + {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, + /* fix priv error */ + /*{.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe},*/ + {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x000000ff}, +}; + +/* slcg ltc */ +static const struct gating_desc gv11b_slcg_ltc[] = { + {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, +}; + +/* slcg perf */ +static const struct gating_desc gv11b_slcg_perf[] = { + {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x0024a124, .prod = 0x00000001, .disable = 0x00000000}, +}; + +/* slcg PriRing */ +static const struct gating_desc gv11b_slcg_priring[] = { + {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, +}; + +/* slcg pwr_csb */ +static const struct gating_desc gv11b_slcg_pwr_csb[] = { + {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, + {.addr = 0x00000a74, .prod = 0x00004040, .disable = 0x00007ffe}, + {.addr = 0x000206b8, .prod = 0x00000008, .disable = 0x0000000f}, +}; + +/* slcg pmu */ +static const struct gating_desc gv11b_slcg_pmu[] = { + {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x0010aa74, .prod = 0x00004040, .disable = 0x00007ffe}, + {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, +}; + +/* therm gr */ +static const struct gating_desc gv11b_slcg_therm[] = { + {.addr = 0x000206b8, .prod = 0x00000008, .disable = 0x0000000f}, +}; + +/* slcg Xbar */ +static const struct gating_desc gv11b_slcg_xbar[] = { + {.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe}, + {.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe}, + {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, + {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, +}; + +/* blcg bus */ +static const struct gating_desc gv11b_blcg_bus[] = { + {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, +}; + +/* blcg ce */ +static const struct gating_desc gv11b_blcg_ce[] = { + {.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000}, +}; + +/* blcg ctxsw prog */ +static const struct gating_desc gv11b_blcg_ctxsw_prog[] = { +}; + +/* blcg fb */ +static const struct gating_desc gv11b_blcg_fb[] = { + {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, + {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, +}; + +/* blcg fifo */ +static const struct gating_desc gv11b_blcg_fifo[] = { + {.addr = 0x000026e0, .prod = 0x0000c244, .disable = 0x00000000}, +}; + +/* blcg gr */ +static const struct gating_desc gv11b_blcg_gr[] = { + {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, + {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, + {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, + {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, + {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, + {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, + {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, + {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, + {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, + {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00418e0c, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, + {.addr = 0x00419868, .prod = 0x00008243, .disable = 0x00000000}, + {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00419c80, .prod = 0x00004045, .disable = 0x00000000}, + {.addr = 0x00419c88, .prod = 0x00004043, .disable = 0x00000000}, + {.addr = 0x00419c90, .prod = 0x0000004a, .disable = 0x00000000}, + {.addr = 0x00419c98, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x00419ca0, .prod = 0x00000043, .disable = 0x00000000}, + {.addr = 0x00419ca8, .prod = 0x00000003, .disable = 0x00000000}, + {.addr = 0x00419cb0, .prod = 0x00000002, .disable = 0x00000000}, + {.addr = 0x00419a40, .prod = 0x00000242, .disable = 0x00000000}, + {.addr = 0x00419a48, .prod = 0x00000242, .disable = 0x00000000}, + {.addr = 0x00419a50, .prod = 0x00000242, .disable = 0x00000000}, + {.addr = 0x00419a58, .prod = 0x00000242, .disable = 0x00000000}, + {.addr = 0x00419a60, .prod = 0x00000202, .disable = 0x00000000}, + {.addr = 0x00419a68, .prod = 0x00000202, .disable = 0x00000000}, + {.addr = 0x00419a78, .prod = 0x00000242, .disable = 0x00000000}, + {.addr = 0x00419a80, .prod = 0x00000242, .disable = 0x00000000}, + {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, + {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, +}; + +/* blcg ltc */ +static const struct gating_desc gv11b_blcg_ltc[] = { + {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, +}; + +/* blcg pwr_csb */ +static const struct gating_desc gv11b_blcg_pwr_csb[] = { + {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, +}; + +/* blcg pmu */ +static const struct gating_desc gv11b_blcg_pmu[] = { + {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, +}; + +/* blcg Xbar */ +static const struct gating_desc gv11b_blcg_xbar[] = { + {.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000}, + {.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000}, + {.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000}, + {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, +}; + +/* pg gr */ +static const struct gating_desc gv11b_pg_gr[] = { +}; + +/* inline functions */ +void gv11b_slcg_bus_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_bus) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_bus[i].addr, + gv11b_slcg_bus[i].prod); + else + gk20a_writel(g, gv11b_slcg_bus[i].addr, + gv11b_slcg_bus[i].disable); + } +} + +void gv11b_slcg_ce2_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_ce2) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_ce2[i].addr, + gv11b_slcg_ce2[i].prod); + else + gk20a_writel(g, gv11b_slcg_ce2[i].addr, + gv11b_slcg_ce2[i].disable); + } +} + +void gv11b_slcg_chiplet_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_chiplet) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_chiplet[i].addr, + gv11b_slcg_chiplet[i].prod); + else + gk20a_writel(g, gv11b_slcg_chiplet[i].addr, + gv11b_slcg_chiplet[i].disable); + } +} + +void gv11b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod) +{ +} + +void gv11b_slcg_fb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_fb) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_fb[i].addr, + gv11b_slcg_fb[i].prod); + else + gk20a_writel(g, gv11b_slcg_fb[i].addr, + gv11b_slcg_fb[i].disable); + } +} + +void gv11b_slcg_fifo_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_fifo) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_fifo[i].addr, + gv11b_slcg_fifo[i].prod); + else + gk20a_writel(g, gv11b_slcg_fifo[i].addr, + gv11b_slcg_fifo[i].disable); + } +} + +void gr_gv11b_slcg_gr_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_gr) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_gr[i].addr, + gv11b_slcg_gr[i].prod); + else + gk20a_writel(g, gv11b_slcg_gr[i].addr, + gv11b_slcg_gr[i].disable); + } +} + +void ltc_gv11b_slcg_ltc_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_ltc) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_ltc[i].addr, + gv11b_slcg_ltc[i].prod); + else + gk20a_writel(g, gv11b_slcg_ltc[i].addr, + gv11b_slcg_ltc[i].disable); + } +} + +void gv11b_slcg_perf_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_perf) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_perf[i].addr, + gv11b_slcg_perf[i].prod); + else + gk20a_writel(g, gv11b_slcg_perf[i].addr, + gv11b_slcg_perf[i].disable); + } +} + +void gv11b_slcg_priring_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_priring) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_priring[i].addr, + gv11b_slcg_priring[i].prod); + else + gk20a_writel(g, gv11b_slcg_priring[i].addr, + gv11b_slcg_priring[i].disable); + } +} + +void gv11b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_pwr_csb) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_pwr_csb[i].addr, + gv11b_slcg_pwr_csb[i].prod); + else + gk20a_writel(g, gv11b_slcg_pwr_csb[i].addr, + gv11b_slcg_pwr_csb[i].disable); + } +} + +void gv11b_slcg_pmu_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_pmu) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_pmu[i].addr, + gv11b_slcg_pmu[i].prod); + else + gk20a_writel(g, gv11b_slcg_pmu[i].addr, + gv11b_slcg_pmu[i].disable); + } +} + +void gv11b_slcg_therm_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_therm) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_therm[i].addr, + gv11b_slcg_therm[i].prod); + else + gk20a_writel(g, gv11b_slcg_therm[i].addr, + gv11b_slcg_therm[i].disable); + } +} + +void gv11b_slcg_xbar_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_xbar) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_xbar[i].addr, + gv11b_slcg_xbar[i].prod); + else + gk20a_writel(g, gv11b_slcg_xbar[i].addr, + gv11b_slcg_xbar[i].disable); + } +} + +void gv11b_blcg_bus_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_blcg_bus) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_blcg_bus[i].addr, + gv11b_blcg_bus[i].prod); + else + gk20a_writel(g, gv11b_blcg_bus[i].addr, + gv11b_blcg_bus[i].disable); + } +} + +void gv11b_blcg_ce_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_blcg_ce) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_blcg_ce[i].addr, + gv11b_blcg_ce[i].prod); + else + gk20a_writel(g, gv11b_blcg_ce[i].addr, + gv11b_blcg_ce[i].disable); + } +} + +void gv11b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_blcg_ctxsw_prog) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_blcg_ctxsw_prog[i].addr, + gv11b_blcg_ctxsw_prog[i].prod); + else + gk20a_writel(g, gv11b_blcg_ctxsw_prog[i].addr, + gv11b_blcg_ctxsw_prog[i].disable); + } +} + +void gv11b_blcg_fb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_blcg_fb) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_blcg_fb[i].addr, + gv11b_blcg_fb[i].prod); + else + gk20a_writel(g, gv11b_blcg_fb[i].addr, + gv11b_blcg_fb[i].disable); + } +} + +void gv11b_blcg_fifo_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_blcg_fifo) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_blcg_fifo[i].addr, + gv11b_blcg_fifo[i].prod); + else + gk20a_writel(g, gv11b_blcg_fifo[i].addr, + gv11b_blcg_fifo[i].disable); + } +} + +void gv11b_blcg_gr_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_blcg_gr) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_blcg_gr[i].addr, + gv11b_blcg_gr[i].prod); + else + gk20a_writel(g, gv11b_blcg_gr[i].addr, + gv11b_blcg_gr[i].disable); + } +} + +void gv11b_blcg_ltc_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_blcg_ltc) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_blcg_ltc[i].addr, + gv11b_blcg_ltc[i].prod); + else + gk20a_writel(g, gv11b_blcg_ltc[i].addr, + gv11b_blcg_ltc[i].disable); + } +} + +void gv11b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_blcg_pwr_csb) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_blcg_pwr_csb[i].addr, + gv11b_blcg_pwr_csb[i].prod); + else + gk20a_writel(g, gv11b_blcg_pwr_csb[i].addr, + gv11b_blcg_pwr_csb[i].disable); + } +} + +void gv11b_blcg_pmu_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_blcg_pmu) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_blcg_pmu[i].addr, + gv11b_blcg_pmu[i].prod); + else + gk20a_writel(g, gv11b_blcg_pmu[i].addr, + gv11b_blcg_pmu[i].disable); + } +} + +void gv11b_blcg_xbar_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_blcg_xbar) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_blcg_xbar[i].addr, + gv11b_blcg_xbar[i].prod); + else + gk20a_writel(g, gv11b_blcg_xbar[i].addr, + gv11b_blcg_xbar[i].disable); + } +} + +void gr_gv11b_pg_gr_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_pg_gr) / sizeof(struct gating_desc); + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) + return; + + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_pg_gr[i].addr, + gv11b_pg_gr[i].prod); + else + gk20a_writel(g, gv11b_pg_gr[i].addr, + gv11b_pg_gr[i].disable); + } +} + +#endif /* __gv11b_gating_reglist_h__ */ diff --git a/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.h b/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.h new file mode 100644 index 00000000..233189e0 --- /dev/null +++ b/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2016, NVIDIA Corporation. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gk20a/gk20a.h" + +void gv11b_slcg_bus_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_slcg_ce2_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_slcg_chiplet_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_slcg_fb_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_slcg_fifo_load_gating_prod(struct gk20a *g, + bool prod); + +void gr_gv11b_slcg_gr_load_gating_prod(struct gk20a *g, + bool prod); + +void ltc_gv11b_slcg_ltc_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_slcg_perf_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_slcg_priring_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_slcg_pmu_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_slcg_therm_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_slcg_xbar_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_blcg_bus_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_blcg_ce_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_blcg_fb_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_blcg_fifo_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_blcg_gr_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_blcg_ltc_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_blcg_pmu_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_blcg_xbar_load_gating_prod(struct gk20a *g, + bool prod); + +void gr_gv11b_pg_gr_load_gating_prod(struct gk20a *g, + bool prod); + diff --git a/drivers/gpu/nvgpu/gk20a/gk20a_gating_reglist.c b/drivers/gpu/nvgpu/gk20a/gk20a_gating_reglist.c deleted file mode 100644 index 751c6a19..00000000 --- a/drivers/gpu/nvgpu/gk20a/gk20a_gating_reglist.c +++ /dev/null @@ -1,404 +0,0 @@ -/* - * Copyright (c) 2012-2017, NVIDIA Corporation. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * This file is autogenerated. Do not edit. - */ - -#ifndef __gk20a_gating_reglist_h__ -#define __gk20a_gating_reglist_h__ - -#include "gk20a_gating_reglist.h" -#include - -struct gating_desc { - u32 addr; - u32 prod; - u32 disable; -}; -/* slcg gr */ -static const struct gating_desc gk20a_slcg_gr[] = { - {.addr = 0x004041f4, .prod = 0x00000002, .disable = 0x03fffffe}, - {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x0003fffe}, - {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00405910, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, - {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x0000001e}, - {.addr = 0x0041a894, .prod = 0x00000000, .disable = 0x0003fffe}, - {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, - {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x0000003e}, - {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, - {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00418c74, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x00418cf4, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x00418d74, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x00418f10, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x00418e10, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x00419024, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e}, - {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e}, - {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x00419ad0, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x0041986c, .prod = 0x0000dfc0, .disable = 0x00fffffe}, - {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe}, - {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe}, - {.addr = 0x00419c74, .prod = 0x00000000, .disable = 0x0000001e}, - {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe}, - {.addr = 0x00419fdc, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x00419fe4, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe}, - {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x0041be2c, .prod = 0x020bbfc0, .disable = 0xfffffffe}, - {.addr = 0x0041bfec, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x0041bed4, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x0040881c, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00408a8c, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00408a94, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00408a9c, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00408aa4, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00408aac, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x000001ff}, - {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0x00fffffe}, - {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, - {.addr = 0x0010e48c, .prod = 0x00000000, .disable = 0x0000003e}, - {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000000fe}, - {.addr = 0x00106f28, .prod = 0x00000040, .disable = 0x000007fe}, - {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, - {.addr = 0x0017ea98, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x00106f28, .prod = 0x00000040, .disable = 0x000007fe}, - {.addr = 0x00120048, .prod = 0x00000000, .disable = 0x00000049}, -}; - -/* slcg perf */ -static const struct gating_desc gk20a_slcg_perf[] = { - {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000}, - {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000}, - {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000}, - {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000}, -}; - -/* blcg gr */ -static const struct gating_desc gk20a_blcg_gr[] = { - {.addr = 0x004041f0, .prod = 0x00004046, .disable = 0x00000000}, - {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, - {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, - {.addr = 0x004078c0, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x00406000, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x00405860, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x0040590c, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x00408040, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x00407000, .prod = 0x00004041, .disable = 0x00000000}, - {.addr = 0x00405bf0, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x0041a890, .prod = 0x0000007f, .disable = 0x00000000}, - {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, - {.addr = 0x00418500, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x00418608, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00418688, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x00418828, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x00418bbc, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00418970, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00418c70, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x00418cf0, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x00418d70, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x00418f0c, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x00418e0c, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x00419020, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x00419a40, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00419a48, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00419a50, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00419a58, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00419a60, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00419a68, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00419a70, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00419a78, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00419a80, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00419acc, .prod = 0x00004047, .disable = 0x00000000}, - {.addr = 0x00419868, .prod = 0x00000043, .disable = 0x00000000}, - {.addr = 0x00419cd4, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00419cdc, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00419c70, .prod = 0x00004045, .disable = 0x00000000}, - {.addr = 0x00419fd0, .prod = 0x00004043, .disable = 0x00000000}, - {.addr = 0x00419fd8, .prod = 0x00004045, .disable = 0x00000000}, - {.addr = 0x00419fe0, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00419fe8, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00419ff0, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x00419ff8, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00419f90, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x0041be28, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x0041bfe8, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x0041bed0, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x00408810, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00408818, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00408a80, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00408a88, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00408a90, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00408a98, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00408aa0, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00408aa8, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x004089a8, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x004089b0, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x004089b8, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x0017ea60, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x0017ea68, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, - {.addr = 0x0017ea78, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x00100d1c, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x00106f24, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x0041be00, .prod = 0x00000004, .disable = 0x00000007}, - {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x0017ea70, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x00100c98, .prod = 0x00000242, .disable = 0x00000000}, - {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, -}; - -/* pg gr */ -static const struct gating_desc gk20a_pg_gr[] = { - {.addr = 0x004041f8, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x004041fc, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00409898, .prod = 0x10140000, .disable = 0x00000000}, - {.addr = 0x0040989c, .prod = 0xff00000a, .disable = 0x00000000}, - {.addr = 0x004078c8, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x004078cc, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00406008, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x0040600c, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00405868, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x0040586c, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00405914, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00405924, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00408048, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x0040804c, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00407008, .prod = 0x10140000, .disable = 0x00000000}, - {.addr = 0x0040700c, .prod = 0xff00000a, .disable = 0x00000000}, - {.addr = 0x00405bf8, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00405bfc, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x0041a898, .prod = 0x10140000, .disable = 0x00000000}, - {.addr = 0x0041a89c, .prod = 0xff00000a, .disable = 0x00000000}, - {.addr = 0x00418510, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00418514, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00418610, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00418614, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00418690, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00418694, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00418720, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00418724, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00418840, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00418844, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00418bc4, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00418bc8, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00418978, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x0041897c, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00418c78, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00418c7c, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00418cf8, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00418cfc, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00418d78, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00418d7c, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00418f14, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00418f18, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00418e14, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00418e18, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00419030, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00419050, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00419a88, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00419a8c, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00419a90, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00419a94, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00419a98, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00419a9c, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00419aa0, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00419aa4, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00419ad4, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00419ad8, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00419870, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00419874, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00419ce4, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00419cf0, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00419c78, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00419c7c, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00419fa0, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00419fa4, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00419fa8, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00419fac, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00419fb0, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00419fb4, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00419fb8, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00419fbc, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00419fc0, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00419fc4, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00419fc8, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00419fcc, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x0041be30, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x0041be34, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x0041bff0, .prod = 0x10747c00, .disable = 0x00000000}, - {.addr = 0x0041bff4, .prod = 0xff00000a, .disable = 0x00000000}, - {.addr = 0x0041bed8, .prod = 0x10240a00, .disable = 0x00000000}, - {.addr = 0x0041bee0, .prod = 0xff00000a, .disable = 0x00000000}, - {.addr = 0x00408820, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00408824, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00408828, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x0040882c, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00408ac0, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00408ac4, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00408ac8, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00408acc, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00408ad0, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00408ad4, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00408ad8, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00408adc, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00408ae0, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00408ae4, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x00408ae8, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x00408aec, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x004089c0, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x004089c4, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x004089c8, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x004089cc, .prod = 0xff00a725, .disable = 0x00000000}, - {.addr = 0x004089d0, .prod = 0x10940000, .disable = 0x00000000}, - {.addr = 0x004089d4, .prod = 0xff00a725, .disable = 0x00000000}, -}; - -/* therm gr */ -static const struct gating_desc gk20a_slcg_therm[] = { - {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, -}; - -/* static inline functions */ -void gr_gk20a_slcg_gr_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gk20a_slcg_gr) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gk20a_slcg_gr[i].addr, - gk20a_slcg_gr[i].prod); - else - gk20a_writel(g, gk20a_slcg_gr[i].addr, - gk20a_slcg_gr[i].disable); - } -} - -void ltc_gk20a_slcg_ltc_load_gating_prod(struct gk20a *g, - bool prod) -{ -} - -void gr_gk20a_slcg_perf_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gk20a_slcg_perf) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gk20a_slcg_perf[i].addr, - gk20a_slcg_perf[i].prod); - else - gk20a_writel(g, gk20a_slcg_perf[i].addr, - gk20a_slcg_perf[i].disable); - } -} - -void gr_gk20a_blcg_gr_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gk20a_blcg_gr) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gk20a_blcg_gr[i].addr, - gk20a_blcg_gr[i].prod); - else - gk20a_writel(g, gk20a_blcg_gr[i].addr, - gk20a_blcg_gr[i].disable); - } -} - -void gr_gk20a_pg_gr_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gk20a_pg_gr) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gk20a_pg_gr[i].addr, - gk20a_pg_gr[i].prod); - else - gk20a_writel(g, gk20a_pg_gr[i].addr, - gk20a_pg_gr[i].disable); - } -} - -void gr_gk20a_slcg_therm_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gk20a_slcg_therm) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gk20a_slcg_therm[i].addr, - gk20a_slcg_therm[i].prod); - else - gk20a_writel(g, gk20a_slcg_therm[i].addr, - gk20a_slcg_therm[i].disable); - } -} - -#endif /* __gk20a_gating_reglist_h__ */ diff --git a/drivers/gpu/nvgpu/gk20a/gk20a_gating_reglist.h b/drivers/gpu/nvgpu/gk20a/gk20a_gating_reglist.h deleted file mode 100644 index e27c1633..00000000 --- a/drivers/gpu/nvgpu/gk20a/gk20a_gating_reglist.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * drivers/video/tegra/host/gk20a/gk20a_gating_reglist.h - * - * Copyright (c) 2012-2014, NVIDIA Corporation. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * This file is autogenerated. Do not edit. - */ - -#include "gk20a.h" - -void gr_gk20a_slcg_gr_load_gating_prod(struct gk20a *g, - bool prod); - -void gr_gk20a_slcg_perf_load_gating_prod(struct gk20a *g, - bool prod); - -void ltc_gk20a_slcg_ltc_load_gating_prod(struct gk20a *g, - bool prod); - -void gr_gk20a_blcg_gr_load_gating_prod(struct gk20a *g, - bool prod); - -void gr_gk20a_pg_gr_load_gating_prod(struct gk20a *g, - bool prod); - -void gr_gk20a_slcg_therm_load_gating_prod(struct gk20a *g, - bool prod); - - diff --git a/drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.c b/drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.c deleted file mode 100644 index 0ebb2d0d..00000000 --- a/drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.c +++ /dev/null @@ -1,731 +0,0 @@ -/* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * This file is autogenerated. Do not edit. - */ - -#ifndef __gm20b_gating_reglist_h__ -#define __gm20b_gating_reglist_h__ - -#include "gm20b_gating_reglist.h" -#include - -struct gating_desc { - u32 addr; - u32 prod; - u32 disable; -}; -/* slcg bus */ -static const struct gating_desc gm20b_slcg_bus[] = { - {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, -}; - -/* slcg ce2 */ -static const struct gating_desc gm20b_slcg_ce2[] = { - {.addr = 0x00106f28, .prod = 0x00000000, .disable = 0x000007fe}, -}; - -/* slcg chiplet */ -static const struct gating_desc gm20b_slcg_chiplet[] = { - {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, -}; - -/* slcg fb */ -static const struct gating_desc gm20b_slcg_fb[] = { - {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, -}; - -/* slcg fifo */ -static const struct gating_desc gm20b_slcg_fifo[] = { - {.addr = 0x000026ac, .prod = 0x00000100, .disable = 0x0001fffe}, -}; - -/* slcg gr */ -static const struct gating_desc gm20b_slcg_gr[] = { - {.addr = 0x004041f4, .prod = 0x00000002, .disable = 0x03fffffe}, - {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, - {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x0003fffe}, - {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, - {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, - {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x0000007e}, - {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, - {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x0003fffe}, - {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, - {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, - {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x0000003e}, - {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, - {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00418c74, .prod = 0xffffffc0, .disable = 0xfffffffe}, - {.addr = 0x00418cf4, .prod = 0xfffffffc, .disable = 0xfffffffe}, - {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, - {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, - {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, - {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, - {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00419d64, .prod = 0x00000000, .disable = 0x000001ff}, - {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e}, - {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e}, - {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, - {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe}, - {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe}, - {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, - {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe}, - {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe}, - {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe}, - {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe}, - {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, - {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, - {.addr = 0x0041bed4, .prod = 0xfffffff6, .disable = 0xfffffffe}, - {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x0040881c, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00408a8c, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00408a94, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00408a9c, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00408aa4, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00408aac, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x000001ff}, -}; - -/* slcg ltc */ -static const struct gating_desc gm20b_slcg_ltc[] = { - {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, -}; - -/* slcg perf */ -static const struct gating_desc gm20b_slcg_perf[] = { - {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000}, - {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000}, - {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000}, - {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000}, -}; - -/* slcg PriRing */ -static const struct gating_desc gm20b_slcg_priring[] = { - {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, -}; - -/* slcg pwr_csb */ -static const struct gating_desc gm20b_slcg_pwr_csb[] = { - {.addr = 0x0000017c, .prod = 0x00020008, .disable = 0x0003fffe}, - {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, - {.addr = 0x00000a74, .prod = 0x00000000, .disable = 0x00007ffe}, - {.addr = 0x000016b8, .prod = 0x00000000, .disable = 0x0000000f}, -}; - -/* slcg pmu */ -static const struct gating_desc gm20b_slcg_pmu[] = { - {.addr = 0x0010a17c, .prod = 0x00020008, .disable = 0x0003fffe}, - {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe}, - {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, -}; - -/* therm gr */ -static const struct gating_desc gm20b_slcg_therm[] = { - {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, -}; - -/* slcg Xbar */ -static const struct gating_desc gm20b_slcg_xbar[] = { - {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, - {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, -}; - -/* blcg bus */ -static const struct gating_desc gm20b_blcg_bus[] = { - {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, -}; - -/* blcg ctxsw prog */ -static const struct gating_desc gm20b_blcg_ctxsw_prog[] = { -}; - -/* blcg fb */ -static const struct gating_desc gm20b_blcg_fb[] = { - {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, - {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00100c98, .prod = 0x00000242, .disable = 0x00000000}, -}; - -/* blcg fifo */ -static const struct gating_desc gm20b_blcg_fifo[] = { - {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000}, -}; - -/* blcg gr */ -static const struct gating_desc gm20b_blcg_gr[] = { - {.addr = 0x004041f0, .prod = 0x00004046, .disable = 0x00000000}, - {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, - {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, - {.addr = 0x004078c0, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x00406000, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x00405860, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x0040590c, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x00408040, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x00407000, .prod = 0x00004041, .disable = 0x00000000}, - {.addr = 0x00405bf0, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x0041a890, .prod = 0x0000007f, .disable = 0x00000000}, - {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, - {.addr = 0x00418500, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x00418608, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00418688, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x00418828, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x00418bbc, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00418970, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00418c70, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x00418cf0, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x00418d70, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x00418f0c, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x00418e0c, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x00419020, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x00418898, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x00419a40, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x00419a48, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00419a50, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00419a58, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00419a60, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00419a68, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00419a70, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00419a78, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00419a80, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00419868, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000}, - {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000}, - {.addr = 0x00419c70, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x00419fd0, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x00419fd8, .prod = 0x00004046, .disable = 0x00000000}, - {.addr = 0x00419fe0, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x00419fe8, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x00419ff0, .prod = 0x00004045, .disable = 0x00000000}, - {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000}, - {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000}, - {.addr = 0x0041be28, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x0041bfe8, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x0041bed0, .prod = 0x00004044, .disable = 0x00000000}, - {.addr = 0x00408810, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00408818, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00408a80, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00408a88, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00408a90, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00408a98, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00408aa0, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x00408aa8, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x004089a8, .prod = 0x00004042, .disable = 0x00000000}, - {.addr = 0x004089b0, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x004089b8, .prod = 0x00004042, .disable = 0x00000000}, -}; - -/* blcg ltc */ -static const struct gating_desc gm20b_blcg_ltc[] = { - {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, -}; - -/* blcg pwr_csb */ -static const struct gating_desc gm20b_blcg_pwr_csb[] = { - {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, -}; - -/* blcg pmu */ -static const struct gating_desc gm20b_blcg_pmu[] = { - {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, -}; - -/* blcg Xbar */ -static const struct gating_desc gm20b_blcg_xbar[] = { - {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, -}; - -/* pg gr */ -static const struct gating_desc gm20b_pg_gr[] = { -}; - -/* inline functions */ -void gm20b_slcg_bus_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gm20b_slcg_bus) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gm20b_slcg_bus[i].addr, - gm20b_slcg_bus[i].prod); - else - gk20a_writel(g, gm20b_slcg_bus[i].addr, - gm20b_slcg_bus[i].disable); - } -} - -void gm20b_slcg_ce2_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gm20b_slcg_ce2) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gm20b_slcg_ce2[i].addr, - gm20b_slcg_ce2[i].prod); - else - gk20a_writel(g, gm20b_slcg_ce2[i].addr, - gm20b_slcg_ce2[i].disable); - } -} - -void gm20b_slcg_chiplet_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gm20b_slcg_chiplet) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gm20b_slcg_chiplet[i].addr, - gm20b_slcg_chiplet[i].prod); - else - gk20a_writel(g, gm20b_slcg_chiplet[i].addr, - gm20b_slcg_chiplet[i].disable); - } -} - -void gm20b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, - bool prod) -{ -} - -void gm20b_slcg_fb_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gm20b_slcg_fb) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gm20b_slcg_fb[i].addr, - gm20b_slcg_fb[i].prod); - else - gk20a_writel(g, gm20b_slcg_fb[i].addr, - gm20b_slcg_fb[i].disable); - } -} - -void gm20b_slcg_fifo_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gm20b_slcg_fifo) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gm20b_slcg_fifo[i].addr, - gm20b_slcg_fifo[i].prod); - else - gk20a_writel(g, gm20b_slcg_fifo[i].addr, - gm20b_slcg_fifo[i].disable); - } -} - -void gr_gm20b_slcg_gr_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gm20b_slcg_gr) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gm20b_slcg_gr[i].addr, - gm20b_slcg_gr[i].prod); - else - gk20a_writel(g, gm20b_slcg_gr[i].addr, - gm20b_slcg_gr[i].disable); - } -} - -void ltc_gm20b_slcg_ltc_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gm20b_slcg_ltc) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gm20b_slcg_ltc[i].addr, - gm20b_slcg_ltc[i].prod); - else - gk20a_writel(g, gm20b_slcg_ltc[i].addr, - gm20b_slcg_ltc[i].disable); - } -} - -void gm20b_slcg_perf_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gm20b_slcg_perf) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gm20b_slcg_perf[i].addr, - gm20b_slcg_perf[i].prod); - else - gk20a_writel(g, gm20b_slcg_perf[i].addr, - gm20b_slcg_perf[i].disable); - } -} - -void gm20b_slcg_priring_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gm20b_slcg_priring) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gm20b_slcg_priring[i].addr, - gm20b_slcg_priring[i].prod); - else - gk20a_writel(g, gm20b_slcg_priring[i].addr, - gm20b_slcg_priring[i].disable); - } -} - -void gm20b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gm20b_slcg_pwr_csb) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gm20b_slcg_pwr_csb[i].addr, - gm20b_slcg_pwr_csb[i].prod); - else - gk20a_writel(g, gm20b_slcg_pwr_csb[i].addr, - gm20b_slcg_pwr_csb[i].disable); - } -} - -void gm20b_slcg_pmu_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gm20b_slcg_pmu) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gm20b_slcg_pmu[i].addr, - gm20b_slcg_pmu[i].prod); - else - gk20a_writel(g, gm20b_slcg_pmu[i].addr, - gm20b_slcg_pmu[i].disable); - } -} - -void gm20b_slcg_therm_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gm20b_slcg_therm) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gm20b_slcg_therm[i].addr, - gm20b_slcg_therm[i].prod); - else - gk20a_writel(g, gm20b_slcg_therm[i].addr, - gm20b_slcg_therm[i].disable); - } -} - -void gm20b_slcg_xbar_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gm20b_slcg_xbar) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gm20b_slcg_xbar[i].addr, - gm20b_slcg_xbar[i].prod); - else - gk20a_writel(g, gm20b_slcg_xbar[i].addr, - gm20b_slcg_xbar[i].disable); - } -} - -void gm20b_blcg_bus_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gm20b_blcg_bus) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gm20b_blcg_bus[i].addr, - gm20b_blcg_bus[i].prod); - else - gk20a_writel(g, gm20b_blcg_bus[i].addr, - gm20b_blcg_bus[i].disable); - } -} - -void gm20b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gm20b_blcg_ctxsw_prog) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gm20b_blcg_ctxsw_prog[i].addr, - gm20b_blcg_ctxsw_prog[i].prod); - else - gk20a_writel(g, gm20b_blcg_ctxsw_prog[i].addr, - gm20b_blcg_ctxsw_prog[i].disable); - } -} - -void gm20b_blcg_fb_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gm20b_blcg_fb) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gm20b_blcg_fb[i].addr, - gm20b_blcg_fb[i].prod); - else - gk20a_writel(g, gm20b_blcg_fb[i].addr, - gm20b_blcg_fb[i].disable); - } -} - -void gm20b_blcg_fifo_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gm20b_blcg_fifo) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gm20b_blcg_fifo[i].addr, - gm20b_blcg_fifo[i].prod); - else - gk20a_writel(g, gm20b_blcg_fifo[i].addr, - gm20b_blcg_fifo[i].disable); - } -} - -void gm20b_blcg_gr_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gm20b_blcg_gr) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gm20b_blcg_gr[i].addr, - gm20b_blcg_gr[i].prod); - else - gk20a_writel(g, gm20b_blcg_gr[i].addr, - gm20b_blcg_gr[i].disable); - } -} - -void gm20b_blcg_ltc_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gm20b_blcg_ltc) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gm20b_blcg_ltc[i].addr, - gm20b_blcg_ltc[i].prod); - else - gk20a_writel(g, gm20b_blcg_ltc[i].addr, - gm20b_blcg_ltc[i].disable); - } -} - -void gm20b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gm20b_blcg_pwr_csb) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gm20b_blcg_pwr_csb[i].addr, - gm20b_blcg_pwr_csb[i].prod); - else - gk20a_writel(g, gm20b_blcg_pwr_csb[i].addr, - gm20b_blcg_pwr_csb[i].disable); - } -} - -void gm20b_blcg_pmu_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gm20b_blcg_pmu) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gm20b_blcg_pmu[i].addr, - gm20b_blcg_pmu[i].prod); - else - gk20a_writel(g, gm20b_blcg_pmu[i].addr, - gm20b_blcg_pmu[i].disable); - } -} - -void gm20b_blcg_xbar_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gm20b_blcg_xbar) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gm20b_blcg_xbar[i].addr, - gm20b_blcg_xbar[i].prod); - else - gk20a_writel(g, gm20b_blcg_xbar[i].addr, - gm20b_blcg_xbar[i].disable); - } -} - -void gr_gm20b_pg_gr_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gm20b_pg_gr) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gm20b_pg_gr[i].addr, - gm20b_pg_gr[i].prod); - else - gk20a_writel(g, gm20b_pg_gr[i].addr, - gm20b_pg_gr[i].disable); - } -} - -#endif /* __gm20b_gating_reglist_h__ */ diff --git a/drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.h b/drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.h deleted file mode 100644 index 557f5689..00000000 --- a/drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * drivers/video/tegra/host/gm20b/gm20b_gating_reglist.h - * - * Copyright (c) 2014-2015, NVIDIA Corporation. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * This file is autogenerated. Do not edit. - */ - -#include "gk20a/gk20a.h" - -void gm20b_slcg_bus_load_gating_prod(struct gk20a *g, - bool prod); - -void gm20b_slcg_ce2_load_gating_prod(struct gk20a *g, - bool prod); - -void gm20b_slcg_chiplet_load_gating_prod(struct gk20a *g, - bool prod); - -void gm20b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, - bool prod); - -void gm20b_slcg_fb_load_gating_prod(struct gk20a *g, - bool prod); - -void gm20b_slcg_fifo_load_gating_prod(struct gk20a *g, - bool prod); - -void gr_gm20b_slcg_gr_load_gating_prod(struct gk20a *g, - bool prod); - -void ltc_gm20b_slcg_ltc_load_gating_prod(struct gk20a *g, - bool prod); - -void gm20b_slcg_perf_load_gating_prod(struct gk20a *g, - bool prod); - -void gm20b_slcg_priring_load_gating_prod(struct gk20a *g, - bool prod); - -void gm20b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, - bool prod); - -void gm20b_slcg_pmu_load_gating_prod(struct gk20a *g, - bool prod); - -void gm20b_slcg_therm_load_gating_prod(struct gk20a *g, - bool prod); - -void gm20b_slcg_xbar_load_gating_prod(struct gk20a *g, - bool prod); - -void gm20b_blcg_bus_load_gating_prod(struct gk20a *g, - bool prod); - -void gm20b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, - bool prod); - -void gm20b_blcg_fb_load_gating_prod(struct gk20a *g, - bool prod); - -void gm20b_blcg_fifo_load_gating_prod(struct gk20a *g, - bool prod); - -void gm20b_blcg_gr_load_gating_prod(struct gk20a *g, - bool prod); - -void gm20b_blcg_ltc_load_gating_prod(struct gk20a *g, - bool prod); - -void gm20b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, - bool prod); - -void gm20b_blcg_pmu_load_gating_prod(struct gk20a *g, - bool prod); - -void gm20b_blcg_xbar_load_gating_prod(struct gk20a *g, - bool prod); - -void gr_gm20b_pg_gr_load_gating_prod(struct gk20a *g, - bool prod); - diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index bbeaa40f..9fa6b6cc 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -43,7 +43,7 @@ #include "gr_gm20b.h" #include "ltc_gm20b.h" #include "fb_gm20b.h" -#include "gm20b_gating_reglist.h" +#include "clock_gating/gm20b_gating_reglist.h" #include "fifo_gm20b.h" #include "gr_ctx_gm20b.h" #include "mm_gm20b.h" diff --git a/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.c b/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.c deleted file mode 100644 index 169a1fee..00000000 --- a/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.c +++ /dev/null @@ -1,679 +0,0 @@ -/* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * This file is autogenerated. Do not edit. - */ - -#ifndef __gp106_gating_reglist_h__ -#define __gp106_gating_reglist_h__ - -#include "gp106_gating_reglist.h" -#include - -struct gating_desc { - u32 addr; - u32 prod; - u32 disable; -}; -/* slcg bus */ -static const struct gating_desc gp106_slcg_bus[] = { - {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, -}; - -/* slcg ce2 */ -static const struct gating_desc gp106_slcg_ce2[] = { - {.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe}, -}; - -/* slcg chiplet */ -static const struct gating_desc gp106_slcg_chiplet[] = { - {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010c0fc, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010d0fc, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, -}; - -/* slcg fb */ -static const struct gating_desc gp106_slcg_fb[] = { - {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, -}; - -/* slcg fifo */ -static const struct gating_desc gp106_slcg_fifo[] = { - {.addr = 0x000026ac, .prod = 0x00000000, .disable = 0x0001fffe}, -}; - -/* slcg gr */ -static const struct gating_desc gp106_slcg_gr[] = { - {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe}, - {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, - {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe}, - {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, - {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, - {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, - {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x03fffffe}, - {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, - {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, - {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe}, - {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, - {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe}, - {.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe}, - {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, - {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, - {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, - {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, - {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x0000ffff}, - {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e}, - {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e}, - {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, - {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe}, - {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe}, - {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, - {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe}, - {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe}, - {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe}, - {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe}, - {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, - {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, - {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, - {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x0000ffff}, -}; - -/* slcg ltc */ -static const struct gating_desc gp106_slcg_ltc[] = { - {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, -}; - -/* slcg perf */ -static const struct gating_desc gp106_slcg_perf[] = { - {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000}, - {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000}, - {.addr = 0x001bc218, .prod = 0x000001ff, .disable = 0x00000000}, - {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000}, - {.addr = 0x001b8218, .prod = 0x000001ff, .disable = 0x00000000}, - {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000}, -}; - -/* slcg PriRing */ -static const struct gating_desc gp106_slcg_priring[] = { - {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, -}; - -/* slcg pmu */ -static const struct gating_desc gp106_slcg_pmu[] = { - {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, - {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe}, - {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, -}; - -/* therm gr */ -static const struct gating_desc gp106_slcg_therm[] = { - {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, -}; - -/* slcg Xbar */ -static const struct gating_desc gp106_slcg_xbar[] = { - {.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe}, - {.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe}, - {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, - {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, - {.addr = 0x0013cc24, .prod = 0x00000000, .disable = 0x1ffffffe}, -}; - -/* blcg bus */ -static const struct gating_desc gp106_blcg_bus[] = { - {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, -}; - -/* blcg ce */ -static const struct gating_desc gp106_blcg_ce[] = { - {.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000}, -}; - -/* blcg fb */ -static const struct gating_desc gp106_blcg_fb[] = { - {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, - {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, -}; - -/* blcg fifo */ -static const struct gating_desc gp106_blcg_fifo[] = { - {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000}, -}; - -/* blcg gr */ -static const struct gating_desc gp106_blcg_gr[] = { - {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, - {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, - {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, - {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, - {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, - {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, - {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, - {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, - {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, - {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00418e0c, .prod = 0x00008444, .disable = 0x00000000}, - {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, - {.addr = 0x00419a40, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419a48, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419a50, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419a58, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419a60, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419a68, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419a70, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419a78, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419a80, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000}, - {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000}, - {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000}, - {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00419fd0, .prod = 0x0000c044, .disable = 0x00000000}, - {.addr = 0x00419fd8, .prod = 0x0000c046, .disable = 0x00000000}, - {.addr = 0x00419fe0, .prod = 0x0000c044, .disable = 0x00000000}, - {.addr = 0x00419fe8, .prod = 0x0000c042, .disable = 0x00000000}, - {.addr = 0x00419ff0, .prod = 0x0000c045, .disable = 0x00000000}, - {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000}, - {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000}, - {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, - {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, -}; - -/* blcg ltc */ -static const struct gating_desc gp106_blcg_ltc[] = { - {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, -}; - -/* blcg pmu */ -static const struct gating_desc gp106_blcg_pmu[] = { - {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, -}; - -/* blcg Xbar */ -static const struct gating_desc gp106_blcg_xbar[] = { - {.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000}, - {.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000}, - {.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000}, - {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x0013cc20, .prod = 0x00000042, .disable = 0x00000000}, -}; - -/* pg gr */ -static const struct gating_desc gp106_pg_gr[] = { -}; - -/* inline functions */ -void gp106_slcg_bus_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp106_slcg_bus) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp106_slcg_bus[i].addr, - gp106_slcg_bus[i].prod); - else - gk20a_writel(g, gp106_slcg_bus[i].addr, - gp106_slcg_bus[i].disable); - } -} - -void gp106_slcg_ce2_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp106_slcg_ce2) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp106_slcg_ce2[i].addr, - gp106_slcg_ce2[i].prod); - else - gk20a_writel(g, gp106_slcg_ce2[i].addr, - gp106_slcg_ce2[i].disable); - } -} - -void gp106_slcg_chiplet_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp106_slcg_chiplet) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp106_slcg_chiplet[i].addr, - gp106_slcg_chiplet[i].prod); - else - gk20a_writel(g, gp106_slcg_chiplet[i].addr, - gp106_slcg_chiplet[i].disable); - } -} - -void gp106_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, - bool prod) -{ -} - -void gp106_slcg_fb_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp106_slcg_fb) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp106_slcg_fb[i].addr, - gp106_slcg_fb[i].prod); - else - gk20a_writel(g, gp106_slcg_fb[i].addr, - gp106_slcg_fb[i].disable); - } -} - -void gp106_slcg_fifo_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp106_slcg_fifo) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp106_slcg_fifo[i].addr, - gp106_slcg_fifo[i].prod); - else - gk20a_writel(g, gp106_slcg_fifo[i].addr, - gp106_slcg_fifo[i].disable); - } -} - -void gr_gp106_slcg_gr_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp106_slcg_gr) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp106_slcg_gr[i].addr, - gp106_slcg_gr[i].prod); - else - gk20a_writel(g, gp106_slcg_gr[i].addr, - gp106_slcg_gr[i].disable); - } -} - -void ltc_gp106_slcg_ltc_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp106_slcg_ltc) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp106_slcg_ltc[i].addr, - gp106_slcg_ltc[i].prod); - else - gk20a_writel(g, gp106_slcg_ltc[i].addr, - gp106_slcg_ltc[i].disable); - } -} - -void gp106_slcg_perf_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp106_slcg_perf) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp106_slcg_perf[i].addr, - gp106_slcg_perf[i].prod); - else - gk20a_writel(g, gp106_slcg_perf[i].addr, - gp106_slcg_perf[i].disable); - } -} - -void gp106_slcg_priring_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp106_slcg_priring) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp106_slcg_priring[i].addr, - gp106_slcg_priring[i].prod); - else - gk20a_writel(g, gp106_slcg_priring[i].addr, - gp106_slcg_priring[i].disable); - } -} - -void gp106_slcg_pmu_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp106_slcg_pmu) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp106_slcg_pmu[i].addr, - gp106_slcg_pmu[i].prod); - else - gk20a_writel(g, gp106_slcg_pmu[i].addr, - gp106_slcg_pmu[i].disable); - } -} - -void gp106_slcg_therm_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp106_slcg_therm) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp106_slcg_therm[i].addr, - gp106_slcg_therm[i].prod); - else - gk20a_writel(g, gp106_slcg_therm[i].addr, - gp106_slcg_therm[i].disable); - } -} - -void gp106_slcg_xbar_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp106_slcg_xbar) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp106_slcg_xbar[i].addr, - gp106_slcg_xbar[i].prod); - else - gk20a_writel(g, gp106_slcg_xbar[i].addr, - gp106_slcg_xbar[i].disable); - } -} - -void gp106_blcg_bus_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp106_blcg_bus) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp106_blcg_bus[i].addr, - gp106_blcg_bus[i].prod); - else - gk20a_writel(g, gp106_blcg_bus[i].addr, - gp106_blcg_bus[i].disable); - } -} - -void gp106_blcg_ce_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp106_blcg_ce) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp106_blcg_ce[i].addr, - gp106_blcg_ce[i].prod); - else - gk20a_writel(g, gp106_blcg_ce[i].addr, - gp106_blcg_ce[i].disable); - } -} - -void gp106_blcg_fb_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp106_blcg_fb) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp106_blcg_fb[i].addr, - gp106_blcg_fb[i].prod); - else - gk20a_writel(g, gp106_blcg_fb[i].addr, - gp106_blcg_fb[i].disable); - } -} - -void gp106_blcg_fifo_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp106_blcg_fifo) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp106_blcg_fifo[i].addr, - gp106_blcg_fifo[i].prod); - else - gk20a_writel(g, gp106_blcg_fifo[i].addr, - gp106_blcg_fifo[i].disable); - } -} - -void gp106_blcg_gr_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp106_blcg_gr) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp106_blcg_gr[i].addr, - gp106_blcg_gr[i].prod); - else - gk20a_writel(g, gp106_blcg_gr[i].addr, - gp106_blcg_gr[i].disable); - } -} - -void gp106_blcg_ltc_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp106_blcg_ltc) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp106_blcg_ltc[i].addr, - gp106_blcg_ltc[i].prod); - else - gk20a_writel(g, gp106_blcg_ltc[i].addr, - gp106_blcg_ltc[i].disable); - } -} - -void gp106_blcg_pmu_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp106_blcg_pmu) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp106_blcg_pmu[i].addr, - gp106_blcg_pmu[i].prod); - else - gk20a_writel(g, gp106_blcg_pmu[i].addr, - gp106_blcg_pmu[i].disable); - } -} - -void gp106_blcg_xbar_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp106_blcg_xbar) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp106_blcg_xbar[i].addr, - gp106_blcg_xbar[i].prod); - else - gk20a_writel(g, gp106_blcg_xbar[i].addr, - gp106_blcg_xbar[i].disable); - } -} - -void gr_gp106_pg_gr_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp106_pg_gr) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp106_pg_gr[i].addr, - gp106_pg_gr[i].prod); - else - gk20a_writel(g, gp106_pg_gr[i].addr, - gp106_pg_gr[i].disable); - } -} - -#endif /* __gp106_gating_reglist_h__ */ diff --git a/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.h b/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.h deleted file mode 100644 index 773abde6..00000000 --- a/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2015-2016, NVIDIA Corporation. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "gk20a/gk20a.h" - -void gp106_slcg_bus_load_gating_prod(struct gk20a *g, - bool prod); - -void gp106_slcg_ce2_load_gating_prod(struct gk20a *g, - bool prod); - -void gp106_slcg_chiplet_load_gating_prod(struct gk20a *g, - bool prod); - -void gp106_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, - bool prod); - -void gp106_slcg_fb_load_gating_prod(struct gk20a *g, - bool prod); - -void gp106_slcg_fifo_load_gating_prod(struct gk20a *g, - bool prod); - -void gr_gp106_slcg_gr_load_gating_prod(struct gk20a *g, - bool prod); - -void ltc_gp106_slcg_ltc_load_gating_prod(struct gk20a *g, - bool prod); - -void gp106_slcg_perf_load_gating_prod(struct gk20a *g, - bool prod); - -void gp106_slcg_priring_load_gating_prod(struct gk20a *g, - bool prod); - -void gp106_slcg_pmu_load_gating_prod(struct gk20a *g, - bool prod); - -void gp106_slcg_therm_load_gating_prod(struct gk20a *g, - bool prod); - -void gp106_slcg_xbar_load_gating_prod(struct gk20a *g, - bool prod); - -void gp106_blcg_bus_load_gating_prod(struct gk20a *g, - bool prod); - -void gp106_blcg_ce_load_gating_prod(struct gk20a *g, - bool prod); - -void gp106_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, - bool prod); - -void gp106_blcg_fb_load_gating_prod(struct gk20a *g, - bool prod); - -void gp106_blcg_fifo_load_gating_prod(struct gk20a *g, - bool prod); - -void gp106_blcg_gr_load_gating_prod(struct gk20a *g, - bool prod); - -void gp106_blcg_ltc_load_gating_prod(struct gk20a *g, - bool prod); - -void gp106_blcg_pmu_load_gating_prod(struct gk20a *g, - bool prod); - -void gp106_blcg_xbar_load_gating_prod(struct gk20a *g, - bool prod); - -void gr_gp106_pg_gr_load_gating_prod(struct gk20a *g, - bool prod); - diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 66123fab..7a8a8e16 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -78,7 +78,7 @@ #include "gp106/gr_ctx_gp106.h" #include "gp106/gr_gp106.h" #include "gp106/fb_gp106.h" -#include "gp106/gp106_gating_reglist.h" +#include "clock_gating/gp106_gating_reglist.h" #include "gp106/flcn_gp106.h" #include "gp106/fuse_gp106.h" diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c deleted file mode 100644 index 4355f698..00000000 --- a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c +++ /dev/null @@ -1,742 +0,0 @@ -/* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * This file is autogenerated. Do not edit. - */ - -#ifndef __gp10b_gating_reglist_h__ -#define __gp10b_gating_reglist_h__ - -#include "gp10b_gating_reglist.h" -#include - -struct gating_desc { - u32 addr; - u32 prod; - u32 disable; -}; -/* slcg bus */ -static const struct gating_desc gp10b_slcg_bus[] = { - {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, -}; - -/* slcg ce2 */ -static const struct gating_desc gp10b_slcg_ce2[] = { - {.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe}, -}; - -/* slcg chiplet */ -static const struct gating_desc gp10b_slcg_chiplet[] = { - {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, -}; - -/* slcg fb */ -static const struct gating_desc gp10b_slcg_fb[] = { - {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, -}; - -/* slcg fifo */ -static const struct gating_desc gp10b_slcg_fifo[] = { - {.addr = 0x000026ac, .prod = 0x00000f40, .disable = 0x0001fffe}, -}; - -/* slcg gr */ -static const struct gating_desc gp10b_slcg_gr[] = { - {.addr = 0x004041f4, .prod = 0x00000002, .disable = 0x03fffffe}, - {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, - {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe}, - {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00406004, .prod = 0x00000200, .disable = 0x0001fffe}, - {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, - {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, - {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, - {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x03fffffe}, - {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, - {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, - {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x0000003e}, - {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, - {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00418c74, .prod = 0xffffffc0, .disable = 0xfffffffe}, - {.addr = 0x00418cf4, .prod = 0xfffffffc, .disable = 0xfffffffe}, - {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, - {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, - {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, - {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, - {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x0000ffff}, - {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e}, - {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e}, - {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, - {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe}, - {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe}, - {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, - {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe}, - {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe}, - {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe}, - {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe}, - {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, - {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, - {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, - {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x0000ffff}, -}; - -/* slcg ltc */ -static const struct gating_desc gp10b_slcg_ltc[] = { - {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, -}; - -/* slcg perf */ -static const struct gating_desc gp10b_slcg_perf[] = { - {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000}, - {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000}, - {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000}, - {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000}, -}; - -/* slcg PriRing */ -static const struct gating_desc gp10b_slcg_priring[] = { - {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, -}; - -/* slcg pwr_csb */ -static const struct gating_desc gp10b_slcg_pwr_csb[] = { - {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe}, - {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, - {.addr = 0x00000a74, .prod = 0x00004000, .disable = 0x00007ffe}, - {.addr = 0x000016b8, .prod = 0x00000000, .disable = 0x0000000f}, -}; - -/* slcg pmu */ -static const struct gating_desc gp10b_slcg_pmu[] = { - {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, - {.addr = 0x0010aa74, .prod = 0x00004000, .disable = 0x00007ffe}, - {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, -}; - -/* therm gr */ -static const struct gating_desc gp10b_slcg_therm[] = { - {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, -}; - -/* slcg Xbar */ -static const struct gating_desc gp10b_slcg_xbar[] = { - {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, - {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, -}; - -/* blcg bus */ -static const struct gating_desc gp10b_blcg_bus[] = { - {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, -}; - -/* blcg ce */ -static const struct gating_desc gp10b_blcg_ce[] = { - {.addr = 0x00104200, .prod = 0x00008242, .disable = 0x00000000}, -}; - -/* blcg ctxsw prog */ -static const struct gating_desc gp10b_blcg_ctxsw_prog[] = { -}; - -/* blcg fb */ -static const struct gating_desc gp10b_blcg_fb[] = { - {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, - {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, -}; - -/* blcg fifo */ -static const struct gating_desc gp10b_blcg_fifo[] = { - {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000}, -}; - -/* blcg gr */ -static const struct gating_desc gp10b_blcg_gr[] = { - {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, - {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, - {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, - {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, - {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, - /* fix priv error */ - /*{.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000},*/ - {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, - {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, - {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, - {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, - {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00418e0c, .prod = 0x00008444, .disable = 0x00000000}, - {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, - {.addr = 0x00419a40, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419a48, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419a50, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419a58, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419a60, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419a68, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419a70, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419a78, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419a80, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000}, - {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000}, - {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000}, - {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00419fd0, .prod = 0x0000c044, .disable = 0x00000000}, - {.addr = 0x00419fd8, .prod = 0x0000c046, .disable = 0x00000000}, - {.addr = 0x00419fe0, .prod = 0x0000c044, .disable = 0x00000000}, - {.addr = 0x00419fe8, .prod = 0x0000c042, .disable = 0x00000000}, - {.addr = 0x00419ff0, .prod = 0x0000c045, .disable = 0x00000000}, - {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000}, - {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000}, - {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, - {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, -}; - -/* blcg ltc */ -static const struct gating_desc gp10b_blcg_ltc[] = { - {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, -}; - -/* blcg pwr_csb */ -static const struct gating_desc gp10b_blcg_pwr_csb[] = { - {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, -}; - -/* blcg pmu */ -static const struct gating_desc gp10b_blcg_pmu[] = { - {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, -}; - -/* blcg Xbar */ -static const struct gating_desc gp10b_blcg_xbar[] = { - {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, -}; - -/* pg gr */ -static const struct gating_desc gp10b_pg_gr[] = { -}; - -/* inline functions */ -void gp10b_slcg_bus_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_bus) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_bus[i].addr, - gp10b_slcg_bus[i].prod); - else - gk20a_writel(g, gp10b_slcg_bus[i].addr, - gp10b_slcg_bus[i].disable); - } -} - -void gp10b_slcg_ce2_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_ce2) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_ce2[i].addr, - gp10b_slcg_ce2[i].prod); - else - gk20a_writel(g, gp10b_slcg_ce2[i].addr, - gp10b_slcg_ce2[i].disable); - } -} - -void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_chiplet) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_chiplet[i].addr, - gp10b_slcg_chiplet[i].prod); - else - gk20a_writel(g, gp10b_slcg_chiplet[i].addr, - gp10b_slcg_chiplet[i].disable); - } -} - -void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, - bool prod) -{ -} - -void gp10b_slcg_fb_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_fb) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_fb[i].addr, - gp10b_slcg_fb[i].prod); - else - gk20a_writel(g, gp10b_slcg_fb[i].addr, - gp10b_slcg_fb[i].disable); - } -} - -void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_fifo) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_fifo[i].addr, - gp10b_slcg_fifo[i].prod); - else - gk20a_writel(g, gp10b_slcg_fifo[i].addr, - gp10b_slcg_fifo[i].disable); - } -} - -void gr_gp10b_slcg_gr_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_gr) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_gr[i].addr, - gp10b_slcg_gr[i].prod); - else - gk20a_writel(g, gp10b_slcg_gr[i].addr, - gp10b_slcg_gr[i].disable); - } -} - -void ltc_gp10b_slcg_ltc_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_ltc) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_ltc[i].addr, - gp10b_slcg_ltc[i].prod); - else - gk20a_writel(g, gp10b_slcg_ltc[i].addr, - gp10b_slcg_ltc[i].disable); - } -} - -void gp10b_slcg_perf_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_perf) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_perf[i].addr, - gp10b_slcg_perf[i].prod); - else - gk20a_writel(g, gp10b_slcg_perf[i].addr, - gp10b_slcg_perf[i].disable); - } -} - -void gp10b_slcg_priring_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_priring) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_priring[i].addr, - gp10b_slcg_priring[i].prod); - else - gk20a_writel(g, gp10b_slcg_priring[i].addr, - gp10b_slcg_priring[i].disable); - } -} - -void gp10b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_pwr_csb) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr, - gp10b_slcg_pwr_csb[i].prod); - else - gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr, - gp10b_slcg_pwr_csb[i].disable); - } -} - -void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_pmu) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_pmu[i].addr, - gp10b_slcg_pmu[i].prod); - else - gk20a_writel(g, gp10b_slcg_pmu[i].addr, - gp10b_slcg_pmu[i].disable); - } -} - -void gp10b_slcg_therm_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_therm) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_therm[i].addr, - gp10b_slcg_therm[i].prod); - else - gk20a_writel(g, gp10b_slcg_therm[i].addr, - gp10b_slcg_therm[i].disable); - } -} - -void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_xbar) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_xbar[i].addr, - gp10b_slcg_xbar[i].prod); - else - gk20a_writel(g, gp10b_slcg_xbar[i].addr, - gp10b_slcg_xbar[i].disable); - } -} - -void gp10b_blcg_bus_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_blcg_bus) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_blcg_bus[i].addr, - gp10b_blcg_bus[i].prod); - else - gk20a_writel(g, gp10b_blcg_bus[i].addr, - gp10b_blcg_bus[i].disable); - } -} - -void gp10b_blcg_ce_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_blcg_ce) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_blcg_ce[i].addr, - gp10b_blcg_ce[i].prod); - else - gk20a_writel(g, gp10b_blcg_ce[i].addr, - gp10b_blcg_ce[i].disable); - } -} - -void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_blcg_ctxsw_prog) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr, - gp10b_blcg_ctxsw_prog[i].prod); - else - gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr, - gp10b_blcg_ctxsw_prog[i].disable); - } -} - -void gp10b_blcg_fb_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_blcg_fb) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_blcg_fb[i].addr, - gp10b_blcg_fb[i].prod); - else - gk20a_writel(g, gp10b_blcg_fb[i].addr, - gp10b_blcg_fb[i].disable); - } -} - -void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_blcg_fifo) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_blcg_fifo[i].addr, - gp10b_blcg_fifo[i].prod); - else - gk20a_writel(g, gp10b_blcg_fifo[i].addr, - gp10b_blcg_fifo[i].disable); - } -} - -void gp10b_blcg_gr_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_blcg_gr) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_blcg_gr[i].addr, - gp10b_blcg_gr[i].prod); - else - gk20a_writel(g, gp10b_blcg_gr[i].addr, - gp10b_blcg_gr[i].disable); - } -} - -void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_blcg_ltc) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_blcg_ltc[i].addr, - gp10b_blcg_ltc[i].prod); - else - gk20a_writel(g, gp10b_blcg_ltc[i].addr, - gp10b_blcg_ltc[i].disable); - } -} - -void gp10b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_blcg_pwr_csb) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr, - gp10b_blcg_pwr_csb[i].prod); - else - gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr, - gp10b_blcg_pwr_csb[i].disable); - } -} - -void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_blcg_pmu) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_blcg_pmu[i].addr, - gp10b_blcg_pmu[i].prod); - else - gk20a_writel(g, gp10b_blcg_pmu[i].addr, - gp10b_blcg_pmu[i].disable); - } -} - -void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_blcg_xbar) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_blcg_xbar[i].addr, - gp10b_blcg_xbar[i].prod); - else - gk20a_writel(g, gp10b_blcg_xbar[i].addr, - gp10b_blcg_xbar[i].disable); - } -} - -void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_pg_gr) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_pg_gr[i].addr, - gp10b_pg_gr[i].prod); - else - gk20a_writel(g, gp10b_pg_gr[i].addr, - gp10b_pg_gr[i].disable); - } -} - -#endif /* __gp10b_gating_reglist_h__ */ diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h deleted file mode 100644 index 7dbc6cac..00000000 --- a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2015-2016, NVIDIA Corporation. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "gk20a/gk20a.h" - -void gp10b_slcg_bus_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_slcg_ce2_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_slcg_fb_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g, - bool prod); - -void gr_gp10b_slcg_gr_load_gating_prod(struct gk20a *g, - bool prod); - -void ltc_gp10b_slcg_ltc_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_slcg_perf_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_slcg_priring_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_slcg_therm_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_blcg_bus_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_blcg_ce_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_blcg_fb_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_blcg_gr_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g, - bool prod); - -void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g, - bool prod); - diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index e4bf0fd7..6d7d32ac 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -48,7 +48,7 @@ #include "gp10b/pmu_gp10b.h" #include "gp10b/gr_ctx_gp10b.h" #include "gp10b/fifo_gp10b.h" -#include "gp10b/gp10b_gating_reglist.h" +#include "clock_gating/gp10b_gating_reglist.h" #include "gp10b/regops_gp10b.h" #include "gp10b/therm_gp10b.h" #include "gp10b/priv_ring_gp10b.h" diff --git a/drivers/gpu/nvgpu/gv100/gv100_gating_reglist.c b/drivers/gpu/nvgpu/gv100/gv100_gating_reglist.c deleted file mode 100644 index 60ec0282..00000000 --- a/drivers/gpu/nvgpu/gv100/gv100_gating_reglist.c +++ /dev/null @@ -1,951 +0,0 @@ -/* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * This file is autogenerated. Do not edit. - */ - -#ifndef __gv100_gating_reglist_h__ -#define __gv100_gating_reglist_h__ - -#include -#include "gv100_gating_reglist.h" - -struct gating_desc { - u32 addr; - u32 prod; - u32 disable; -}; -/* slcg bus */ -static const struct gating_desc gv100_slcg_bus[] = { - {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, -}; - -/* slcg ce2 */ -static const struct gating_desc gv100_slcg_ce2[] = { - {.addr = 0x00104204, .prod = 0x00000040, .disable = 0x000007fe}, -}; - -/* slcg chiplet */ -static const struct gating_desc gv100_slcg_chiplet[] = { - {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010c17c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010c27c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010c37c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010c47c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010c57c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010d17c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010d27c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010d37c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010d47c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010d57c, .prod = 0x00000000, .disable = 0x00000007}, - /* fix priv error */ - /*{.addr = 0x0010d67c, .prod = 0x00000000, .disable = 0x00000007},*/ - /*{.addr = 0x0010d77c, .prod = 0x00000000, .disable = 0x00000007},*/ - {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, -}; - -/* slcg fb */ -static const struct gating_desc gv100_slcg_fb[] = { - {.addr = 0x00100d14, .prod = 0x00000020, .disable = 0xfffffffe}, - {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x001facb4, .prod = 0x00000000, .disable = 0x000001fe}, -}; - -/* slcg fifo */ -static const struct gating_desc gv100_slcg_fifo[] = { - {.addr = 0x000026ec, .prod = 0x00000000, .disable = 0x0001fffe}, -}; - -/* slcg gr */ -static const struct gating_desc gv100_slcg_gr[] = { - {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe}, - {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, - {.addr = 0x00409894, .prod = 0x00000000, .disable = 0x0000fffe}, - {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00406004, .prod = 0x00000200, .disable = 0x0001fffe}, - {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, - {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, - {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00405bf4, .prod = 0x00000000, .disable = 0x00000002}, - {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, - {.addr = 0x0041a894, .prod = 0x00000000, .disable = 0x0000fffe}, - {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, - {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, - {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe}, - {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, - {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe}, - {.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe}, - {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, - {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, - {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, - {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, - {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x000000ff}, - {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, - {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, - /* fix priv error */ - /*{.addr = 0x00419c84, .prod = 0x0003fffe, .disable = 0x0003fffe},*/ - {.addr = 0x00419c8c, .prod = 0xffffff84, .disable = 0xfffffffe}, - {.addr = 0x00419c94, .prod = 0x00000240, .disable = 0x00007ffe}, - {.addr = 0x00419ca4, .prod = 0x00003ffe, .disable = 0x00003ffe}, - {.addr = 0x00419cac, .prod = 0x0001fffe, .disable = 0x0001fffe}, - {.addr = 0x00419a44, .prod = 0x00000008, .disable = 0x0000000e}, - {.addr = 0x00419a4c, .prod = 0x000001f8, .disable = 0x000001fe}, - {.addr = 0x00419a54, .prod = 0x0000003c, .disable = 0x0000003e}, - {.addr = 0x00419a5c, .prod = 0x0000000c, .disable = 0x0000000e}, - {.addr = 0x00419a64, .prod = 0x00000186, .disable = 0x000001fe}, - {.addr = 0x00419a7c, .prod = 0x0000003c, .disable = 0x0000003e}, - {.addr = 0x00419a84, .prod = 0x0000000c, .disable = 0x0000000e}, - {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, - {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, - {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, - {.addr = 0x00412814, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00412a84, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x004129ac, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00412a24, .prod = 0x00000000, .disable = 0x000000ff}, - {.addr = 0x00412c14, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00412e84, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00412dac, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00412e24, .prod = 0x00000000, .disable = 0x000000ff}, - /* fix priv error */ - /*{.addr = 0x00413014, .prod = 0x00000000, .disable = 0x0001fffe},*/ - /*{.addr = 0x00413284, .prod = 0x00000000, .disable = 0x0001fffe},*/ - /*{.addr = 0x004131ac, .prod = 0x00000000, .disable = 0x0001fffe},*/ - /*{.addr = 0x00413224, .prod = 0x00000000, .disable = 0x000000ff},*/ - /*{.addr = 0x00413414, .prod = 0x00000000, .disable = 0x0001fffe},*/ - /*{.addr = 0x00413684, .prod = 0x00000000, .disable = 0x0001fffe},*/ - /*{.addr = 0x004135ac, .prod = 0x00000000, .disable = 0x0001fffe},*/ - /*{.addr = 0x00413624, .prod = 0x00000000, .disable = 0x000000ff},*/ - /*{.addr = 0x00413814, .prod = 0x00000000, .disable = 0x0001fffe},*/ - /*{.addr = 0x00413a84, .prod = 0x00000000, .disable = 0x0001fffe},*/ - /*{.addr = 0x004139ac, .prod = 0x00000000, .disable = 0x0001fffe},*/ - /*{.addr = 0x00413a24, .prod = 0x00000000, .disable = 0x000000ff},*/ - /*{.addr = 0x00413c14, .prod = 0x00000000, .disable = 0x0001fffe},*/ - /*{.addr = 0x00413e84, .prod = 0x00000000, .disable = 0x0001fffe},*/ - /*{.addr = 0x00413dac, .prod = 0x00000000, .disable = 0x0001fffe},*/ - /*{.addr = 0x00413e24, .prod = 0x00000000, .disable = 0x000000ff},*/ - {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x000000ff}, -}; - -/* slcg ltc */ -static const struct gating_desc gv100_slcg_ltc[] = { - {.addr = 0x00154050, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x0015455c, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x0015475c, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x0015495c, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x00154b5c, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x0015435c, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x00156050, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x0015655c, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x0015675c, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x0015695c, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x00156b5c, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x0015635c, .prod = 0x00000000, .disable = 0xfffffffe}, - /* fix priv error */ - /*{.addr = 0x00158050, .prod = 0x00000000, .disable = 0xfffffffe},*/ - /*{.addr = 0x0015855c, .prod = 0x00000000, .disable = 0xfffffffe},*/ - /*{.addr = 0x0015875c, .prod = 0x00000000, .disable = 0xfffffffe},*/ - /*{.addr = 0x0015895c, .prod = 0x00000000, .disable = 0xfffffffe},*/ - /*{.addr = 0x00158b5c, .prod = 0x00000000, .disable = 0xfffffffe},*/ - /*{.addr = 0x0015835c, .prod = 0x00000000, .disable = 0xfffffffe},*/ - /*{.addr = 0x0015a050, .prod = 0x00000000, .disable = 0xfffffffe},*/ - /*{.addr = 0x0015a55c, .prod = 0x00000000, .disable = 0xfffffffe},*/ - /*{.addr = 0x0015a75c, .prod = 0x00000000, .disable = 0xfffffffe},*/ - /*{.addr = 0x0015a95c, .prod = 0x00000000, .disable = 0xfffffffe},*/ - /*{.addr = 0x0015ab5c, .prod = 0x00000000, .disable = 0xfffffffe},*/ - /*{.addr = 0x0015a35c, .prod = 0x00000000, .disable = 0xfffffffe},*/ - /*{.addr = 0x0015c050, .prod = 0x00000000, .disable = 0xfffffffe},*/ - /*{.addr = 0x0015c55c, .prod = 0x00000000, .disable = 0xfffffffe},*/ - /*{.addr = 0x0015c75c, .prod = 0x00000000, .disable = 0xfffffffe},*/ - /*{.addr = 0x0015c95c, .prod = 0x00000000, .disable = 0xfffffffe},*/ - /*{.addr = 0x0015cb5c, .prod = 0x00000000, .disable = 0xfffffffe},*/ - /*{.addr = 0x0015c35c, .prod = 0x00000000, .disable = 0xfffffffe},*/ - /*{.addr = 0x0015e050, .prod = 0x00000000, .disable = 0xfffffffe},*/ - /*{.addr = 0x0015e55c, .prod = 0x00000000, .disable = 0xfffffffe},*/ - /*{.addr = 0x0015e75c, .prod = 0x00000000, .disable = 0xfffffffe},*/ - /*{.addr = 0x0015e95c, .prod = 0x00000000, .disable = 0xfffffffe},*/ - /*{.addr = 0x0015eb5c, .prod = 0x00000000, .disable = 0xfffffffe},*/ - /*{.addr = 0x0015e35c, .prod = 0x00000000, .disable = 0xfffffffe},*/ - {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, -}; - -/* slcg perf */ -static const struct gating_desc gv100_slcg_perf[] = { - {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00246218, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00246418, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00246618, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00246818, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00246a18, .prod = 0xffffffff, .disable = 0x00000000}, - /* fix priv error */ - /*{.addr = 0x00246c18, .prod = 0xffffffff, .disable = 0x00000000},*/ - /*{.addr = 0x00246e18, .prod = 0xffffffff, .disable = 0x00000000},*/ - {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00246218, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00246418, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00246618, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00246818, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00246a18, .prod = 0xffffffff, .disable = 0x00000000}, - /* fix priv error */ - /*{.addr = 0x00246c18, .prod = 0xffffffff, .disable = 0x00000000},*/ - /*{.addr = 0x00246e18, .prod = 0xffffffff, .disable = 0x00000000},*/ - {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00244218, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00244418, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00244618, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00244818, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00244a18, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00244218, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00244418, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00244618, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00244818, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00244a18, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x0024a124, .prod = 0x00000001, .disable = 0x00000000}, -}; - -/* slcg PriRing */ -static const struct gating_desc gv100_slcg_priring[] = { - {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, -}; - -/* slcg pwr_csb */ -static const struct gating_desc gv100_slcg_pwr_csb[] = { - {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe}, - {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, - {.addr = 0x00000a74, .prod = 0x00000000, .disable = 0x00007ffe}, - {.addr = 0x000016b8, .prod = 0x00000008, .disable = 0x0000000f}, -}; - -/* slcg pmu */ -static const struct gating_desc gv100_slcg_pmu[] = { - {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, - {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe}, - {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, -}; - -/* therm gr */ -static const struct gating_desc gv100_slcg_therm[] = { - {.addr = 0x000206b8, .prod = 0x00000008, .disable = 0x0000000f}, -}; - -/* slcg Xbar */ -static const struct gating_desc gv100_slcg_xbar[] = { - {.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe}, - {.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe}, - {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, - {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, - {.addr = 0x0013cc24, .prod = 0x00000000, .disable = 0x1ffffffe}, - {.addr = 0x0013cc44, .prod = 0x00000000, .disable = 0x1ffffffe}, - {.addr = 0x0013cc64, .prod = 0x00000000, .disable = 0x1ffffffe}, - {.addr = 0x0013cc84, .prod = 0x00000000, .disable = 0x1ffffffe}, - {.addr = 0x0013cca4, .prod = 0x00000000, .disable = 0x1ffffffe}, -}; - -/* blcg bus */ -static const struct gating_desc gv100_blcg_bus[] = { - {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, -}; - -/* blcg ce */ -static const struct gating_desc gv100_blcg_ce[] = { - {.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000}, -}; - -/* blcg ctxsw prog */ -static const struct gating_desc gv100_blcg_ctxsw_prog[] = { -}; - -/* blcg fb */ -static const struct gating_desc gv100_blcg_fb[] = { - {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, - {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, - /* fix priv error */ - /*{.addr = 0x00100d1c, .prod = 0x00000042, .disable = 0x00000000},*/ - {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, - {.addr = 0x001facb0, .prod = 0x00004242, .disable = 0x00000000}, -}; - -/* blcg fifo */ -static const struct gating_desc gv100_blcg_fifo[] = { - {.addr = 0x000026e0, .prod = 0x0000c242, .disable = 0x00000000}, -}; - -/* blcg gr */ -static const struct gating_desc gv100_blcg_gr[] = { - {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, - {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, - {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, - {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, - {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, - {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, - {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, - {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, - {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, - {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00418e0c, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, - {.addr = 0x00419868, .prod = 0x00008243, .disable = 0x00000000}, - {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00419c80, .prod = 0x00004048, .disable = 0x00000000}, - {.addr = 0x00419c88, .prod = 0x00004048, .disable = 0x00000000}, - {.addr = 0x00419c90, .prod = 0x0000004a, .disable = 0x00000000}, - {.addr = 0x00419c98, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x00419ca0, .prod = 0x00000043, .disable = 0x00000000}, - {.addr = 0x00419ca8, .prod = 0x00000003, .disable = 0x00000000}, - {.addr = 0x00419cb0, .prod = 0x00000002, .disable = 0x00000000}, - {.addr = 0x00419a40, .prod = 0x00000545, .disable = 0x00000000}, - {.addr = 0x00419a48, .prod = 0x00004545, .disable = 0x00000000}, - {.addr = 0x00419a50, .prod = 0x00004545, .disable = 0x00000000}, - {.addr = 0x00419a58, .prod = 0x00004545, .disable = 0x00000000}, - {.addr = 0x00419a60, .prod = 0x00000505, .disable = 0x00000000}, - {.addr = 0x00419a68, .prod = 0x00000505, .disable = 0x00000000}, - {.addr = 0x00419a78, .prod = 0x00000505, .disable = 0x00000000}, - {.addr = 0x00419a80, .prod = 0x00004545, .disable = 0x00000000}, - {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, - {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00412810, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00412a80, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x004129a8, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00412c10, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00412e80, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00412da8, .prod = 0x0000c242, .disable = 0x00000000}, - /* fix priv error */ - /*{.addr = 0x00413010, .prod = 0x0000c242, .disable = 0x00000000},*/ - /*{.addr = 0x00413280, .prod = 0x0000c242, .disable = 0x00000000},*/ - /*{.addr = 0x004131a8, .prod = 0x0000c242, .disable = 0x00000000},*/ - /*{.addr = 0x00413410, .prod = 0x0000c242, .disable = 0x00000000},*/ - /*{.addr = 0x00413680, .prod = 0x0000c242, .disable = 0x00000000},*/ - /*{.addr = 0x004135a8, .prod = 0x0000c242, .disable = 0x00000000},*/ - /*{.addr = 0x00413810, .prod = 0x0000c242, .disable = 0x00000000},*/ - /*{.addr = 0x00413a80, .prod = 0x0000c242, .disable = 0x00000000},*/ - /*{.addr = 0x004139a8, .prod = 0x0000c242, .disable = 0x00000000},*/ - /*{.addr = 0x00413c10, .prod = 0x0000c242, .disable = 0x00000000},*/ - /*{.addr = 0x00413e80, .prod = 0x0000c242, .disable = 0x00000000},*/ - /*{.addr = 0x00413da8, .prod = 0x0000c242, .disable = 0x00000000},*/ - {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, -}; - -/* blcg ltc */ -static const struct gating_desc gv100_blcg_ltc[] = { - {.addr = 0x00154030, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x00154040, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x001545e0, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x001545c8, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x001547e0, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x001547c8, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x001549e0, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x001549c8, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x00154be0, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x00154bc8, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x001543e0, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x001543c8, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x00156030, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x00156040, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x001565e0, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x001565c8, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x001567e0, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x001567c8, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x001569e0, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x001569c8, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x00156be0, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x00156bc8, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x001563e0, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x001563c8, .prod = 0x00000044, .disable = 0x00000000}, - /* fix priv error */ - /*{.addr = 0x00158030, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x00158040, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x001585e0, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x001585c8, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x001587e0, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x001587c8, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x001589e0, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x001589c8, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x00158be0, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x00158bc8, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x001583e0, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x001583c8, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015a030, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015a040, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015a5e0, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015a5c8, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015a7e0, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015a7c8, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015a9e0, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015a9c8, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015abe0, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015abc8, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015a3e0, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015a3c8, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015c030, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015c040, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015c5e0, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015c5c8, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015c7e0, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015c7c8, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015c9e0, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015c9c8, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015cbe0, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015cbc8, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015c3e0, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015c3c8, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015e030, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015e040, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015e5e0, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015e5c8, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015e7e0, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015e7c8, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015e9e0, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015e9c8, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015ebe0, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015ebc8, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015e3e0, .prod = 0x00000044, .disable = 0x00000000},*/ - /*{.addr = 0x0015e3c8, .prod = 0x00000044, .disable = 0x00000000},*/ - {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, -}; - -/* blcg pwr_csb */ -static const struct gating_desc gv100_blcg_pwr_csb[] = { - {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, -}; - -/* blcg pmu */ -static const struct gating_desc gv100_blcg_pmu[] = { - {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, -}; - -/* blcg Xbar */ -static const struct gating_desc gv100_blcg_xbar[] = { - {.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000}, - {.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000}, - {.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000}, - {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x0013cc20, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x0013cc40, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x0013cc60, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x0013cc80, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x0013cca0, .prod = 0x00000042, .disable = 0x00000000}, -}; - -/* pg gr */ -static const struct gating_desc gv100_pg_gr[] = { -}; - -/* inline functions */ -void gv100_slcg_bus_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv100_slcg_bus) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv100_slcg_bus[i].addr, - gv100_slcg_bus[i].prod); - else - gk20a_writel(g, gv100_slcg_bus[i].addr, - gv100_slcg_bus[i].disable); - } -} - -void gv100_slcg_ce2_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv100_slcg_ce2) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv100_slcg_ce2[i].addr, - gv100_slcg_ce2[i].prod); - else - gk20a_writel(g, gv100_slcg_ce2[i].addr, - gv100_slcg_ce2[i].disable); - } -} - -void gv100_slcg_chiplet_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv100_slcg_chiplet) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv100_slcg_chiplet[i].addr, - gv100_slcg_chiplet[i].prod); - else - gk20a_writel(g, gv100_slcg_chiplet[i].addr, - gv100_slcg_chiplet[i].disable); - } -} - -void gv100_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, - bool prod) -{ -} - -void gv100_slcg_fb_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv100_slcg_fb) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv100_slcg_fb[i].addr, - gv100_slcg_fb[i].prod); - else - gk20a_writel(g, gv100_slcg_fb[i].addr, - gv100_slcg_fb[i].disable); - } -} - -void gv100_slcg_fifo_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv100_slcg_fifo) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv100_slcg_fifo[i].addr, - gv100_slcg_fifo[i].prod); - else - gk20a_writel(g, gv100_slcg_fifo[i].addr, - gv100_slcg_fifo[i].disable); - } -} - -void gr_gv100_slcg_gr_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv100_slcg_gr) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv100_slcg_gr[i].addr, - gv100_slcg_gr[i].prod); - else - gk20a_writel(g, gv100_slcg_gr[i].addr, - gv100_slcg_gr[i].disable); - } -} - -void ltc_gv100_slcg_ltc_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv100_slcg_ltc) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv100_slcg_ltc[i].addr, - gv100_slcg_ltc[i].prod); - else - gk20a_writel(g, gv100_slcg_ltc[i].addr, - gv100_slcg_ltc[i].disable); - } -} - -void gv100_slcg_perf_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv100_slcg_perf) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv100_slcg_perf[i].addr, - gv100_slcg_perf[i].prod); - else - gk20a_writel(g, gv100_slcg_perf[i].addr, - gv100_slcg_perf[i].disable); - } -} - -void gv100_slcg_priring_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv100_slcg_priring) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv100_slcg_priring[i].addr, - gv100_slcg_priring[i].prod); - else - gk20a_writel(g, gv100_slcg_priring[i].addr, - gv100_slcg_priring[i].disable); - } -} - -void gv100_slcg_pwr_csb_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv100_slcg_pwr_csb) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv100_slcg_pwr_csb[i].addr, - gv100_slcg_pwr_csb[i].prod); - else - gk20a_writel(g, gv100_slcg_pwr_csb[i].addr, - gv100_slcg_pwr_csb[i].disable); - } -} - -void gv100_slcg_pmu_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv100_slcg_pmu) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv100_slcg_pmu[i].addr, - gv100_slcg_pmu[i].prod); - else - gk20a_writel(g, gv100_slcg_pmu[i].addr, - gv100_slcg_pmu[i].disable); - } -} - -void gv100_slcg_therm_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv100_slcg_therm) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv100_slcg_therm[i].addr, - gv100_slcg_therm[i].prod); - else - gk20a_writel(g, gv100_slcg_therm[i].addr, - gv100_slcg_therm[i].disable); - } -} - -void gv100_slcg_xbar_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv100_slcg_xbar) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv100_slcg_xbar[i].addr, - gv100_slcg_xbar[i].prod); - else - gk20a_writel(g, gv100_slcg_xbar[i].addr, - gv100_slcg_xbar[i].disable); - } -} - -void gv100_blcg_bus_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv100_blcg_bus) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv100_blcg_bus[i].addr, - gv100_blcg_bus[i].prod); - else - gk20a_writel(g, gv100_blcg_bus[i].addr, - gv100_blcg_bus[i].disable); - } -} - -void gv100_blcg_ce_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv100_blcg_ce) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv100_blcg_ce[i].addr, - gv100_blcg_ce[i].prod); - else - gk20a_writel(g, gv100_blcg_ce[i].addr, - gv100_blcg_ce[i].disable); - } -} - -void gv100_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv100_blcg_ctxsw_prog) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv100_blcg_ctxsw_prog[i].addr, - gv100_blcg_ctxsw_prog[i].prod); - else - gk20a_writel(g, gv100_blcg_ctxsw_prog[i].addr, - gv100_blcg_ctxsw_prog[i].disable); - } -} - -void gv100_blcg_fb_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv100_blcg_fb) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv100_blcg_fb[i].addr, - gv100_blcg_fb[i].prod); - else - gk20a_writel(g, gv100_blcg_fb[i].addr, - gv100_blcg_fb[i].disable); - } -} - -void gv100_blcg_fifo_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv100_blcg_fifo) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv100_blcg_fifo[i].addr, - gv100_blcg_fifo[i].prod); - else - gk20a_writel(g, gv100_blcg_fifo[i].addr, - gv100_blcg_fifo[i].disable); - } -} - -void gv100_blcg_gr_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv100_blcg_gr) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv100_blcg_gr[i].addr, - gv100_blcg_gr[i].prod); - else - gk20a_writel(g, gv100_blcg_gr[i].addr, - gv100_blcg_gr[i].disable); - } -} - -void gv100_blcg_ltc_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv100_blcg_ltc) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv100_blcg_ltc[i].addr, - gv100_blcg_ltc[i].prod); - else - gk20a_writel(g, gv100_blcg_ltc[i].addr, - gv100_blcg_ltc[i].disable); - } -} - -void gv100_blcg_pwr_csb_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv100_blcg_pwr_csb) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv100_blcg_pwr_csb[i].addr, - gv100_blcg_pwr_csb[i].prod); - else - gk20a_writel(g, gv100_blcg_pwr_csb[i].addr, - gv100_blcg_pwr_csb[i].disable); - } -} - -void gv100_blcg_pmu_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv100_blcg_pmu) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv100_blcg_pmu[i].addr, - gv100_blcg_pmu[i].prod); - else - gk20a_writel(g, gv100_blcg_pmu[i].addr, - gv100_blcg_pmu[i].disable); - } -} - -void gv100_blcg_xbar_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv100_blcg_xbar) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv100_blcg_xbar[i].addr, - gv100_blcg_xbar[i].prod); - else - gk20a_writel(g, gv100_blcg_xbar[i].addr, - gv100_blcg_xbar[i].disable); - } -} - -void gr_gv100_pg_gr_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv100_pg_gr) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv100_pg_gr[i].addr, - gv100_pg_gr[i].prod); - else - gk20a_writel(g, gv100_pg_gr[i].addr, - gv100_pg_gr[i].disable); - } -} - -#endif /* __gv100_gating_reglist_h__ */ diff --git a/drivers/gpu/nvgpu/gv100/gv100_gating_reglist.h b/drivers/gpu/nvgpu/gv100/gv100_gating_reglist.h deleted file mode 100644 index fa231d26..00000000 --- a/drivers/gpu/nvgpu/gv100/gv100_gating_reglist.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA Corporation. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "gk20a/gk20a.h" - -void gv100_slcg_bus_load_gating_prod(struct gk20a *g, - bool prod); - -void gv100_slcg_ce2_load_gating_prod(struct gk20a *g, - bool prod); - -void gv100_slcg_chiplet_load_gating_prod(struct gk20a *g, - bool prod); - -void gv100_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, - bool prod); - -void gv100_slcg_fb_load_gating_prod(struct gk20a *g, - bool prod); - -void gv100_slcg_fifo_load_gating_prod(struct gk20a *g, - bool prod); - -void gr_gv100_slcg_gr_load_gating_prod(struct gk20a *g, - bool prod); - -void ltc_gv100_slcg_ltc_load_gating_prod(struct gk20a *g, - bool prod); - -void gv100_slcg_perf_load_gating_prod(struct gk20a *g, - bool prod); - -void gv100_slcg_priring_load_gating_prod(struct gk20a *g, - bool prod); - -void gv100_slcg_pwr_csb_load_gating_prod(struct gk20a *g, - bool prod); - -void gv100_slcg_pmu_load_gating_prod(struct gk20a *g, - bool prod); - -void gv100_slcg_therm_load_gating_prod(struct gk20a *g, - bool prod); - -void gv100_slcg_xbar_load_gating_prod(struct gk20a *g, - bool prod); - -void gv100_blcg_bus_load_gating_prod(struct gk20a *g, - bool prod); - -void gv100_blcg_ce_load_gating_prod(struct gk20a *g, - bool prod); - -void gv100_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, - bool prod); - -void gv100_blcg_fb_load_gating_prod(struct gk20a *g, - bool prod); - -void gv100_blcg_fifo_load_gating_prod(struct gk20a *g, - bool prod); - -void gv100_blcg_gr_load_gating_prod(struct gk20a *g, - bool prod); - -void gv100_blcg_ltc_load_gating_prod(struct gk20a *g, - bool prod); - -void gv100_blcg_pwr_csb_load_gating_prod(struct gk20a *g, - bool prod); - -void gv100_blcg_pmu_load_gating_prod(struct gk20a *g, - bool prod); - -void gv100_blcg_xbar_load_gating_prod(struct gk20a *g, - bool prod); - -void gr_gv100_pg_gr_load_gating_prod(struct gk20a *g, - bool prod); - diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 28bad8d6..a4dd09ec 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -97,7 +97,7 @@ #include "gv100/pmu_gv100.h" #include "gv100/nvlink_gv100.h" #include "gv100/regops_gv100.h" -#include "gv100/gv100_gating_reglist.h" +#include "clock_gating/gv100_gating_reglist.h" #include #include diff --git a/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c b/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c deleted file mode 100644 index 4dbc87d5..00000000 --- a/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c +++ /dev/null @@ -1,750 +0,0 @@ -/* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * This file is autogenerated. Do not edit. - */ - -#ifndef __gv11b_gating_reglist_h__ -#define __gv11b_gating_reglist_h__ - -#include -#include "gv11b_gating_reglist.h" -#include - -struct gating_desc { - u32 addr; - u32 prod; - u32 disable; -}; -/* slcg bus */ -static const struct gating_desc gv11b_slcg_bus[] = { - {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, -}; - -/* slcg ce2 */ -static const struct gating_desc gv11b_slcg_ce2[] = { - {.addr = 0x00104204, .prod = 0x00000040, .disable = 0x000007fe}, -}; - -/* slcg chiplet */ -static const struct gating_desc gv11b_slcg_chiplet[] = { - {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, -}; - -/* slcg fb */ -static const struct gating_desc gv11b_slcg_fb[] = { - {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, -}; - -/* slcg fifo */ -static const struct gating_desc gv11b_slcg_fifo[] = { - {.addr = 0x000026ec, .prod = 0x00000000, .disable = 0x0001fffe}, -}; - -/* slcg gr */ -static const struct gating_desc gv11b_slcg_gr[] = { - {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe}, - {.addr = 0x00409134, .prod = 0x00020008, .disable = 0x0003fffe}, - {.addr = 0x00409894, .prod = 0x00000000, .disable = 0x0000fffe}, - {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00406004, .prod = 0x00000200, .disable = 0x0001fffe}, - {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, - {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, - /* fix priv error */ - /*{.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe},*/ - /*{.addr = 0x00405bf4, .prod = 0x00000000, .disable = 0x00000002},*/ - {.addr = 0x0041a134, .prod = 0x00020008, .disable = 0x0003fffe}, - {.addr = 0x0041a894, .prod = 0x00000000, .disable = 0x0000fffe}, - {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, - /* fix priv error */ - /*{.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe},*/ - {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, - {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe}, - {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, - {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, - /* fix priv error */ - /*{.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe},*/ - {.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe}, - {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, - {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, - {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, - {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, - {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x000000ff}, - {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, - {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, - {.addr = 0x00419c8c, .prod = 0xffffff84, .disable = 0xfffffffe}, - {.addr = 0x00419c94, .prod = 0x00080040, .disable = 0x000ffffe}, - {.addr = 0x00419ca4, .prod = 0x00003ffe, .disable = 0x00003ffe}, - {.addr = 0x00419cac, .prod = 0x0001fffe, .disable = 0x0001fffe}, - {.addr = 0x00419a44, .prod = 0x00000008, .disable = 0x0000000e}, - {.addr = 0x00419a4c, .prod = 0x000001f8, .disable = 0x000001fe}, - {.addr = 0x00419a54, .prod = 0x0000003c, .disable = 0x0000003e}, - {.addr = 0x00419a5c, .prod = 0x0000000c, .disable = 0x0000000e}, - {.addr = 0x00419a64, .prod = 0x000001ba, .disable = 0x000001fe}, - {.addr = 0x00419a7c, .prod = 0x0000003c, .disable = 0x0000003e}, - {.addr = 0x00419a84, .prod = 0x0000000c, .disable = 0x0000000e}, - {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, - {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, - /* fix priv error */ - /*{.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe},*/ - {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x000000ff}, -}; - -/* slcg ltc */ -static const struct gating_desc gv11b_slcg_ltc[] = { - {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, -}; - -/* slcg perf */ -static const struct gating_desc gv11b_slcg_perf[] = { - {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, - {.addr = 0x0024a124, .prod = 0x00000001, .disable = 0x00000000}, -}; - -/* slcg PriRing */ -static const struct gating_desc gv11b_slcg_priring[] = { - {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, -}; - -/* slcg pwr_csb */ -static const struct gating_desc gv11b_slcg_pwr_csb[] = { - {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe}, - {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, - {.addr = 0x00000a74, .prod = 0x00004040, .disable = 0x00007ffe}, - {.addr = 0x000206b8, .prod = 0x00000008, .disable = 0x0000000f}, -}; - -/* slcg pmu */ -static const struct gating_desc gv11b_slcg_pmu[] = { - {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, - {.addr = 0x0010aa74, .prod = 0x00004040, .disable = 0x00007ffe}, - {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, -}; - -/* therm gr */ -static const struct gating_desc gv11b_slcg_therm[] = { - {.addr = 0x000206b8, .prod = 0x00000008, .disable = 0x0000000f}, -}; - -/* slcg Xbar */ -static const struct gating_desc gv11b_slcg_xbar[] = { - {.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe}, - {.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe}, - {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, - {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, -}; - -/* blcg bus */ -static const struct gating_desc gv11b_blcg_bus[] = { - {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, -}; - -/* blcg ce */ -static const struct gating_desc gv11b_blcg_ce[] = { - {.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000}, -}; - -/* blcg ctxsw prog */ -static const struct gating_desc gv11b_blcg_ctxsw_prog[] = { -}; - -/* blcg fb */ -static const struct gating_desc gv11b_blcg_fb[] = { - {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, - {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, -}; - -/* blcg fifo */ -static const struct gating_desc gv11b_blcg_fifo[] = { - {.addr = 0x000026e0, .prod = 0x0000c244, .disable = 0x00000000}, -}; - -/* blcg gr */ -static const struct gating_desc gv11b_blcg_gr[] = { - {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, - {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, - {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, - {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, - {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, - {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, - {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, - {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, - {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, - {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00418e0c, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, - {.addr = 0x00419868, .prod = 0x00008243, .disable = 0x00000000}, - {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00419c80, .prod = 0x00004045, .disable = 0x00000000}, - {.addr = 0x00419c88, .prod = 0x00004043, .disable = 0x00000000}, - {.addr = 0x00419c90, .prod = 0x0000004a, .disable = 0x00000000}, - {.addr = 0x00419c98, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x00419ca0, .prod = 0x00000043, .disable = 0x00000000}, - {.addr = 0x00419ca8, .prod = 0x00000003, .disable = 0x00000000}, - {.addr = 0x00419cb0, .prod = 0x00000002, .disable = 0x00000000}, - {.addr = 0x00419a40, .prod = 0x00000242, .disable = 0x00000000}, - {.addr = 0x00419a48, .prod = 0x00000242, .disable = 0x00000000}, - {.addr = 0x00419a50, .prod = 0x00000242, .disable = 0x00000000}, - {.addr = 0x00419a58, .prod = 0x00000242, .disable = 0x00000000}, - {.addr = 0x00419a60, .prod = 0x00000202, .disable = 0x00000000}, - {.addr = 0x00419a68, .prod = 0x00000202, .disable = 0x00000000}, - {.addr = 0x00419a78, .prod = 0x00000242, .disable = 0x00000000}, - {.addr = 0x00419a80, .prod = 0x00000242, .disable = 0x00000000}, - {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, - {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, -}; - -/* blcg ltc */ -static const struct gating_desc gv11b_blcg_ltc[] = { - {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, -}; - -/* blcg pwr_csb */ -static const struct gating_desc gv11b_blcg_pwr_csb[] = { - {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, -}; - -/* blcg pmu */ -static const struct gating_desc gv11b_blcg_pmu[] = { - {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, -}; - -/* blcg Xbar */ -static const struct gating_desc gv11b_blcg_xbar[] = { - {.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000}, - {.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000}, - {.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000}, - {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, -}; - -/* pg gr */ -static const struct gating_desc gv11b_pg_gr[] = { -}; - -/* inline functions */ -void gv11b_slcg_bus_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv11b_slcg_bus) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv11b_slcg_bus[i].addr, - gv11b_slcg_bus[i].prod); - else - gk20a_writel(g, gv11b_slcg_bus[i].addr, - gv11b_slcg_bus[i].disable); - } -} - -void gv11b_slcg_ce2_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv11b_slcg_ce2) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv11b_slcg_ce2[i].addr, - gv11b_slcg_ce2[i].prod); - else - gk20a_writel(g, gv11b_slcg_ce2[i].addr, - gv11b_slcg_ce2[i].disable); - } -} - -void gv11b_slcg_chiplet_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv11b_slcg_chiplet) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv11b_slcg_chiplet[i].addr, - gv11b_slcg_chiplet[i].prod); - else - gk20a_writel(g, gv11b_slcg_chiplet[i].addr, - gv11b_slcg_chiplet[i].disable); - } -} - -void gv11b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, - bool prod) -{ -} - -void gv11b_slcg_fb_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv11b_slcg_fb) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv11b_slcg_fb[i].addr, - gv11b_slcg_fb[i].prod); - else - gk20a_writel(g, gv11b_slcg_fb[i].addr, - gv11b_slcg_fb[i].disable); - } -} - -void gv11b_slcg_fifo_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv11b_slcg_fifo) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv11b_slcg_fifo[i].addr, - gv11b_slcg_fifo[i].prod); - else - gk20a_writel(g, gv11b_slcg_fifo[i].addr, - gv11b_slcg_fifo[i].disable); - } -} - -void gr_gv11b_slcg_gr_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv11b_slcg_gr) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv11b_slcg_gr[i].addr, - gv11b_slcg_gr[i].prod); - else - gk20a_writel(g, gv11b_slcg_gr[i].addr, - gv11b_slcg_gr[i].disable); - } -} - -void ltc_gv11b_slcg_ltc_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv11b_slcg_ltc) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv11b_slcg_ltc[i].addr, - gv11b_slcg_ltc[i].prod); - else - gk20a_writel(g, gv11b_slcg_ltc[i].addr, - gv11b_slcg_ltc[i].disable); - } -} - -void gv11b_slcg_perf_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv11b_slcg_perf) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv11b_slcg_perf[i].addr, - gv11b_slcg_perf[i].prod); - else - gk20a_writel(g, gv11b_slcg_perf[i].addr, - gv11b_slcg_perf[i].disable); - } -} - -void gv11b_slcg_priring_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv11b_slcg_priring) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv11b_slcg_priring[i].addr, - gv11b_slcg_priring[i].prod); - else - gk20a_writel(g, gv11b_slcg_priring[i].addr, - gv11b_slcg_priring[i].disable); - } -} - -void gv11b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv11b_slcg_pwr_csb) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv11b_slcg_pwr_csb[i].addr, - gv11b_slcg_pwr_csb[i].prod); - else - gk20a_writel(g, gv11b_slcg_pwr_csb[i].addr, - gv11b_slcg_pwr_csb[i].disable); - } -} - -void gv11b_slcg_pmu_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv11b_slcg_pmu) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv11b_slcg_pmu[i].addr, - gv11b_slcg_pmu[i].prod); - else - gk20a_writel(g, gv11b_slcg_pmu[i].addr, - gv11b_slcg_pmu[i].disable); - } -} - -void gv11b_slcg_therm_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv11b_slcg_therm) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv11b_slcg_therm[i].addr, - gv11b_slcg_therm[i].prod); - else - gk20a_writel(g, gv11b_slcg_therm[i].addr, - gv11b_slcg_therm[i].disable); - } -} - -void gv11b_slcg_xbar_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv11b_slcg_xbar) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv11b_slcg_xbar[i].addr, - gv11b_slcg_xbar[i].prod); - else - gk20a_writel(g, gv11b_slcg_xbar[i].addr, - gv11b_slcg_xbar[i].disable); - } -} - -void gv11b_blcg_bus_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv11b_blcg_bus) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv11b_blcg_bus[i].addr, - gv11b_blcg_bus[i].prod); - else - gk20a_writel(g, gv11b_blcg_bus[i].addr, - gv11b_blcg_bus[i].disable); - } -} - -void gv11b_blcg_ce_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv11b_blcg_ce) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv11b_blcg_ce[i].addr, - gv11b_blcg_ce[i].prod); - else - gk20a_writel(g, gv11b_blcg_ce[i].addr, - gv11b_blcg_ce[i].disable); - } -} - -void gv11b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv11b_blcg_ctxsw_prog) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv11b_blcg_ctxsw_prog[i].addr, - gv11b_blcg_ctxsw_prog[i].prod); - else - gk20a_writel(g, gv11b_blcg_ctxsw_prog[i].addr, - gv11b_blcg_ctxsw_prog[i].disable); - } -} - -void gv11b_blcg_fb_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv11b_blcg_fb) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv11b_blcg_fb[i].addr, - gv11b_blcg_fb[i].prod); - else - gk20a_writel(g, gv11b_blcg_fb[i].addr, - gv11b_blcg_fb[i].disable); - } -} - -void gv11b_blcg_fifo_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv11b_blcg_fifo) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv11b_blcg_fifo[i].addr, - gv11b_blcg_fifo[i].prod); - else - gk20a_writel(g, gv11b_blcg_fifo[i].addr, - gv11b_blcg_fifo[i].disable); - } -} - -void gv11b_blcg_gr_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv11b_blcg_gr) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv11b_blcg_gr[i].addr, - gv11b_blcg_gr[i].prod); - else - gk20a_writel(g, gv11b_blcg_gr[i].addr, - gv11b_blcg_gr[i].disable); - } -} - -void gv11b_blcg_ltc_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv11b_blcg_ltc) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv11b_blcg_ltc[i].addr, - gv11b_blcg_ltc[i].prod); - else - gk20a_writel(g, gv11b_blcg_ltc[i].addr, - gv11b_blcg_ltc[i].disable); - } -} - -void gv11b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv11b_blcg_pwr_csb) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv11b_blcg_pwr_csb[i].addr, - gv11b_blcg_pwr_csb[i].prod); - else - gk20a_writel(g, gv11b_blcg_pwr_csb[i].addr, - gv11b_blcg_pwr_csb[i].disable); - } -} - -void gv11b_blcg_pmu_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv11b_blcg_pmu) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv11b_blcg_pmu[i].addr, - gv11b_blcg_pmu[i].prod); - else - gk20a_writel(g, gv11b_blcg_pmu[i].addr, - gv11b_blcg_pmu[i].disable); - } -} - -void gv11b_blcg_xbar_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv11b_blcg_xbar) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv11b_blcg_xbar[i].addr, - gv11b_blcg_xbar[i].prod); - else - gk20a_writel(g, gv11b_blcg_xbar[i].addr, - gv11b_blcg_xbar[i].disable); - } -} - -void gr_gv11b_pg_gr_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gv11b_pg_gr) / sizeof(struct gating_desc); - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) - return; - - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gv11b_pg_gr[i].addr, - gv11b_pg_gr[i].prod); - else - gk20a_writel(g, gv11b_pg_gr[i].addr, - gv11b_pg_gr[i].disable); - } -} - -#endif /* __gv11b_gating_reglist_h__ */ diff --git a/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.h b/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.h deleted file mode 100644 index 233189e0..00000000 --- a/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA Corporation. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "gk20a/gk20a.h" - -void gv11b_slcg_bus_load_gating_prod(struct gk20a *g, - bool prod); - -void gv11b_slcg_ce2_load_gating_prod(struct gk20a *g, - bool prod); - -void gv11b_slcg_chiplet_load_gating_prod(struct gk20a *g, - bool prod); - -void gv11b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, - bool prod); - -void gv11b_slcg_fb_load_gating_prod(struct gk20a *g, - bool prod); - -void gv11b_slcg_fifo_load_gating_prod(struct gk20a *g, - bool prod); - -void gr_gv11b_slcg_gr_load_gating_prod(struct gk20a *g, - bool prod); - -void ltc_gv11b_slcg_ltc_load_gating_prod(struct gk20a *g, - bool prod); - -void gv11b_slcg_perf_load_gating_prod(struct gk20a *g, - bool prod); - -void gv11b_slcg_priring_load_gating_prod(struct gk20a *g, - bool prod); - -void gv11b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, - bool prod); - -void gv11b_slcg_pmu_load_gating_prod(struct gk20a *g, - bool prod); - -void gv11b_slcg_therm_load_gating_prod(struct gk20a *g, - bool prod); - -void gv11b_slcg_xbar_load_gating_prod(struct gk20a *g, - bool prod); - -void gv11b_blcg_bus_load_gating_prod(struct gk20a *g, - bool prod); - -void gv11b_blcg_ce_load_gating_prod(struct gk20a *g, - bool prod); - -void gv11b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, - bool prod); - -void gv11b_blcg_fb_load_gating_prod(struct gk20a *g, - bool prod); - -void gv11b_blcg_fifo_load_gating_prod(struct gk20a *g, - bool prod); - -void gv11b_blcg_gr_load_gating_prod(struct gk20a *g, - bool prod); - -void gv11b_blcg_ltc_load_gating_prod(struct gk20a *g, - bool prod); - -void gv11b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, - bool prod); - -void gv11b_blcg_pmu_load_gating_prod(struct gk20a *g, - bool prod); - -void gv11b_blcg_xbar_load_gating_prod(struct gk20a *g, - bool prod); - -void gr_gv11b_pg_gr_load_gating_prod(struct gk20a *g, - bool prod); - diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index ff779075..be8ea76e 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -76,7 +76,7 @@ #include "acr_gv11b.h" #include "fb_gv11b.h" #include "fifo_gv11b.h" -#include "gv11b_gating_reglist.h" +#include "clock_gating/gv11b_gating_reglist.h" #include "regops_gv11b.h" #include "subctx_gv11b.h" #include "therm_gv11b.h" diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 7810ab42..43bf6766 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c @@ -50,7 +50,7 @@ #include "gp10b/gr_gp10b.h" #include "gp10b/gr_ctx_gp10b.h" #include "gp10b/fifo_gp10b.h" -#include "gp10b/gp10b_gating_reglist.h" +#include "clock_gating/gp10b_gating_reglist.h" #include "gp10b/regops_gp10b.h" #include "gp10b/therm_gp10b.h" #include "gp10b/priv_ring_gp10b.h" diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 72db457b..b7bb23a7 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -75,7 +75,7 @@ #include #include #include -#include +#include #include #include -- cgit v1.2.2