From c965d7a54a347dc71191561ea5cd1a389ee8b091 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Thu, 5 Feb 2015 17:38:49 -0800 Subject: gpu: nvgpu: gp10b: setup mm hw init Add support for gp10b specific mm hw init. Bug 1587825 Change-Id: Iaccf1bf73468cfdd1842a001ab5e682ac06f1950 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/681787 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 00e41fa7..293eb999 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -25,6 +25,39 @@ u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g) return 36; } +static int gp10b_init_mm_setup_hw(struct gk20a *g) +{ + struct mm_gk20a *mm = &g->mm; + struct inst_desc *inst_block = &mm->bar1.inst_block; + phys_addr_t inst_pa = inst_block->cpu_pa; + int err = 0; + + gk20a_dbg_fn(""); + + g->ops.fb.set_mmu_page_size(g); + + inst_pa = (u32)(inst_pa >> bar1_instance_block_shift_gk20a()); + gk20a_dbg_info("bar1 inst block ptr: 0x%08x", (u32)inst_pa); + + gk20a_writel(g, bus_bar1_block_r(), + bus_bar1_block_target_vid_mem_f() | + bus_bar1_block_mode_virtual_f() | + bus_bar1_block_ptr_f(inst_pa)); + + if (g->ops.mm.init_bar2_mm_hw_setup) { + err = g->ops.mm.init_bar2_mm_hw_setup(g); + if (err) + return err; + } + + if (gk20a_mm_fb_flush(g) || gk20a_mm_fb_flush(g)) + return -EBUSY; + + gk20a_dbg_fn("done"); + return err; + +} + static int gb10b_init_bar2_vm(struct gk20a *g) { int err; @@ -79,6 +112,7 @@ void gp10b_init_mm(struct gpu_ops *gops) { gm20b_init_mm(gops); gops->mm.get_physical_addr_bits = gk20a_mm_get_physical_addr_bits; + gops->mm.init_mm_setup_hw = gp10b_init_mm_setup_hw; gops->mm.init_bar2_vm = gb10b_init_bar2_vm; gops->mm.init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup; } -- cgit v1.2.2