From bf82cd220a1ea4f8e327bc9bae51e36669c43778 Mon Sep 17 00:00:00 2001 From: Supriya Date: Mon, 21 Mar 2016 17:39:48 +0530 Subject: gpu: nvgpu: Add Fuse prints on PMU Halt -Print fuse values in case of PMU halt error -and mailbox reads 0xDEADDEAD Bug 1737044 Change-Id: I59f5fcf4a69bdd2a2eea81a69dd99bb9c4c21e1d Signed-off-by: Supriya Reviewed-on: http://git-master/r/1113464 (cherry picked from commit d0320eed72c5070c4fcc7564c02fa38599984751) Reviewed-on: http://git-master/r/1120429 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gk20a/gk20a.h | 1 + drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 6 ++++++ drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 5 +++++ drivers/gpu/nvgpu/gm20b/hw_fuse_gm20b.h | 10 +++++++++- drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 14 ++++++++++++++ 5 files changed, 35 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index ee78c6e2..273eeaf4 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -456,6 +456,7 @@ struct gpu_ops { u8 grfeaturemask); int (*send_lrf_tex_ltc_dram_overide_en_dis_cmd) (struct gk20a *g, u32 mask); + void (*dump_secure_fuses)(struct gk20a *g); u32 lspmuwprinitdone; u32 lsfloadedfalconid; bool fecsbootstrapdone; diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 60c87979..4edfe90c 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c @@ -2772,6 +2772,7 @@ void gk20a_init_pmu_ops(struct gpu_ops *gops) gops->pmu.pmu_elpg_statistics = gk20a_pmu_elpg_statistics; gops->pmu.pmu_pg_grinit_param = NULL; gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; + gops->pmu.dump_secure_fuses = NULL; } int gk20a_init_pmu_support(struct gk20a *g) @@ -3730,6 +3731,11 @@ void gk20a_pmu_isr(struct gk20a *g) gk20a_err(dev_from_gk20a(g), "pmu halt intr not implemented"); pmu_dump_falcon_stats(pmu); + if (gk20a_readl(g, pwr_pmu_mailbox_r + (PMU_MODE_MISMATCH_STATUS_MAILBOX_R)) == + PMU_MODE_MISMATCH_STATUS_VAL) + if (g->ops.pmu.dump_secure_fuses) + g->ops.pmu.dump_secure_fuses(g); } if (intr & pwr_falcon_irqstat_exterr_true_f()) { gk20a_err(dev_from_gk20a(g), diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 54d01947..c533ba8d 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h @@ -60,6 +60,11 @@ #define APP_VERSION_1 17997577 #define APP_VERSION_0 16856675 +/*Fuse defines*/ +#define FUSE_GCPLEX_CONFIG_FUSE_0 0x2C8 +#define PMU_MODE_MISMATCH_STATUS_MAILBOX_R 6 +#define PMU_MODE_MISMATCH_STATUS_VAL 0xDEADDEAD + enum pmu_perfmon_cmd_start_fields { COUNTER_ALLOC diff --git a/drivers/gpu/nvgpu/gm20b/hw_fuse_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_fuse_gm20b.h index a36709e3..62f68378 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_fuse_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_fuse_gm20b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -126,4 +126,12 @@ static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) { return (r >> (0 + i*0)) & 0x1; } +static inline u32 fuse_opt_sec_debug_en_r(void) +{ + return 0x00021218; +} +static inline u32 fuse_opt_priv_sec_en_r(void) +{ + return 0x00021434; +} #endif diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index ce3da2b6..34d1c30c 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c @@ -14,12 +14,14 @@ */ #include /* for udelay */ +#include #include "gk20a/gk20a.h" #include "gk20a/pmu_gk20a.h" #include "acr_gm20b.h" #include "pmu_gm20b.h" #include "hw_gr_gm20b.h" #include "hw_pwr_gm20b.h" +#include "hw_fuse_gm20b.h" /*! * Structure/object which single register write need to be done during PG init @@ -289,6 +291,17 @@ static void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr) gk20a_writel(g, pwr_falcon_dmatrfbase_r(), addr); } +/*Dump Security related fuses*/ +static void pmu_dump_security_fuses_gm20b(struct gk20a *g) +{ + gk20a_err(dev_from_gk20a(g), "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x", + gk20a_readl(g, fuse_opt_sec_debug_en_r())); + gk20a_err(dev_from_gk20a(g), "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", + gk20a_readl(g, fuse_opt_priv_sec_en_r())); + gk20a_err(dev_from_gk20a(g), "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", + tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0)); +} + void gm20b_init_pmu_ops(struct gpu_ops *gops) { if (gops->privsecurity) { @@ -309,4 +322,5 @@ void gm20b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.pmu_elpg_statistics = gk20a_pmu_elpg_statistics; gops->pmu.pmu_pg_grinit_param = NULL; gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; + gops->pmu.dump_secure_fuses = pmu_dump_security_fuses_gm20b; } -- cgit v1.2.2