From b69020bff5dfa69cad926c9374cdbe9a62509ffd Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Wed, 15 Mar 2017 16:42:12 -0700 Subject: gpu: nvgpu: Rename gk20a_mem_* functions Rename the functions used for mem_desc access to nvgpu_mem_*. JIRA NVGPU-12 Change-Id: Ibfdc1112d43f0a125e4487c250e3f977ffd2cd75 Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1323325 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/boardobj/boardobjgrp.c | 6 +- drivers/gpu/nvgpu/common/linux/mem_desc.c | 28 ++-- drivers/gpu/nvgpu/gk20a/bus_gk20a.c | 2 +- drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 8 +- drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c | 54 ++++---- drivers/gpu/nvgpu/gk20a/debug_gk20a.c | 2 +- drivers/gpu/nvgpu/gk20a/fb_gk20a.c | 2 +- drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c | 12 +- drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 58 ++++---- drivers/gpu/nvgpu/gk20a/gk20a.h | 2 +- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 190 +++++++++++++-------------- drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 57 ++++---- drivers/gpu/nvgpu/gk20a/mm_gk20a.h | 12 +- drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 8 +- drivers/gpu/nvgpu/gk20a/pramin_gk20a.c | 2 +- drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 14 +- drivers/gpu/nvgpu/gm20b/bus_gm20b.c | 2 +- drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 2 +- drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 14 +- drivers/gpu/nvgpu/gm20b/mm_gm20b.c | 4 +- drivers/gpu/nvgpu/gp106/acr_gp106.c | 12 +- drivers/gpu/nvgpu/gp106/sec2_gp106.c | 4 +- drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | 40 +++--- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 44 +++---- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 22 ++-- drivers/gpu/nvgpu/include/nvgpu/mem_desc.h | 30 ++--- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c | 2 +- drivers/gpu/nvgpu/vgpu/mm_vgpu.c | 2 +- 28 files changed, 318 insertions(+), 317 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/boardobj/boardobjgrp.c b/drivers/gpu/nvgpu/boardobj/boardobjgrp.c index 43928ac1..d193861a 100644 --- a/drivers/gpu/nvgpu/boardobj/boardobjgrp.c +++ b/drivers/gpu/nvgpu/boardobj/boardobjgrp.c @@ -409,7 +409,7 @@ u32 boardobjgrp_pmuset_impl(struct gk20a *g, struct boardobjgrp *pboardobjgrp) gk20a_pmu_vidmem_surface_alloc(g, &pcmd->surf.vidmem_desc, pcmd->fbsize); } - gk20a_mem_wr_n(g, &pcmd->surf.vidmem_desc, 0, pcmd->buf, pcmd->fbsize); + nvgpu_mem_wr_n(g, &pcmd->surf.vidmem_desc, 0, pcmd->buf, pcmd->fbsize); /* Send the SET PMU CMD to the PMU */ status = boardobjgrp_pmucmdsend(g, pboardobjgrp, @@ -488,7 +488,7 @@ boardobjgrp_pmugetstatus_impl(struct gk20a *g, struct boardobjgrp *pboardobjgrp, goto boardobjgrp_pmugetstatus_exit; } - gk20a_mem_wr_n(g, &pcmd->surf.vidmem_desc, 0, pset->buf, pset->hdrsize); + nvgpu_mem_wr_n(g, &pcmd->surf.vidmem_desc, 0, pset->buf, pset->hdrsize); /* Send the GET_STATUS PMU CMD to the PMU */ status = boardobjgrp_pmucmdsend(g, pboardobjgrp, &pboardobjgrp->pmu.getstatus); @@ -499,7 +499,7 @@ boardobjgrp_pmugetstatus_impl(struct gk20a *g, struct boardobjgrp *pboardobjgrp, } /*copy the data back to sysmem buffer that belongs to command*/ - gk20a_mem_rd_n(g, &pcmd->surf.vidmem_desc, 0, pcmd->buf, pcmd->fbsize); + nvgpu_mem_rd_n(g, &pcmd->surf.vidmem_desc, 0, pcmd->buf, pcmd->fbsize); boardobjgrp_pmugetstatus_exit: return status; diff --git a/drivers/gpu/nvgpu/common/linux/mem_desc.c b/drivers/gpu/nvgpu/common/linux/mem_desc.c index b2ef122e..02c3d1a9 100644 --- a/drivers/gpu/nvgpu/common/linux/mem_desc.c +++ b/drivers/gpu/nvgpu/common/linux/mem_desc.c @@ -20,7 +20,7 @@ #include "gk20a/gk20a.h" #include "gk20a/mm_gk20a.h" -u32 __gk20a_aperture_mask(struct gk20a *g, enum gk20a_aperture aperture, +u32 __nvgpu_aperture_mask(struct gk20a *g, enum nvgpu_aperture aperture, u32 sysmem_mask, u32 vidmem_mask) { switch (aperture) { @@ -36,14 +36,14 @@ u32 __gk20a_aperture_mask(struct gk20a *g, enum gk20a_aperture aperture, return 0; } -u32 gk20a_aperture_mask(struct gk20a *g, struct mem_desc *mem, +u32 nvgpu_aperture_mask(struct gk20a *g, struct mem_desc *mem, u32 sysmem_mask, u32 vidmem_mask) { - return __gk20a_aperture_mask(g, mem->aperture, + return __nvgpu_aperture_mask(g, mem->aperture, sysmem_mask, vidmem_mask); } -int gk20a_mem_begin(struct gk20a *g, struct mem_desc *mem) +int nvgpu_mem_begin(struct gk20a *g, struct mem_desc *mem) { void *cpu_va; @@ -66,7 +66,7 @@ int gk20a_mem_begin(struct gk20a *g, struct mem_desc *mem) return 0; } -void gk20a_mem_end(struct gk20a *g, struct mem_desc *mem) +void nvgpu_mem_end(struct gk20a *g, struct mem_desc *mem) { if (mem->aperture != APERTURE_SYSMEM || g->mm.force_pramin) return; @@ -75,7 +75,7 @@ void gk20a_mem_end(struct gk20a *g, struct mem_desc *mem) mem->cpu_va = NULL; } -u32 gk20a_mem_rd32(struct gk20a *g, struct mem_desc *mem, u32 w) +u32 nvgpu_mem_rd32(struct gk20a *g, struct mem_desc *mem, u32 w) { u32 data = 0; @@ -103,13 +103,13 @@ u32 gk20a_mem_rd32(struct gk20a *g, struct mem_desc *mem, u32 w) return data; } -u32 gk20a_mem_rd(struct gk20a *g, struct mem_desc *mem, u32 offset) +u32 nvgpu_mem_rd(struct gk20a *g, struct mem_desc *mem, u32 offset) { WARN_ON(offset & 3); - return gk20a_mem_rd32(g, mem, offset / sizeof(u32)); + return nvgpu_mem_rd32(g, mem, offset / sizeof(u32)); } -void gk20a_mem_rd_n(struct gk20a *g, struct mem_desc *mem, +void nvgpu_mem_rd_n(struct gk20a *g, struct mem_desc *mem, u32 offset, void *dest, u32 size) { WARN_ON(offset & 3); @@ -135,7 +135,7 @@ void gk20a_mem_rd_n(struct gk20a *g, struct mem_desc *mem, } } -void gk20a_mem_wr32(struct gk20a *g, struct mem_desc *mem, u32 w, u32 data) +void nvgpu_mem_wr32(struct gk20a *g, struct mem_desc *mem, u32 w, u32 data) { if (mem->aperture == APERTURE_SYSMEM && !g->mm.force_pramin) { u32 *ptr = mem->cpu_va; @@ -158,13 +158,13 @@ void gk20a_mem_wr32(struct gk20a *g, struct mem_desc *mem, u32 w, u32 data) } } -void gk20a_mem_wr(struct gk20a *g, struct mem_desc *mem, u32 offset, u32 data) +void nvgpu_mem_wr(struct gk20a *g, struct mem_desc *mem, u32 offset, u32 data) { WARN_ON(offset & 3); - gk20a_mem_wr32(g, mem, offset / sizeof(u32), data); + nvgpu_mem_wr32(g, mem, offset / sizeof(u32), data); } -void gk20a_mem_wr_n(struct gk20a *g, struct mem_desc *mem, u32 offset, +void nvgpu_mem_wr_n(struct gk20a *g, struct mem_desc *mem, u32 offset, void *src, u32 size) { WARN_ON(offset & 3); @@ -192,7 +192,7 @@ void gk20a_mem_wr_n(struct gk20a *g, struct mem_desc *mem, u32 offset, } } -void gk20a_memset(struct gk20a *g, struct mem_desc *mem, u32 offset, +void nvgpu_memset(struct gk20a *g, struct mem_desc *mem, u32 offset, u32 c, u32 size) { WARN_ON(offset & 3); diff --git a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c index fda1f80e..d161a29c 100644 --- a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c @@ -138,7 +138,7 @@ static int gk20a_bus_bar1_bind(struct gk20a *g, struct mem_desc *bar1_inst) gk20a_dbg_info("bar1 inst block ptr: 0x%08x", ptr_v); gk20a_writel(g, bus_bar1_block_r(), - gk20a_aperture_mask(g, bar1_inst, + nvgpu_aperture_mask(g, bar1_inst, bus_bar1_block_target_sys_mem_ncoh_f(), bus_bar1_block_target_vid_mem_f()) | bus_bar1_block_mode_virtual_f() | diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index b7306369..e13a903f 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c @@ -2124,7 +2124,7 @@ static void gk20a_submit_append_priv_cmdbuf(struct channel_gk20a *c, pbdma_gp_entry1_length_f(cmd->size) }; - gk20a_mem_wr_n(g, gpfifo_mem, c->gpfifo.put * sizeof(x), + nvgpu_mem_wr_n(g, gpfifo_mem, c->gpfifo.put * sizeof(x), &x, sizeof(x)); if (cmd->mem->aperture == APERTURE_SYSMEM) @@ -2207,10 +2207,10 @@ static int gk20a_submit_append_gpfifo(struct channel_gk20a *c, int length1 = len - length0; void *src2 = (u8 *)cpu_src + length0; - gk20a_mem_wr_n(c->g, gpfifo_mem, start, cpu_src, length0); - gk20a_mem_wr_n(c->g, gpfifo_mem, 0, src2, length1); + nvgpu_mem_wr_n(c->g, gpfifo_mem, start, cpu_src, length0); + nvgpu_mem_wr_n(c->g, gpfifo_mem, 0, src2, length1); } else { - gk20a_mem_wr_n(c->g, gpfifo_mem, start, cpu_src, len); + nvgpu_mem_wr_n(c->g, gpfifo_mem, start, cpu_src, len); } diff --git a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c index 8baf60dd..d9dfb133 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c @@ -46,13 +46,13 @@ static void add_wait_cmd(struct gk20a *g, struct priv_cmd_entry *cmd, u32 off, { off = cmd->off + off; /* syncpoint_a */ - gk20a_mem_wr32(g, cmd->mem, off++, 0x2001001C); + nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001C); /* payload */ - gk20a_mem_wr32(g, cmd->mem, off++, thresh); + nvgpu_mem_wr32(g, cmd->mem, off++, thresh); /* syncpoint_b */ - gk20a_mem_wr32(g, cmd->mem, off++, 0x2001001D); + nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001D); /* syncpt_id, switch_en, wait */ - gk20a_mem_wr32(g, cmd->mem, off++, (id << 8) | 0x10); + nvgpu_mem_wr32(g, cmd->mem, off++, (id << 8) | 0x10); } static int gk20a_channel_syncpt_wait_syncpt(struct gk20a_channel_sync *s, @@ -151,7 +151,7 @@ static int gk20a_channel_syncpt_wait_fd(struct gk20a_channel_sync *s, int fd, if (nvhost_syncpt_is_expired_ext(sp->host1x_pdev, wait_id, wait_value)) { /* each wait_cmd is 4 u32s */ - gk20a_memset(c->g, wait_cmd->mem, + nvgpu_memset(c->g, wait_cmd->mem, (wait_cmd->off + i * 4) * sizeof(u32), 0, 4 * sizeof(u32)); } else @@ -212,22 +212,22 @@ static int __gk20a_channel_syncpt_incr(struct gk20a_channel_sync *s, if (wfi_cmd) { /* wfi */ - gk20a_mem_wr32(c->g, incr_cmd->mem, off++, 0x2001001E); + nvgpu_mem_wr32(c->g, incr_cmd->mem, off++, 0x2001001E); /* handle, ignored */ - gk20a_mem_wr32(c->g, incr_cmd->mem, off++, 0x00000000); + nvgpu_mem_wr32(c->g, incr_cmd->mem, off++, 0x00000000); } /* syncpoint_a */ - gk20a_mem_wr32(c->g, incr_cmd->mem, off++, 0x2001001C); + nvgpu_mem_wr32(c->g, incr_cmd->mem, off++, 0x2001001C); /* payload, ignored */ - gk20a_mem_wr32(c->g, incr_cmd->mem, off++, 0); + nvgpu_mem_wr32(c->g, incr_cmd->mem, off++, 0); /* syncpoint_b */ - gk20a_mem_wr32(c->g, incr_cmd->mem, off++, 0x2001001D); + nvgpu_mem_wr32(c->g, incr_cmd->mem, off++, 0x2001001D); /* syncpt_id, incr */ - gk20a_mem_wr32(c->g, incr_cmd->mem, off++, (sp->id << 8) | 0x1); + nvgpu_mem_wr32(c->g, incr_cmd->mem, off++, (sp->id << 8) | 0x1); /* syncpoint_b */ - gk20a_mem_wr32(c->g, incr_cmd->mem, off++, 0x2001001D); + nvgpu_mem_wr32(c->g, incr_cmd->mem, off++, 0x2001001D); /* syncpt_id, incr */ - gk20a_mem_wr32(c->g, incr_cmd->mem, off++, (sp->id << 8) | 0x1); + nvgpu_mem_wr32(c->g, incr_cmd->mem, off++, (sp->id << 8) | 0x1); WARN_ON(off - incr_cmd->off != incr_cmd_size); @@ -531,39 +531,39 @@ static void add_sema_cmd(struct gk20a *g, struct channel_gk20a *c, nvgpu_semaphore_incr(s); /* semaphore_a */ - gk20a_mem_wr32(g, cmd->mem, off++, 0x20010004); + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010004); /* offset_upper */ - gk20a_mem_wr32(g, cmd->mem, off++, (va >> 32) & 0xff); + nvgpu_mem_wr32(g, cmd->mem, off++, (va >> 32) & 0xff); /* semaphore_b */ - gk20a_mem_wr32(g, cmd->mem, off++, 0x20010005); + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010005); /* offset */ - gk20a_mem_wr32(g, cmd->mem, off++, va & 0xffffffff); + nvgpu_mem_wr32(g, cmd->mem, off++, va & 0xffffffff); if (acquire) { /* semaphore_c */ - gk20a_mem_wr32(g, cmd->mem, off++, 0x20010006); + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006); /* payload */ - gk20a_mem_wr32(g, cmd->mem, off++, + nvgpu_mem_wr32(g, cmd->mem, off++, nvgpu_semaphore_get_value(s)); /* semaphore_d */ - gk20a_mem_wr32(g, cmd->mem, off++, 0x20010007); + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007); /* operation: acq_geq, switch_en */ - gk20a_mem_wr32(g, cmd->mem, off++, 0x4 | (0x1 << 12)); + nvgpu_mem_wr32(g, cmd->mem, off++, 0x4 | (0x1 << 12)); } else { /* semaphore_c */ - gk20a_mem_wr32(g, cmd->mem, off++, 0x20010006); + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006); /* payload */ - gk20a_mem_wr32(g, cmd->mem, off++, + nvgpu_mem_wr32(g, cmd->mem, off++, nvgpu_semaphore_get_value(s)); /* semaphore_d */ - gk20a_mem_wr32(g, cmd->mem, off++, 0x20010007); + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007); /* operation: release, wfi */ - gk20a_mem_wr32(g, cmd->mem, off++, + nvgpu_mem_wr32(g, cmd->mem, off++, 0x2 | ((wfi ? 0x0 : 0x1) << 20)); /* non_stall_int */ - gk20a_mem_wr32(g, cmd->mem, off++, 0x20010008); + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010008); /* ignored */ - gk20a_mem_wr32(g, cmd->mem, off++, 0); + nvgpu_mem_wr32(g, cmd->mem, off++, 0); } if (acquire) diff --git a/drivers/gpu/nvgpu/gk20a/debug_gk20a.c b/drivers/gpu/nvgpu/gk20a/debug_gk20a.c index 7e7c9cb8..5724be72 100644 --- a/drivers/gpu/nvgpu/gk20a/debug_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/debug_gk20a.c @@ -87,7 +87,7 @@ static void gk20a_debug_dump_all_channel_status_ramfc(struct gk20a *g, ch_state[chid]->pid = ch->pid; ch_state[chid]->refs = atomic_read(&ch->ref_count); - gk20a_mem_rd_n(g, &ch->inst_block, 0, + nvgpu_mem_rd_n(g, &ch->inst_block, 0, &ch_state[chid]->inst_block[0], ram_in_alloc_size_v()); gk20a_channel_put(ch); diff --git a/drivers/gpu/nvgpu/gk20a/fb_gk20a.c b/drivers/gpu/nvgpu/gk20a/fb_gk20a.c index 44f0ac4c..2e0809ee 100644 --- a/drivers/gpu/nvgpu/gk20a/fb_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fb_gk20a.c @@ -135,7 +135,7 @@ void gk20a_fb_tlb_invalidate(struct gk20a *g, struct mem_desc *pdb) gk20a_writel(g, fb_mmu_invalidate_pdb_r(), fb_mmu_invalidate_pdb_addr_f(addr_lo) | - gk20a_aperture_mask(g, pdb, + nvgpu_aperture_mask(g, pdb, fb_mmu_invalidate_pdb_aperture_sys_mem_f(), fb_mmu_invalidate_pdb_aperture_vid_mem_f())); diff --git a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c index 4fa71797..b4e3bad1 100644 --- a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c @@ -636,11 +636,11 @@ static int gk20a_fecs_trace_bind_channel(struct gk20a *g, pa = gk20a_mm_inst_block_addr(g, &trace->trace_buf); if (!pa) return -ENOMEM; - aperture = gk20a_aperture_mask(g, &trace->trace_buf, + aperture = nvgpu_aperture_mask(g, &trace->trace_buf, ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f(), ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f()); - if (gk20a_mem_begin(g, mem)) + if (nvgpu_mem_begin(g, mem)) return -ENOMEM; lo = u64_lo32(pa); @@ -649,19 +649,19 @@ static int gk20a_fecs_trace_bind_channel(struct gk20a *g, gk20a_dbg(gpu_dbg_ctxsw, "addr_hi=%x addr_lo=%x count=%d", hi, lo, GK20A_FECS_TRACE_NUM_RECORDS); - gk20a_mem_wr(g, mem, + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(), lo); - gk20a_mem_wr(g, mem, + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(), ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(hi) | aperture); - gk20a_mem_wr(g, mem, + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_context_timestamp_buffer_control_o(), ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f( GK20A_FECS_TRACE_NUM_RECORDS)); - gk20a_mem_end(g, mem); + nvgpu_mem_end(g, mem); /* pid (process identifier) in user space, corresponds to tgid (thread * group id) in kernel space. diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index b2a6b1a0..b8b0c9b0 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -3141,7 +3141,7 @@ static int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id, if (count != 0) { gk20a_writel(g, fifo_runlist_base_r(), fifo_runlist_base_ptr_f(u64_lo32(runlist_iova >> 12)) | - gk20a_aperture_mask(g, &runlist->mem[new_buf], + nvgpu_aperture_mask(g, &runlist->mem[new_buf], fifo_runlist_base_target_sys_mem_ncoh_f(), fifo_runlist_base_target_vid_mem_f())); } @@ -3901,7 +3901,7 @@ static void gk20a_fifo_channel_bind(struct channel_gk20a *c) gk20a_writel(g, ccsr_channel_inst_r(c->hw_chid), ccsr_channel_inst_ptr_f(inst_ptr) | - gk20a_aperture_mask(g, &c->inst_block, + nvgpu_aperture_mask(g, &c->inst_block, ccsr_channel_inst_target_sys_mem_ncoh_f(), ccsr_channel_inst_target_vid_mem_f()) | ccsr_channel_inst_bind_true_f()); @@ -3943,14 +3943,14 @@ static int gk20a_fifo_commit_userd(struct channel_gk20a *c) gk20a_dbg_info("channel %d : set ramfc userd 0x%16llx", c->hw_chid, (u64)c->userd_iova); - gk20a_mem_wr32(g, &c->inst_block, + nvgpu_mem_wr32(g, &c->inst_block, ram_in_ramfc_w() + ram_fc_userd_w(), - gk20a_aperture_mask(g, &g->fifo.userd, + nvgpu_aperture_mask(g, &g->fifo.userd, pbdma_userd_target_sys_mem_ncoh_f(), pbdma_userd_target_vid_mem_f()) | pbdma_userd_addr_f(addr_lo)); - gk20a_mem_wr32(g, &c->inst_block, + nvgpu_mem_wr32(g, &c->inst_block, ram_in_ramfc_w() + ram_fc_userd_hi_w(), pbdma_userd_hi_addr_f(addr_hi)); @@ -3967,25 +3967,25 @@ int gk20a_fifo_setup_ramfc(struct channel_gk20a *c, gk20a_dbg_fn(""); - gk20a_memset(g, mem, 0, 0, ram_fc_size_val_v()); + nvgpu_memset(g, mem, 0, 0, ram_fc_size_val_v()); - gk20a_mem_wr32(g, mem, ram_fc_gp_base_w(), + nvgpu_mem_wr32(g, mem, ram_fc_gp_base_w(), pbdma_gp_base_offset_f( u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s()))); - gk20a_mem_wr32(g, mem, ram_fc_gp_base_hi_w(), + nvgpu_mem_wr32(g, mem, ram_fc_gp_base_hi_w(), pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) | pbdma_gp_base_hi_limit2_f(ilog2(gpfifo_entries))); - gk20a_mem_wr32(g, mem, ram_fc_signature_w(), + nvgpu_mem_wr32(g, mem, ram_fc_signature_w(), c->g->ops.fifo.get_pbdma_signature(c->g)); - gk20a_mem_wr32(g, mem, ram_fc_formats_w(), + nvgpu_mem_wr32(g, mem, ram_fc_formats_w(), pbdma_formats_gp_fermi0_f() | pbdma_formats_pb_fermi1_f() | pbdma_formats_mp_fermi0_f()); - gk20a_mem_wr32(g, mem, ram_fc_pb_header_w(), + nvgpu_mem_wr32(g, mem, ram_fc_pb_header_w(), pbdma_pb_header_priv_user_f() | pbdma_pb_header_method_zero_f() | pbdma_pb_header_subchannel_zero_f() | @@ -3993,27 +3993,27 @@ int gk20a_fifo_setup_ramfc(struct channel_gk20a *c, pbdma_pb_header_first_true_f() | pbdma_pb_header_type_inc_f()); - gk20a_mem_wr32(g, mem, ram_fc_subdevice_w(), + nvgpu_mem_wr32(g, mem, ram_fc_subdevice_w(), pbdma_subdevice_id_f(1) | pbdma_subdevice_status_active_f() | pbdma_subdevice_channel_dma_enable_f()); - gk20a_mem_wr32(g, mem, ram_fc_target_w(), pbdma_target_engine_sw_f()); + nvgpu_mem_wr32(g, mem, ram_fc_target_w(), pbdma_target_engine_sw_f()); - gk20a_mem_wr32(g, mem, ram_fc_acquire_w(), + nvgpu_mem_wr32(g, mem, ram_fc_acquire_w(), g->ops.fifo.pbdma_acquire_val(timeout)); - gk20a_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(), + nvgpu_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(), fifo_runlist_timeslice_timeout_128_f() | fifo_runlist_timeslice_timescale_3_f() | fifo_runlist_timeslice_enable_true_f()); - gk20a_mem_wr32(g, mem, ram_fc_pb_timeslice_w(), + nvgpu_mem_wr32(g, mem, ram_fc_pb_timeslice_w(), fifo_pb_timeslice_timeout_16_f() | fifo_pb_timeslice_timescale_0_f() | fifo_pb_timeslice_enable_true_f()); - gk20a_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid)); + nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid)); if (c->is_privileged_channel) gk20a_fifo_setup_ramfc_for_privileged_channel(c); @@ -4035,7 +4035,7 @@ static int channel_gk20a_set_schedule_params(struct channel_gk20a *c) WARN_ON(c->g->ops.fifo.preempt_channel(c->g, c->hw_chid)); /* set new timeslice */ - gk20a_mem_wr32(c->g, &c->inst_block, ram_fc_runlist_timeslice_w(), + nvgpu_mem_wr32(c->g, &c->inst_block, ram_fc_runlist_timeslice_w(), value | (shift << 12) | fifo_runlist_timeslice_enable_true_f()); @@ -4102,7 +4102,7 @@ void gk20a_fifo_setup_ramfc_for_privileged_channel(struct channel_gk20a *c) gk20a_dbg_info("channel %d : set ramfc privileged_channel", c->hw_chid); /* Enable HCE priv mode for phys mode transfer */ - gk20a_mem_wr32(g, mem, ram_fc_hce_ctrl_w(), + nvgpu_mem_wr32(g, mem, ram_fc_hce_ctrl_w(), pbdma_hce_ctrl_hce_priv_mode_yes_f()); } @@ -4114,16 +4114,16 @@ int gk20a_fifo_setup_userd(struct channel_gk20a *c) gk20a_dbg_fn(""); - gk20a_mem_wr32(g, mem, offset + ram_userd_put_w(), 0); - gk20a_mem_wr32(g, mem, offset + ram_userd_get_w(), 0); - gk20a_mem_wr32(g, mem, offset + ram_userd_ref_w(), 0); - gk20a_mem_wr32(g, mem, offset + ram_userd_put_hi_w(), 0); - gk20a_mem_wr32(g, mem, offset + ram_userd_ref_threshold_w(), 0); - gk20a_mem_wr32(g, mem, offset + ram_userd_gp_top_level_get_w(), 0); - gk20a_mem_wr32(g, mem, offset + ram_userd_gp_top_level_get_hi_w(), 0); - gk20a_mem_wr32(g, mem, offset + ram_userd_get_hi_w(), 0); - gk20a_mem_wr32(g, mem, offset + ram_userd_gp_get_w(), 0); - gk20a_mem_wr32(g, mem, offset + ram_userd_gp_put_w(), 0); + nvgpu_mem_wr32(g, mem, offset + ram_userd_put_w(), 0); + nvgpu_mem_wr32(g, mem, offset + ram_userd_get_w(), 0); + nvgpu_mem_wr32(g, mem, offset + ram_userd_ref_w(), 0); + nvgpu_mem_wr32(g, mem, offset + ram_userd_put_hi_w(), 0); + nvgpu_mem_wr32(g, mem, offset + ram_userd_ref_threshold_w(), 0); + nvgpu_mem_wr32(g, mem, offset + ram_userd_gp_top_level_get_w(), 0); + nvgpu_mem_wr32(g, mem, offset + ram_userd_gp_top_level_get_hi_w(), 0); + nvgpu_mem_wr32(g, mem, offset + ram_userd_get_hi_w(), 0); + nvgpu_mem_wr32(g, mem, offset + ram_userd_gp_get_w(), 0); + nvgpu_mem_wr32(g, mem, offset + ram_userd_gp_put_w(), 0); return 0; } diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 2a9f8a06..db7b3c5d 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -617,7 +617,7 @@ struct gpu_ops { bool sparse, bool priv, struct vm_gk20a_mapping_batch *batch, - enum gk20a_aperture aperture); + enum nvgpu_aperture aperture); void (*gmmu_unmap)(struct vm_gk20a *vm, u64 vaddr, u64 size, diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 3e9a388b..360b8c97 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -110,13 +110,13 @@ int gr_gk20a_get_ctx_id(struct gk20a *g, Flush and invalidate before cpu update. */ g->ops.mm.l2_flush(g, true); - if (gk20a_mem_begin(g, &ch_ctx->gr_ctx->mem)) + if (nvgpu_mem_begin(g, &ch_ctx->gr_ctx->mem)) return -ENOMEM; - *ctx_id = gk20a_mem_rd(g, &ch_ctx->gr_ctx->mem, + *ctx_id = nvgpu_mem_rd(g, &ch_ctx->gr_ctx->mem, ctxsw_prog_main_image_context_id_o()); - gk20a_mem_end(g, &ch_ctx->gr_ctx->mem); + nvgpu_mem_end(g, &ch_ctx->gr_ctx->mem); return 0; } @@ -649,11 +649,11 @@ int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va) addr_lo = u64_lo32(gpu_va) >> 12; addr_hi = u64_hi32(gpu_va); - gk20a_mem_wr32(c->g, &c->inst_block, ram_in_gr_wfi_target_w(), + nvgpu_mem_wr32(c->g, &c->inst_block, ram_in_gr_wfi_target_w(), ram_in_gr_cs_wfi_f() | ram_in_gr_wfi_mode_virtual_f() | ram_in_gr_wfi_ptr_lo_f(addr_lo)); - gk20a_mem_wr32(c->g, &c->inst_block, ram_in_gr_wfi_ptr_hi_w(), + nvgpu_mem_wr32(c->g, &c->inst_block, ram_in_gr_wfi_ptr_hi_w(), ram_in_gr_wfi_ptr_hi_f(addr_hi)); return 0; @@ -670,16 +670,16 @@ int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va) int gr_gk20a_ctx_patch_write_begin(struct gk20a *g, struct channel_ctx_gk20a *ch_ctx) { - return gk20a_mem_begin(g, &ch_ctx->patch_ctx.mem); + return nvgpu_mem_begin(g, &ch_ctx->patch_ctx.mem); } void gr_gk20a_ctx_patch_write_end(struct gk20a *g, struct channel_ctx_gk20a *ch_ctx) { - gk20a_mem_end(g, &ch_ctx->patch_ctx.mem); + nvgpu_mem_end(g, &ch_ctx->patch_ctx.mem); /* Write context count to context image if it is mapped */ if (ch_ctx->gr_ctx->mem.cpu_va) { - gk20a_mem_wr(g, &ch_ctx->gr_ctx->mem, + nvgpu_mem_wr(g, &ch_ctx->gr_ctx->mem, ctxsw_prog_main_image_patch_count_o(), ch_ctx->patch_ctx.data_count); } @@ -691,8 +691,8 @@ void gr_gk20a_ctx_patch_write(struct gk20a *g, { if (patch) { u32 patch_slot = ch_ctx->patch_ctx.data_count * 2; - gk20a_mem_wr32(g, &ch_ctx->patch_ctx.mem, patch_slot, addr); - gk20a_mem_wr32(g, &ch_ctx->patch_ctx.mem, patch_slot + 1, data); + nvgpu_mem_wr32(g, &ch_ctx->patch_ctx.mem, patch_slot, addr); + nvgpu_mem_wr32(g, &ch_ctx->patch_ctx.mem, patch_slot + 1, data); ch_ctx->patch_ctx.data_count++; } else { gk20a_writel(g, addr, data); @@ -703,7 +703,7 @@ static u32 fecs_current_ctx_data(struct gk20a *g, struct mem_desc *inst_block) { u32 ptr = u64_lo32(gk20a_mm_inst_block_addr(g, inst_block) >> ram_in_base_shift_v()); - u32 aperture = gk20a_aperture_mask(g, inst_block, + u32 aperture = nvgpu_aperture_mask(g, inst_block, gr_fecs_current_ctx_target_sys_mem_ncoh_f(), gr_fecs_current_ctx_target_vid_mem_f()); @@ -745,7 +745,7 @@ void gr_gk20a_write_zcull_ptr(struct gk20a *g, { u32 va = u64_lo32(gpu_va >> 8); - gk20a_mem_wr(g, mem, + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_zcull_ptr_o(), va); } @@ -754,7 +754,7 @@ void gr_gk20a_write_pm_ptr(struct gk20a *g, { u32 va = u64_lo32(gpu_va >> 8); - gk20a_mem_wr(g, mem, + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_pm_ptr_o(), va); } @@ -768,10 +768,10 @@ static int gr_gk20a_ctx_zcull_setup(struct gk20a *g, struct channel_gk20a *c) gk20a_dbg_fn(""); - if (gk20a_mem_begin(g, mem)) + if (nvgpu_mem_begin(g, mem)) return -ENOMEM; - if (gk20a_mem_begin(g, ctxheader)) { + if (nvgpu_mem_begin(g, ctxheader)) { ret = -ENOMEM; goto clean_up_mem; } @@ -795,7 +795,7 @@ static int gr_gk20a_ctx_zcull_setup(struct gk20a *g, struct channel_gk20a *c) goto clean_up; } - gk20a_mem_wr(g, mem, + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_zcull_o(), ch_ctx->zcull_ctx.ctx_sw_mode); @@ -808,9 +808,9 @@ static int gr_gk20a_ctx_zcull_setup(struct gk20a *g, struct channel_gk20a *c) gk20a_enable_channel_tsg(g, c); clean_up: - gk20a_mem_end(g, ctxheader); + nvgpu_mem_end(g, ctxheader); clean_up_mem: - gk20a_mem_end(g, mem); + nvgpu_mem_end(g, mem); return ret; } @@ -1756,10 +1756,10 @@ restore_fe_go_idle: goto restore_fe_go_idle; } - if (gk20a_mem_begin(g, gold_mem)) + if (nvgpu_mem_begin(g, gold_mem)) goto clean_up; - if (gk20a_mem_begin(g, gr_mem)) + if (nvgpu_mem_begin(g, gr_mem)) goto clean_up; ctx_header_words = roundup(ctx_header_bytes, sizeof(u32)); @@ -1768,26 +1768,26 @@ restore_fe_go_idle: g->ops.mm.l2_flush(g, true); for (i = 0; i < ctx_header_words; i++) { - data = gk20a_mem_rd32(g, gr_mem, i); - gk20a_mem_wr32(g, gold_mem, i, data); + data = nvgpu_mem_rd32(g, gr_mem, i); + nvgpu_mem_wr32(g, gold_mem, i, data); } - gk20a_mem_wr(g, gold_mem, ctxsw_prog_main_image_zcull_o(), + nvgpu_mem_wr(g, gold_mem, ctxsw_prog_main_image_zcull_o(), ctxsw_prog_main_image_zcull_mode_no_ctxsw_v()); - if (gk20a_mem_begin(g, ctxheader)) + if (nvgpu_mem_begin(g, ctxheader)) goto clean_up; if (ctxheader->gpu_va) g->ops.gr.write_zcull_ptr(g, ctxheader, 0); else g->ops.gr.write_zcull_ptr(g, gold_mem, 0); - gk20a_mem_end(g, ctxheader); + nvgpu_mem_end(g, ctxheader); g->ops.gr.commit_inst(c, ch_ctx->global_ctx_buffer_va[GOLDEN_CTX_VA]); gr_gk20a_fecs_ctx_image_save(c, gr_fecs_method_push_adr_wfi_golden_save_v()); - if (gk20a_mem_begin(g, ctxheader)) + if (nvgpu_mem_begin(g, ctxheader)) goto clean_up; if (gr->ctx_vars.local_golden_image == NULL) { @@ -1801,15 +1801,15 @@ restore_fe_go_idle: } if (ctxheader->gpu_va) - gk20a_mem_rd_n(g, ctxheader, 0, + nvgpu_mem_rd_n(g, ctxheader, 0, gr->ctx_vars.local_golden_image, gr->ctx_vars.golden_image_size); else - gk20a_mem_rd_n(g, gold_mem, 0, + nvgpu_mem_rd_n(g, gold_mem, 0, gr->ctx_vars.local_golden_image, gr->ctx_vars.golden_image_size); } - gk20a_mem_end(g, ctxheader); + nvgpu_mem_end(g, ctxheader); g->ops.gr.commit_inst(c, gr_mem->gpu_va); @@ -1824,8 +1824,8 @@ clean_up: else gk20a_dbg_fn("done"); - gk20a_mem_end(g, gold_mem); - gk20a_mem_end(g, gr_mem); + nvgpu_mem_end(g, gold_mem); + nvgpu_mem_end(g, gr_mem); nvgpu_mutex_release(&gr->ctx_mutex); return err; @@ -1865,22 +1865,22 @@ int gr_gk20a_update_smpc_ctxsw_mode(struct gk20a *g, Flush and invalidate before cpu update. */ g->ops.mm.l2_flush(g, true); - if (gk20a_mem_begin(g, mem)) { + if (nvgpu_mem_begin(g, mem)) { ret = -ENOMEM; goto out; } - data = gk20a_mem_rd(g, mem, + data = nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_pm_o()); data = data & ~ctxsw_prog_main_image_pm_smpc_mode_m(); data |= enable_smpc_ctxsw ? ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f() : ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(); - gk20a_mem_wr(g, mem, + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_pm_o(), data); - gk20a_mem_end(g, mem); + nvgpu_mem_end(g, mem); out: gk20a_enable_channel_tsg(g, c); @@ -1964,27 +1964,27 @@ int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g, } /* Now clear the buffer */ - if (gk20a_mem_begin(g, &pm_ctx->mem)) { + if (nvgpu_mem_begin(g, &pm_ctx->mem)) { ret = -ENOMEM; goto cleanup_pm_buf; } - gk20a_memset(g, &pm_ctx->mem, 0, 0, pm_ctx->mem.size); + nvgpu_memset(g, &pm_ctx->mem, 0, 0, pm_ctx->mem.size); - gk20a_mem_end(g, &pm_ctx->mem); + nvgpu_mem_end(g, &pm_ctx->mem); } - if (gk20a_mem_begin(g, gr_mem)) { + if (nvgpu_mem_begin(g, gr_mem)) { ret = -ENOMEM; goto cleanup_pm_buf; } - if (gk20a_mem_begin(g, ctxheader)) { + if (nvgpu_mem_begin(g, ctxheader)) { ret = -ENOMEM; goto clean_up_mem; } - data = gk20a_mem_rd(g, gr_mem, ctxsw_prog_main_image_pm_o()); + data = nvgpu_mem_rd(g, gr_mem, ctxsw_prog_main_image_pm_o()); data = data & ~ctxsw_prog_main_image_pm_mode_m(); if (enable_hwpm_ctxsw) { @@ -1998,22 +1998,22 @@ int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g, data |= pm_ctx->pm_mode; - gk20a_mem_wr(g, gr_mem, ctxsw_prog_main_image_pm_o(), data); + nvgpu_mem_wr(g, gr_mem, ctxsw_prog_main_image_pm_o(), data); if (ctxheader->gpu_va) g->ops.gr.write_pm_ptr(g, ctxheader, virt_addr); else g->ops.gr.write_pm_ptr(g, gr_mem, virt_addr); - gk20a_mem_end(g, ctxheader); - gk20a_mem_end(g, gr_mem); + nvgpu_mem_end(g, ctxheader); + nvgpu_mem_end(g, gr_mem); /* enable channel */ gk20a_enable_channel_tsg(g, c); return 0; clean_up_mem: - gk20a_mem_end(g, gr_mem); + nvgpu_mem_end(g, gr_mem); cleanup_pm_buf: gk20a_gmmu_unmap(c->vm, pm_ctx->mem.gpu_va, pm_ctx->mem.size, gk20a_mem_flag_none); @@ -2048,10 +2048,10 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g, Flush and invalidate before cpu update. */ g->ops.mm.l2_flush(g, true); - if (gk20a_mem_begin(g, mem)) + if (nvgpu_mem_begin(g, mem)) return -ENOMEM; - if (gk20a_mem_begin(g, ctxheader)) { + if (nvgpu_mem_begin(g, ctxheader)) { ret = -ENOMEM; goto clean_up_mem; } @@ -2060,12 +2060,12 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g, if (g->ops.gr.restore_context_header) g->ops.gr.restore_context_header(g, ctxheader); } else { - gk20a_mem_wr_n(g, mem, 0, + nvgpu_mem_wr_n(g, mem, 0, gr->ctx_vars.local_golden_image, gr->ctx_vars.golden_image_size); - gk20a_mem_wr(g, mem, + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_num_save_ops_o(), 0); - gk20a_mem_wr(g, mem, + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_num_restore_ops_o(), 0); } @@ -2083,29 +2083,29 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g, else data = ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(); - gk20a_mem_wr(g, mem, ctxsw_prog_main_image_priv_access_map_config_o(), + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_priv_access_map_config_o(), data); if (ctxheader->gpu_va) { - gk20a_mem_wr(g, ctxheader, + nvgpu_mem_wr(g, ctxheader, ctxsw_prog_main_image_priv_access_map_addr_lo_o(), virt_addr_lo); - gk20a_mem_wr(g, ctxheader, + nvgpu_mem_wr(g, ctxheader, ctxsw_prog_main_image_priv_access_map_addr_hi_o(), virt_addr_hi); } else { - gk20a_mem_wr(g, mem, + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_priv_access_map_addr_lo_o(), virt_addr_lo); - gk20a_mem_wr(g, mem, + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_priv_access_map_addr_hi_o(), virt_addr_hi); } /* disable verif features */ - v = gk20a_mem_rd(g, mem, ctxsw_prog_main_image_misc_options_o()); + v = nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_misc_options_o()); v = v & ~(ctxsw_prog_main_image_misc_options_verif_features_m()); v = v | ctxsw_prog_main_image_misc_options_verif_features_disabled_f(); - gk20a_mem_wr(g, mem, ctxsw_prog_main_image_misc_options_o(), v); + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_misc_options_o(), v); if (g->ops.gr.update_ctxsw_preemption_mode) g->ops.gr.update_ctxsw_preemption_mode(g, ch_ctx, mem); @@ -2116,26 +2116,26 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g, virt_addr_lo = u64_lo32(ch_ctx->patch_ctx.mem.gpu_va); virt_addr_hi = u64_hi32(ch_ctx->patch_ctx.mem.gpu_va); - gk20a_mem_wr(g, mem, ctxsw_prog_main_image_patch_count_o(), + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_patch_count_o(), ch_ctx->patch_ctx.data_count); - gk20a_mem_wr(g, mem, ctxsw_prog_main_image_patch_adr_lo_o(), + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_patch_adr_lo_o(), virt_addr_lo); - gk20a_mem_wr(g, mem, ctxsw_prog_main_image_patch_adr_hi_o(), + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_patch_adr_hi_o(), virt_addr_hi); if (ctxheader->gpu_va) { - gk20a_mem_wr(g, ctxheader, + nvgpu_mem_wr(g, ctxheader, ctxsw_prog_main_image_patch_count_o(), ch_ctx->patch_ctx.data_count); - gk20a_mem_wr(g, ctxheader, + nvgpu_mem_wr(g, ctxheader, ctxsw_prog_main_image_patch_adr_lo_o(), virt_addr_lo); - gk20a_mem_wr(g, ctxheader, + nvgpu_mem_wr(g, ctxheader, ctxsw_prog_main_image_patch_adr_hi_o(), virt_addr_hi); } - gk20a_mem_wr(g, mem, ctxsw_prog_main_image_zcull_o(), + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_zcull_o(), ch_ctx->zcull_ctx.ctx_sw_mode); if (ctxheader->gpu_va) @@ -2153,7 +2153,7 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g, if (ch_ctx->pm_ctx.mem.gpu_va == 0) { gk20a_err(dev_from_gk20a(g), "context switched pm with no pm buffer!"); - gk20a_mem_end(g, mem); + nvgpu_mem_end(g, mem); return -EFAULT; } @@ -2161,11 +2161,11 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g, } else virt_addr = 0; - data = gk20a_mem_rd(g, mem, ctxsw_prog_main_image_pm_o()); + data = nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_pm_o()); data = data & ~ctxsw_prog_main_image_pm_mode_m(); data |= ch_ctx->pm_ctx.pm_mode; - gk20a_mem_wr(g, mem, ctxsw_prog_main_image_pm_o(), data); + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_pm_o(), data); if (ctxheader->gpu_va) g->ops.gr.write_pm_ptr(g, ctxheader, virt_addr); @@ -2173,9 +2173,9 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g, g->ops.gr.write_pm_ptr(g, mem, virt_addr); - gk20a_mem_end(g, ctxheader); + nvgpu_mem_end(g, ctxheader); clean_up_mem: - gk20a_mem_end(g, mem); + nvgpu_mem_end(g, mem); return ret; } @@ -2256,11 +2256,11 @@ static int gr_gk20a_copy_ctxsw_ucode_segments( { unsigned int i; - gk20a_mem_wr_n(g, dst, segments->boot.offset, bootimage, + nvgpu_mem_wr_n(g, dst, segments->boot.offset, bootimage, segments->boot.size); - gk20a_mem_wr_n(g, dst, segments->code.offset, code, + nvgpu_mem_wr_n(g, dst, segments->code.offset, code, segments->code.size); - gk20a_mem_wr_n(g, dst, segments->data.offset, data, + nvgpu_mem_wr_n(g, dst, segments->data.offset, data, segments->data.size); /* compute a "checksum" for the boot binary to detect its version */ @@ -2382,14 +2382,14 @@ void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g) inst_ptr = gk20a_mm_inst_block_addr(g, &ucode_info->inst_blk_desc); gk20a_writel(g, gr_fecs_new_ctx_r(), gr_fecs_new_ctx_ptr_f(inst_ptr >> 12) | - gk20a_aperture_mask(g, &ucode_info->inst_blk_desc, + nvgpu_aperture_mask(g, &ucode_info->inst_blk_desc, gr_fecs_new_ctx_target_sys_mem_ncoh_f(), gr_fecs_new_ctx_target_vid_mem_f()) | gr_fecs_new_ctx_valid_m()); gk20a_writel(g, gr_fecs_arb_ctx_ptr_r(), gr_fecs_arb_ctx_ptr_ptr_f(inst_ptr >> 12) | - gk20a_aperture_mask(g, &ucode_info->inst_blk_desc, + nvgpu_aperture_mask(g, &ucode_info->inst_blk_desc, gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(), gr_fecs_arb_ctx_ptr_target_vid_mem_f())); @@ -4748,7 +4748,7 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) addr >>= fb_mmu_debug_wr_addr_alignment_v(); gk20a_writel(g, fb_mmu_debug_wr_r(), - gk20a_aperture_mask(g, &gr->mmu_wr_mem, + nvgpu_aperture_mask(g, &gr->mmu_wr_mem, fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(), fb_mmu_debug_wr_aperture_vid_mem_f()) | fb_mmu_debug_wr_vol_false_f() | @@ -4758,7 +4758,7 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) addr >>= fb_mmu_debug_rd_addr_alignment_v(); gk20a_writel(g, fb_mmu_debug_rd_r(), - gk20a_aperture_mask(g, &gr->mmu_rd_mem, + nvgpu_aperture_mask(g, &gr->mmu_rd_mem, fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(), fb_mmu_debug_rd_aperture_vid_mem_f()) | fb_mmu_debug_rd_vol_false_f() | @@ -5092,13 +5092,13 @@ static int gr_gk20a_init_access_map(struct gk20a *g) u32 *whitelist = NULL; unsigned int num_entries = 0; - if (gk20a_mem_begin(g, mem)) { + if (nvgpu_mem_begin(g, mem)) { gk20a_err(dev_from_gk20a(g), "failed to map priv access map memory"); return -ENOMEM; } - gk20a_memset(g, mem, 0, 0, PAGE_SIZE * nr_pages); + nvgpu_memset(g, mem, 0, 0, PAGE_SIZE * nr_pages); g->ops.gr.get_access_map(g, &whitelist, &num_entries); @@ -5109,14 +5109,14 @@ static int gr_gk20a_init_access_map(struct gk20a *g) map_shift = map_bit & 0x7; /* i.e. 0-7 */ gk20a_dbg_info("access map addr:0x%x byte:0x%x bit:%d", whitelist[w], map_byte, map_shift); - x = gk20a_mem_rd32(g, mem, map_byte / sizeof(u32)); + x = nvgpu_mem_rd32(g, mem, map_byte / sizeof(u32)); x |= 1 << ( (map_byte % sizeof(u32) * BITS_PER_BYTE) + map_shift); - gk20a_mem_wr32(g, mem, map_byte / sizeof(u32), x); + nvgpu_mem_wr32(g, mem, map_byte / sizeof(u32), x); } - gk20a_mem_end(g, mem); + nvgpu_mem_end(g, mem); return 0; } @@ -7160,7 +7160,7 @@ static int gr_gk20a_ctx_patch_smpc(struct gk20a *g, /* reset the patch count from previous runs,if ucode has already processed it */ - tmp = gk20a_mem_rd(g, mem, + tmp = nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_patch_count_o()); if (!tmp) @@ -7172,13 +7172,13 @@ static int gr_gk20a_ctx_patch_smpc(struct gk20a *g, vaddr_lo = u64_lo32(ch_ctx->patch_ctx.mem.gpu_va); vaddr_hi = u64_hi32(ch_ctx->patch_ctx.mem.gpu_va); - gk20a_mem_wr(g, mem, + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_patch_count_o(), ch_ctx->patch_ctx.data_count); - gk20a_mem_wr(g, mem, + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_patch_adr_lo_o(), vaddr_lo); - gk20a_mem_wr(g, mem, + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_patch_adr_hi_o(), vaddr_hi); @@ -8393,7 +8393,7 @@ int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, * gr_gk20a_apply_instmem_overrides, * recoded in-place instead. */ - if (gk20a_mem_begin(g, &ch_ctx->gr_ctx->mem)) { + if (nvgpu_mem_begin(g, &ch_ctx->gr_ctx->mem)) { err = -ENOMEM; goto cleanup; } @@ -8422,7 +8422,7 @@ int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, err = -EINVAL; goto cleanup; } - if (gk20a_mem_begin(g, &ch_ctx->pm_ctx.mem)) { + if (nvgpu_mem_begin(g, &ch_ctx->pm_ctx.mem)) { err = -ENOMEM; goto cleanup; } @@ -8445,20 +8445,20 @@ int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, (offsets[j] >= g->gr.ctx_vars.golden_image_size)) continue; if (pass == 0) { /* write pass */ - v = gk20a_mem_rd(g, current_mem, offsets[j]); + v = nvgpu_mem_rd(g, current_mem, offsets[j]); v &= ~ctx_ops[i].and_n_mask_lo; v |= ctx_ops[i].value_lo; - gk20a_mem_wr(g, current_mem, offsets[j], v); + nvgpu_mem_wr(g, current_mem, offsets[j], v); gk20a_dbg(gpu_dbg_gpu_dbg, "context wr: offset=0x%x v=0x%x", offsets[j], v); if (ctx_ops[i].op == REGOP(WRITE_64)) { - v = gk20a_mem_rd(g, current_mem, offsets[j] + 4); + v = nvgpu_mem_rd(g, current_mem, offsets[j] + 4); v &= ~ctx_ops[i].and_n_mask_hi; v |= ctx_ops[i].value_hi; - gk20a_mem_wr(g, current_mem, offsets[j] + 4, v); + nvgpu_mem_wr(g, current_mem, offsets[j] + 4, v); gk20a_dbg(gpu_dbg_gpu_dbg, "context wr: offset=0x%x v=0x%x", @@ -8472,14 +8472,14 @@ int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, } else { /* read pass */ ctx_ops[i].value_lo = - gk20a_mem_rd(g, current_mem, offsets[0]); + nvgpu_mem_rd(g, current_mem, offsets[0]); gk20a_dbg(gpu_dbg_gpu_dbg, "context rd: offset=0x%x v=0x%x", offsets[0], ctx_ops[i].value_lo); if (ctx_ops[i].op == REGOP(READ_64)) { ctx_ops[i].value_hi = - gk20a_mem_rd(g, current_mem, offsets[0] + 4); + nvgpu_mem_rd(g, current_mem, offsets[0] + 4); gk20a_dbg(gpu_dbg_gpu_dbg, "context rd: offset=0x%x v=0x%x", @@ -8507,9 +8507,9 @@ int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, if (ch_ctx->patch_ctx.mem.cpu_va) gr_gk20a_ctx_patch_write_end(g, ch_ctx); if (gr_ctx_ready) - gk20a_mem_end(g, &ch_ctx->gr_ctx->mem); + nvgpu_mem_end(g, &ch_ctx->gr_ctx->mem); if (pm_ctx_ready) - gk20a_mem_end(g, &ch_ctx->pm_ctx.mem); + nvgpu_mem_end(g, &ch_ctx->pm_ctx.mem); if (restart_gr_ctxsw) { int tmp_err = gr_gk20a_enable_ctxsw(g); diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index e78eb941..9c9fad1b 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include @@ -139,7 +140,7 @@ static int update_gmmu_ptes_locked(struct vm_gk20a *vm, bool umapped_pte, int rw_flag, bool sparse, bool priv, - enum gk20a_aperture aperture); + enum nvgpu_aperture aperture); static int __must_check gk20a_init_system_vm(struct mm_gk20a *mm); static int __must_check gk20a_init_bar1_vm(struct mm_gk20a *mm); static int __must_check gk20a_init_hwpm(struct mm_gk20a *mm); @@ -945,7 +946,7 @@ int map_gmmu_pages(struct gk20a *g, struct gk20a_mm_entry *entry) sg_phys(entry->mem.sgt->sgl), entry->mem.size); } else { - int err = gk20a_mem_begin(g, &entry->mem); + int err = nvgpu_mem_begin(g, &entry->mem); if (err) return err; @@ -971,7 +972,7 @@ void unmap_gmmu_pages(struct gk20a *g, struct gk20a_mm_entry *entry) sg_phys(entry->mem.sgt->sgl), entry->mem.size); } else { - gk20a_mem_end(g, &entry->mem); + nvgpu_mem_end(g, &entry->mem); } } @@ -1510,7 +1511,7 @@ u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm, bool sparse, bool priv, struct vm_gk20a_mapping_batch *batch, - enum gk20a_aperture aperture) + enum nvgpu_aperture aperture) { int err = 0; bool allocated = false; @@ -1543,7 +1544,7 @@ u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm, sgt ? lo32((u64)sg_phys(sgt->sgl)) : 0, vm->gmmu_page_sizes[pgsz_idx] >> 10, vm_aspace_id(vm), ctag_lines, ctag_offset, - kind_v, flags, gk20a_aperture_str(aperture)); + kind_v, flags, nvgpu_aperture_str(aperture)); err = update_gmmu_ptes_locked(vm, pgsz_idx, sgt, @@ -1634,7 +1635,7 @@ void gk20a_locked_gmmu_unmap(struct vm_gk20a *vm, } } -static enum gk20a_aperture gk20a_dmabuf_aperture(struct gk20a *g, +static enum nvgpu_aperture gk20a_dmabuf_aperture(struct gk20a *g, struct dma_buf *dmabuf) { struct gk20a *buf_owner = gk20a_vidmem_buf_owner(dmabuf); @@ -1723,7 +1724,7 @@ static u64 gk20a_vm_map_duplicate_locked(struct vm_gk20a *vm, vm_aspace_id(vm), mapped_buffer->ctag_lines, mapped_buffer->ctag_offset, mapped_buffer->flags, - gk20a_aperture_str(gk20a_dmabuf_aperture(g, dmabuf))); + nvgpu_aperture_str(gk20a_dmabuf_aperture(g, dmabuf))); if (sgt) *sgt = mapped_buffer->sgt; @@ -1941,11 +1942,11 @@ int gk20a_vidbuf_access_memory(struct gk20a *g, struct dma_buf *dmabuf, switch (cmd) { case NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY_CMD_READ: - gk20a_mem_rd_n(g, mem, offset, buffer, size); + nvgpu_mem_rd_n(g, mem, offset, buffer, size); break; case NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY_CMD_WRITE: - gk20a_mem_wr_n(g, mem, offset, buffer, size); + nvgpu_mem_wr_n(g, mem, offset, buffer, size); break; default: @@ -1959,7 +1960,7 @@ int gk20a_vidbuf_access_memory(struct gk20a *g, struct dma_buf *dmabuf, } static u64 gk20a_mm_get_align(struct gk20a *g, struct scatterlist *sgl, - enum gk20a_aperture aperture) + enum nvgpu_aperture aperture) { u64 align = 0, chunk_align = 0; u64 buf_addr; @@ -2030,7 +2031,7 @@ u64 gk20a_vm_map(struct vm_gk20a *vm, u32 ctag_map_win_ctagline = 0; struct vm_reserved_va_node *va_node = NULL; u32 ctag_offset; - enum gk20a_aperture aperture; + enum nvgpu_aperture aperture; if (user_mapped && vm->userspace_managed && !(flags & NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET)) { @@ -2462,7 +2463,7 @@ static u64 __gk20a_gmmu_map(struct vm_gk20a *vm, u32 flags, int rw_flag, bool priv, - enum gk20a_aperture aperture) + enum nvgpu_aperture aperture) { struct gk20a *g = gk20a_from_vm(vm); u64 vaddr; @@ -2496,7 +2497,7 @@ u64 gk20a_gmmu_map(struct vm_gk20a *vm, u32 flags, int rw_flag, bool priv, - enum gk20a_aperture aperture) + enum nvgpu_aperture aperture) { return __gk20a_gmmu_map(vm, sgt, 0, size, flags, rw_flag, priv, aperture); @@ -2512,7 +2513,7 @@ u64 gk20a_gmmu_fixed_map(struct vm_gk20a *vm, u32 flags, int rw_flag, bool priv, - enum gk20a_aperture aperture) + enum nvgpu_aperture aperture) { return __gk20a_gmmu_map(vm, sgt, addr, size, flags, rw_flag, priv, aperture); @@ -2851,7 +2852,7 @@ static void gk20a_gmmu_free_vid(struct gk20a *g, struct mem_desc *mem) schedule_work(&g->mm.vidmem.clear_mem_worker); } } else { - gk20a_memset(g, mem, 0, 0, mem->size); + nvgpu_memset(g, mem, 0, 0, mem->size); nvgpu_free(mem->allocator, (u64)get_vidmem_page_alloc(mem->sgt->sgl)); gk20a_free_sgtable(g, &mem->sgt); @@ -3170,7 +3171,7 @@ u64 gk20a_mm_iova_addr(struct gk20a *g, struct scatterlist *sgl, void gk20a_pde_wr32(struct gk20a *g, struct gk20a_mm_entry *entry, size_t w, size_t data) { - gk20a_mem_wr32(g, &entry->mem, entry->woffset + w, data); + nvgpu_mem_wr32(g, &entry->mem, entry->woffset + w, data); } u64 gk20a_pde_addr(struct gk20a *g, struct gk20a_mm_entry *entry) @@ -3191,7 +3192,7 @@ static inline u32 big_valid_pde0_bits(struct gk20a *g, { u64 pte_addr = gk20a_pde_addr(g, entry); u32 pde0_bits = - gk20a_aperture_mask(g, &entry->mem, + nvgpu_aperture_mask(g, &entry->mem, gmmu_pde_aperture_big_sys_mem_ncoh_f(), gmmu_pde_aperture_big_video_memory_f()) | gmmu_pde_address_big_sys_f( @@ -3205,7 +3206,7 @@ static inline u32 small_valid_pde1_bits(struct gk20a *g, { u64 pte_addr = gk20a_pde_addr(g, entry); u32 pde1_bits = - gk20a_aperture_mask(g, &entry->mem, + nvgpu_aperture_mask(g, &entry->mem, gmmu_pde_aperture_small_sys_mem_ncoh_f(), gmmu_pde_aperture_small_video_memory_f()) | gmmu_pde_vol_small_true_f() | /* tbd: why? */ @@ -3230,7 +3231,7 @@ static int update_gmmu_pde_locked(struct vm_gk20a *vm, u32 kind_v, u64 *ctag, bool cacheable, bool unammped_pte, int rw_flag, bool sparse, bool priv, - enum gk20a_aperture aperture) + enum nvgpu_aperture aperture) { struct gk20a *g = gk20a_from_vm(vm); bool small_valid, big_valid; @@ -3275,7 +3276,7 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm, u32 kind_v, u64 *ctag, bool cacheable, bool unmapped_pte, int rw_flag, bool sparse, bool priv, - enum gk20a_aperture aperture) + enum nvgpu_aperture aperture) { struct gk20a *g = gk20a_from_vm(vm); int ctag_shift = ilog2(g->ops.fb.compression_page_size(g)); @@ -3296,7 +3297,7 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm, if (priv) pte_w[0] |= gmmu_pte_privilege_true_f(); - pte_w[1] = __gk20a_aperture_mask(g, aperture, + pte_w[1] = __nvgpu_aperture_mask(g, aperture, gmmu_pte_aperture_sys_mem_ncoh_f(), gmmu_pte_aperture_video_memory_f()) | gmmu_pte_kind_f(kind_v) | @@ -3379,7 +3380,7 @@ static int update_gmmu_level_locked(struct vm_gk20a *vm, bool sparse, int lvl, bool priv, - enum gk20a_aperture aperture) + enum nvgpu_aperture aperture) { struct gk20a *g = gk20a_from_vm(vm); const struct gk20a_mmu_level *l = &vm->mmu_levels[lvl]; @@ -3477,7 +3478,7 @@ static int update_gmmu_ptes_locked(struct vm_gk20a *vm, int rw_flag, bool sparse, bool priv, - enum gk20a_aperture aperture) + enum nvgpu_aperture aperture) { struct gk20a *g = gk20a_from_vm(vm); int ctag_granularity = g->ops.fb.compression_page_size(g); @@ -4735,14 +4736,14 @@ void gk20a_mm_init_pdb(struct gk20a *g, struct mem_desc *inst_block, gk20a_dbg_info("pde pa=0x%llx", pdb_addr); - gk20a_mem_wr32(g, inst_block, ram_in_page_dir_base_lo_w(), - gk20a_aperture_mask(g, &vm->pdb.mem, + nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_lo_w(), + nvgpu_aperture_mask(g, &vm->pdb.mem, ram_in_page_dir_base_target_sys_mem_ncoh_f(), ram_in_page_dir_base_target_vid_mem_f()) | ram_in_page_dir_base_vol_true_f() | ram_in_page_dir_base_lo_f(pdb_addr_lo)); - gk20a_mem_wr32(g, inst_block, ram_in_page_dir_base_hi_w(), + nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_hi_w(), ram_in_page_dir_base_hi_f(pdb_addr_hi)); } @@ -4756,10 +4757,10 @@ void gk20a_init_inst_block(struct mem_desc *inst_block, struct vm_gk20a *vm, g->ops.mm.init_pdb(g, inst_block, vm); - gk20a_mem_wr32(g, inst_block, ram_in_adr_limit_lo_w(), + nvgpu_mem_wr32(g, inst_block, ram_in_adr_limit_lo_w(), u64_lo32(vm->va_limit - 1) & ~0xfff); - gk20a_mem_wr32(g, inst_block, ram_in_adr_limit_hi_w(), + nvgpu_mem_wr32(g, inst_block, ram_in_adr_limit_hi_w(), ram_in_adr_limit_hi_f(u64_hi32(vm->va_limit - 1))); if (big_page_size && g->ops.mm.set_big_page_size) diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h index da8bbb0a..3c701907 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h @@ -220,7 +220,7 @@ struct gk20a_mmu_level { u32 kind_v, u64 *ctag, bool cacheable, bool unmapped_pte, int rw_flag, bool sparse, bool priv, - enum gk20a_aperture aperture); + enum nvgpu_aperture aperture); size_t entry_size; }; @@ -514,7 +514,7 @@ u64 gk20a_gmmu_map(struct vm_gk20a *vm, u32 flags, int rw_flag, bool priv, - enum gk20a_aperture aperture); + enum nvgpu_aperture aperture); u64 gk20a_gmmu_fixed_map(struct vm_gk20a *vm, struct sg_table **sgt, u64 addr, @@ -522,7 +522,7 @@ u64 gk20a_gmmu_fixed_map(struct vm_gk20a *vm, u32 flags, int rw_flag, bool priv, - enum gk20a_aperture aperture); + enum nvgpu_aperture aperture); /* Flags for the below gk20a_gmmu_{alloc,alloc_map}_flags* */ @@ -589,9 +589,9 @@ static inline phys_addr_t gk20a_mem_phys(struct mem_desc *mem) return 0; } -u32 __gk20a_aperture_mask(struct gk20a *g, enum gk20a_aperture aperture, +u32 __nvgpu_aperture_mask(struct gk20a *g, enum nvgpu_aperture aperture, u32 sysmem_mask, u32 vidmem_mask); -u32 gk20a_aperture_mask(struct gk20a *g, struct mem_desc *mem, +u32 nvgpu_aperture_mask(struct gk20a *g, struct mem_desc *mem, u32 sysmem_mask, u32 vidmem_mask); void gk20a_pde_wr32(struct gk20a *g, struct gk20a_mm_entry *entry, @@ -612,7 +612,7 @@ u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm, bool sparse, bool priv, struct vm_gk20a_mapping_batch *batch, - enum gk20a_aperture aperture); + enum nvgpu_aperture aperture); void gk20a_gmmu_unmap(struct vm_gk20a *vm, u64 vaddr, diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 3297d376..e70e50c2 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c @@ -307,7 +307,7 @@ static void printtrace(struct pmu_gk20a *pmu) return; /* read pmu traces into system memory buffer */ - gk20a_mem_rd_n(g, &pmu->trace_buf, + nvgpu_mem_rd_n(g, &pmu->trace_buf, 0, tracebuffer, GK20A_PMU_TRACE_BUFSIZE); trace = (char *)tracebuffer; @@ -3155,7 +3155,7 @@ static int gk20a_prepare_ucode(struct gk20a *g) if (err) goto err_release_fw; - gk20a_mem_wr_n(g, &pmu->ucode, 0, pmu->ucode_image, + nvgpu_mem_wr_n(g, &pmu->ucode, 0, pmu->ucode_image, pmu->desc->app_start_offset + pmu->desc->app_size); return gk20a_init_pmu(pmu); @@ -4872,7 +4872,7 @@ int gk20a_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd, (struct flcn_mem_desc_v0 *) pv->pmu_allocation_get_fb_addr(pmu, in)); - gk20a_mem_wr_n(g, seq->in_mem, 0, + nvgpu_mem_wr_n(g, seq->in_mem, 0, payload->in.buf, payload->in.fb_size); } else { @@ -5736,7 +5736,7 @@ static int falc_trace_show(struct seq_file *s, void *data) return -ENOMEM; /* read pmu traces into system memory buffer */ - gk20a_mem_rd_n(g, &pmu->trace_buf, + nvgpu_mem_rd_n(g, &pmu->trace_buf, 0, tracebuffer, GK20A_PMU_TRACE_BUFSIZE); trace = (char *)tracebuffer; diff --git a/drivers/gpu/nvgpu/gk20a/pramin_gk20a.c b/drivers/gpu/nvgpu/gk20a/pramin_gk20a.c index bed2e9b5..7e6005a2 100644 --- a/drivers/gpu/nvgpu/gk20a/pramin_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pramin_gk20a.c @@ -32,7 +32,7 @@ static u32 gk20a_pramin_enter(struct gk20a *g, struct mem_desc *mem, u32 hi = (u32)((addr & ~(u64)0xfffff) >> bus_bar0_window_target_bar0_window_base_shift_v()); u32 lo = (u32)(addr & 0xfffff); - u32 win = gk20a_aperture_mask(g, mem, + u32 win = nvgpu_aperture_mask(g, mem, bus_bar0_window_target_sys_mem_noncoherent_f(), bus_bar0_window_target_vid_mem_f()) | bus_bar0_window_base_f(hi); diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index 360cfc33..da3adb72 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c @@ -723,7 +723,7 @@ static void lsfm_init_wpr_contents(struct gk20a *g, struct ls_flcn_mgr *plsfm, */ while (pnode) { /* Flush WPR header to memory*/ - gk20a_mem_wr_n(g, ucode, i * sizeof(pnode->wpr_header), + nvgpu_mem_wr_n(g, ucode, i * sizeof(pnode->wpr_header), &pnode->wpr_header, sizeof(pnode->wpr_header)); gm20b_dbg_pmu("wpr header"); @@ -739,7 +739,7 @@ static void lsfm_init_wpr_contents(struct gk20a *g, struct ls_flcn_mgr *plsfm, pnode->wpr_header.status); /*Flush LSB header to memory*/ - gk20a_mem_wr_n(g, ucode, pnode->wpr_header.lsb_offset, + nvgpu_mem_wr_n(g, ucode, pnode->wpr_header.lsb_offset, &pnode->lsb_header, sizeof(pnode->lsb_header)); gm20b_dbg_pmu("lsb header"); @@ -773,13 +773,13 @@ static void lsfm_init_wpr_contents(struct gk20a *g, struct ls_flcn_mgr *plsfm, if (!pnode->ucode_img.header) { /*Populate gen bl and flush to memory*/ lsfm_fill_flcn_bl_gen_desc(g, pnode); - gk20a_mem_wr_n(g, ucode, + nvgpu_mem_wr_n(g, ucode, pnode->lsb_header.bl_data_off, &pnode->bl_gen_desc, pnode->bl_gen_desc_size); } /*Copying of ucode*/ - gk20a_mem_wr_n(g, ucode, pnode->lsb_header.ucode_off, + nvgpu_mem_wr_n(g, ucode, pnode->lsb_header.ucode_off, pnode->ucode_img.data, pnode->ucode_img.data_size); pnode = pnode->next; @@ -787,7 +787,7 @@ static void lsfm_init_wpr_contents(struct gk20a *g, struct ls_flcn_mgr *plsfm, } /* Tag the terminator WPR header with an invalid falcon ID. */ - gk20a_mem_wr32(g, ucode, + nvgpu_mem_wr32(g, ucode, plsfm->managed_flcn_cnt * sizeof(struct lsf_wpr_header) + offsetof(struct lsf_wpr_header, falcon_id), LSF_FALCON_ID_INVALID); @@ -1133,7 +1133,7 @@ static int gm20b_bootstrap_hs_flcn(struct gk20a *g) ((struct flcn_acr_desc *)acr_dmem)->regions.no_regions = 2; ((struct flcn_acr_desc *)acr_dmem)->wpr_offset = 0; - gk20a_mem_wr_n(g, &acr->acr_ucode, 0, + nvgpu_mem_wr_n(g, &acr->acr_ucode, 0, acr_ucode_data_t210_load, img_size_in_bytes); /* * In order to execute this binary, we will be using @@ -1433,7 +1433,7 @@ int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt) goto err_free_ucode; } - gk20a_mem_wr_n(g, &acr->hsbl_ucode, 0, pmu_bl_gm10x, bl_sz); + nvgpu_mem_wr_n(g, &acr->hsbl_ucode, 0, pmu_bl_gm10x, bl_sz); gm20b_dbg_pmu("Copied bl ucode to bl_cpuva\n"); } /* diff --git a/drivers/gpu/nvgpu/gm20b/bus_gm20b.c b/drivers/gpu/nvgpu/gm20b/bus_gm20b.c index 68a4b15f..ba04945b 100644 --- a/drivers/gpu/nvgpu/gm20b/bus_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/bus_gm20b.c @@ -33,7 +33,7 @@ static int gm20b_bus_bar1_bind(struct gk20a *g, struct mem_desc *bar1_inst) gk20a_dbg_info("bar1 inst block ptr: 0x%08x", ptr_v); gk20a_writel(g, bus_bar1_block_r(), - gk20a_aperture_mask(g, bar1_inst, + nvgpu_aperture_mask(g, bar1_inst, bus_bar1_block_target_sys_mem_ncoh_f(), bus_bar1_block_target_vid_mem_f()) | bus_bar1_block_mode_virtual_f() | diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index edf962de..6c34689b 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c @@ -41,7 +41,7 @@ static void channel_gm20b_bind(struct channel_gk20a *c) gk20a_writel(g, ccsr_channel_inst_r(c->hw_chid), ccsr_channel_inst_ptr_f(inst_ptr) | - gk20a_aperture_mask(g, &c->inst_block, + nvgpu_aperture_mask(g, &c->inst_block, ccsr_channel_inst_target_sys_mem_ncoh_f(), ccsr_channel_inst_target_vid_mem_f()) | ccsr_channel_inst_bind_true_f()); diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index a5dbe23d..57bff64f 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -862,7 +862,7 @@ static void gr_gm20b_update_ctxsw_preemption_mode(struct gk20a *g, if (gr_ctx->compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CTA) { gk20a_dbg_info("CTA: %x", cta_preempt_option); - gk20a_mem_wr(g, mem, + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_preemption_options_o(), cta_preempt_option); } @@ -1022,15 +1022,15 @@ static int gr_gm20b_update_pc_sampling(struct channel_gk20a *c, mem = &ch_ctx->gr_ctx->mem; - if (gk20a_mem_begin(c->g, mem)) + if (nvgpu_mem_begin(c->g, mem)) return -ENOMEM; - v = gk20a_mem_rd(c->g, mem, ctxsw_prog_main_image_pm_o()); + v = nvgpu_mem_rd(c->g, mem, ctxsw_prog_main_image_pm_o()); v &= ~ctxsw_prog_main_image_pm_pc_sampling_m(); v |= ctxsw_prog_main_image_pm_pc_sampling_f(enable); - gk20a_mem_wr(c->g, mem, ctxsw_prog_main_image_pm_o(), v); + nvgpu_mem_wr(c->g, mem, ctxsw_prog_main_image_pm_o(), v); - gk20a_mem_end(c->g, mem); + nvgpu_mem_end(c->g, mem); gk20a_dbg_fn("done"); @@ -1112,9 +1112,9 @@ static void gr_gm20b_enable_cde_in_fecs(struct gk20a *g, struct mem_desc *mem) { u32 cde_v; - cde_v = gk20a_mem_rd(g, mem, ctxsw_prog_main_image_ctl_o()); + cde_v = nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_ctl_o()); cde_v |= ctxsw_prog_main_image_ctl_cde_enabled_f(); - gk20a_mem_wr(g, mem, ctxsw_prog_main_image_ctl_o(), cde_v); + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_ctl_o(), cde_v); } static void gr_gm20b_bpt_reg_info(struct gk20a *g, struct warpstate *w_state) diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c index 949a5c5d..08d446e7 100644 --- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c @@ -28,7 +28,7 @@ static void gm20b_mm_set_big_page_size(struct gk20a *g, gk20a_dbg_fn(""); gk20a_dbg_info("big page size %d\n", size); - val = gk20a_mem_rd32(g, mem, ram_in_big_page_size_w()); + val = nvgpu_mem_rd32(g, mem, ram_in_big_page_size_w()); val &= ~ram_in_big_page_size_m(); if (size == SZ_64K) @@ -36,7 +36,7 @@ static void gm20b_mm_set_big_page_size(struct gk20a *g, else val |= ram_in_big_page_size_128kb_f(); - gk20a_mem_wr32(g, mem, ram_in_big_page_size_w(), val); + nvgpu_mem_wr32(g, mem, ram_in_big_page_size_w(), val); gk20a_dbg_fn("done"); } diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c index c7638d3e..ee709ed1 100644 --- a/drivers/gpu/nvgpu/gp106/acr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c @@ -701,7 +701,7 @@ static void lsfm_init_wpr_contents(struct gk20a *g, */ while (pnode) { /* Flush WPR header to memory*/ - gk20a_mem_wr_n(g, ucode, i * sizeof(pnode->wpr_header), + nvgpu_mem_wr_n(g, ucode, i * sizeof(pnode->wpr_header), &pnode->wpr_header, sizeof(pnode->wpr_header)); gp106_dbg_pmu("wpr header"); @@ -717,7 +717,7 @@ static void lsfm_init_wpr_contents(struct gk20a *g, pnode->wpr_header.status); /*Flush LSB header to memory*/ - gk20a_mem_wr_n(g, ucode, pnode->wpr_header.lsb_offset, + nvgpu_mem_wr_n(g, ucode, pnode->wpr_header.lsb_offset, &pnode->lsb_header, sizeof(pnode->lsb_header)); gp106_dbg_pmu("lsb header"); @@ -751,13 +751,13 @@ static void lsfm_init_wpr_contents(struct gk20a *g, if (!pnode->ucode_img.header) { /*Populate gen bl and flush to memory*/ lsfm_fill_flcn_bl_gen_desc(g, pnode); - gk20a_mem_wr_n(g, ucode, + nvgpu_mem_wr_n(g, ucode, pnode->lsb_header.bl_data_off, &pnode->bl_gen_desc, pnode->bl_gen_desc_size); } /*Copying of ucode*/ - gk20a_mem_wr_n(g, ucode, pnode->lsb_header.ucode_off, + nvgpu_mem_wr_n(g, ucode, pnode->lsb_header.ucode_off, pnode->ucode_img.data, pnode->ucode_img.data_size); pnode = pnode->next; @@ -765,7 +765,7 @@ static void lsfm_init_wpr_contents(struct gk20a *g, } /* Tag the terminator WPR header with an invalid falcon ID. */ - gk20a_mem_wr32(g, ucode, + nvgpu_mem_wr32(g, ucode, plsfm->managed_flcn_cnt * sizeof(struct lsf_wpr_header) + offsetof(struct lsf_wpr_header, falcon_id), LSF_FALCON_ID_INVALID); @@ -1124,7 +1124,7 @@ static int gp106_bootstrap_hs_flcn(struct gk20a *g) ((struct flcn_acr_desc_v1 *)acr_dmem)->regions.region_props[ 0].shadowmMem_startaddress = wpr_inf.nonwpr_base >> 8; - gk20a_mem_wr_n(g, &acr->acr_ucode, 0, + nvgpu_mem_wr_n(g, &acr->acr_ucode, 0, acr_ucode_data_t210_load, img_size_in_bytes); /* diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c index dd67f882..5a331480 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c @@ -170,7 +170,7 @@ int bl_bootstrap_sec2(struct pmu_gk20a *pmu, pwr_pmu_new_instblk_ptr_f( gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | pwr_pmu_new_instblk_valid_f(1) | - gk20a_aperture_mask(g, &mm->pmu.inst_block, + nvgpu_aperture_mask(g, &mm->pmu.inst_block, pwr_pmu_new_instblk_target_sys_coh_f(), pwr_pmu_new_instblk_target_fb_f())); @@ -315,7 +315,7 @@ void init_pmu_setup_hw1(struct gk20a *g) pwr_pmu_new_instblk_ptr_f( gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | pwr_pmu_new_instblk_valid_f(1) | - gk20a_aperture_mask(g, &mm->pmu.inst_block, + nvgpu_aperture_mask(g, &mm->pmu.inst_block, pwr_pmu_new_instblk_target_sys_coh_f(), pwr_pmu_new_instblk_target_fb_f())); diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c index 6f1a0298..3787662b 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c @@ -33,18 +33,18 @@ static void gp10b_set_pdb_fault_replay_flags(struct gk20a *g, gk20a_dbg_fn(""); - val = gk20a_mem_rd32(g, mem, + val = nvgpu_mem_rd32(g, mem, ram_in_page_dir_base_fault_replay_tex_w()); val &= ~ram_in_page_dir_base_fault_replay_tex_m(); val |= ram_in_page_dir_base_fault_replay_tex_true_f(); - gk20a_mem_wr32(g, mem, + nvgpu_mem_wr32(g, mem, ram_in_page_dir_base_fault_replay_tex_w(), val); - val = gk20a_mem_rd32(g, mem, + val = nvgpu_mem_rd32(g, mem, ram_in_page_dir_base_fault_replay_gcc_w()); val &= ~ram_in_page_dir_base_fault_replay_gcc_m(); val |= ram_in_page_dir_base_fault_replay_gcc_true_f(); - gk20a_mem_wr32(g, mem, + nvgpu_mem_wr32(g, mem, ram_in_page_dir_base_fault_replay_gcc_w(), val); gk20a_dbg_fn("done"); @@ -64,14 +64,14 @@ int channel_gp10b_commit_userd(struct channel_gk20a *c) gk20a_dbg_info("channel %d : set ramfc userd 0x%16llx", c->hw_chid, (u64)c->userd_iova); - gk20a_mem_wr32(g, &c->inst_block, + nvgpu_mem_wr32(g, &c->inst_block, ram_in_ramfc_w() + ram_fc_userd_w(), (g->mm.vidmem_is_vidmem ? pbdma_userd_target_sys_mem_ncoh_f() : pbdma_userd_target_vid_mem_f()) | pbdma_userd_addr_f(addr_lo)); - gk20a_mem_wr32(g, &c->inst_block, + nvgpu_mem_wr32(g, &c->inst_block, ram_in_ramfc_w() + ram_fc_userd_hi_w(), pbdma_userd_hi_addr_f(addr_hi)); @@ -87,25 +87,25 @@ static int channel_gp10b_setup_ramfc(struct channel_gk20a *c, gk20a_dbg_fn(""); - gk20a_memset(g, mem, 0, 0, ram_fc_size_val_v()); + nvgpu_memset(g, mem, 0, 0, ram_fc_size_val_v()); - gk20a_mem_wr32(g, mem, ram_fc_gp_base_w(), + nvgpu_mem_wr32(g, mem, ram_fc_gp_base_w(), pbdma_gp_base_offset_f( u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s()))); - gk20a_mem_wr32(g, mem, ram_fc_gp_base_hi_w(), + nvgpu_mem_wr32(g, mem, ram_fc_gp_base_hi_w(), pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) | pbdma_gp_base_hi_limit2_f(ilog2(gpfifo_entries))); - gk20a_mem_wr32(g, mem, ram_fc_signature_w(), + nvgpu_mem_wr32(g, mem, ram_fc_signature_w(), c->g->ops.fifo.get_pbdma_signature(c->g)); - gk20a_mem_wr32(g, mem, ram_fc_formats_w(), + nvgpu_mem_wr32(g, mem, ram_fc_formats_w(), pbdma_formats_gp_fermi0_f() | pbdma_formats_pb_fermi1_f() | pbdma_formats_mp_fermi0_f()); - gk20a_mem_wr32(g, mem, ram_fc_pb_header_w(), + nvgpu_mem_wr32(g, mem, ram_fc_pb_header_w(), pbdma_pb_header_priv_user_f() | pbdma_pb_header_method_zero_f() | pbdma_pb_header_subchannel_zero_f() | @@ -113,17 +113,17 @@ static int channel_gp10b_setup_ramfc(struct channel_gk20a *c, pbdma_pb_header_first_true_f() | pbdma_pb_header_type_inc_f()); - gk20a_mem_wr32(g, mem, ram_fc_subdevice_w(), + nvgpu_mem_wr32(g, mem, ram_fc_subdevice_w(), pbdma_subdevice_id_f(1) | pbdma_subdevice_status_active_f() | pbdma_subdevice_channel_dma_enable_f()); - gk20a_mem_wr32(g, mem, ram_fc_target_w(), pbdma_target_engine_sw_f()); + nvgpu_mem_wr32(g, mem, ram_fc_target_w(), pbdma_target_engine_sw_f()); - gk20a_mem_wr32(g, mem, ram_fc_acquire_w(), + nvgpu_mem_wr32(g, mem, ram_fc_acquire_w(), g->ops.fifo.pbdma_acquire_val(acquire_timeout)); - gk20a_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(), + nvgpu_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(), pbdma_runlist_timeslice_timeout_128_f() | pbdma_runlist_timeslice_timescale_3_f() | pbdma_runlist_timeslice_enable_true_f()); @@ -132,11 +132,11 @@ static int channel_gp10b_setup_ramfc(struct channel_gk20a *c, gp10b_set_pdb_fault_replay_flags(c->g, mem); - gk20a_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid)); + nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid)); if (c->is_privileged_channel) { /* Set privilege level for channel */ - gk20a_mem_wr32(g, mem, ram_fc_config_w(), + nvgpu_mem_wr32(g, mem, ram_fc_config_w(), pbdma_config_auth_level_privileged_f()); gk20a_fifo_setup_ramfc_for_privileged_channel(c); @@ -158,7 +158,7 @@ static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c) gk20a_dbg_fn(""); - v = gk20a_mem_rd32(c->g, &c->inst_block, + v = nvgpu_mem_rd32(c->g, &c->inst_block, ram_fc_allowed_syncpoints_w()); old_syncpt = pbdma_allowed_syncpoints_0_index_v(v); if (c->sync) @@ -178,7 +178,7 @@ static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c) v |= pbdma_allowed_syncpoints_0_index_f(new_syncpt); - gk20a_mem_wr32(c->g, &c->inst_block, + nvgpu_mem_wr32(c->g, &c->inst_block, ram_fc_allowed_syncpoints_w(), v); } diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 95590e40..fc831e75 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -1039,51 +1039,51 @@ static void dump_ctx_switch_stats(struct gk20a *g, struct vm_gk20a *vm, { struct mem_desc *mem = &gr_ctx->mem; - if (gk20a_mem_begin(g, mem)) { + if (nvgpu_mem_begin(g, mem)) { WARN_ON("Cannot map context"); return; } gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_magic_value_o : %x (expect %x)\n", - gk20a_mem_rd(g, mem, + nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_magic_value_o()), ctxsw_prog_main_image_magic_value_v_value_v()); gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi : %x\n", - gk20a_mem_rd(g, mem, + nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o())); gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_ptr : %x\n", - gk20a_mem_rd(g, mem, + nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_context_timestamp_buffer_ptr_o())); gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_control : %x\n", - gk20a_mem_rd(g, mem, + nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_context_timestamp_buffer_control_o())); gk20a_err(dev_from_gk20a(g), "NUM_SAVE_OPERATIONS : %d\n", - gk20a_mem_rd(g, mem, + nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_num_save_ops_o())); gk20a_err(dev_from_gk20a(g), "WFI_SAVE_OPERATIONS : %d\n", - gk20a_mem_rd(g, mem, + nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_num_wfi_save_ops_o())); gk20a_err(dev_from_gk20a(g), "CTA_SAVE_OPERATIONS : %d\n", - gk20a_mem_rd(g, mem, + nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_num_cta_save_ops_o())); gk20a_err(dev_from_gk20a(g), "GFXP_SAVE_OPERATIONS : %d\n", - gk20a_mem_rd(g, mem, + nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_num_gfxp_save_ops_o())); gk20a_err(dev_from_gk20a(g), "CILP_SAVE_OPERATIONS : %d\n", - gk20a_mem_rd(g, mem, + nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_num_cilp_save_ops_o())); gk20a_err(dev_from_gk20a(g), "image gfx preemption option (GFXP is 1) %x\n", - gk20a_mem_rd(g, mem, + nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_graphics_preemption_options_o())); gk20a_err(dev_from_gk20a(g), "image compute preemption option (CTA is 1) %x\n", - gk20a_mem_rd(g, mem, + nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_compute_preemption_options_o())); - gk20a_mem_end(g, mem); + nvgpu_mem_end(g, mem); } static void gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, @@ -1123,21 +1123,21 @@ static void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, if (gr_ctx->graphics_preempt_mode == NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP) { gk20a_dbg_info("GfxP: %x", gfxp_preempt_option); - gk20a_mem_wr(g, mem, + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_graphics_preemption_options_o(), gfxp_preempt_option); } if (gr_ctx->compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CILP) { gk20a_dbg_info("CILP: %x", cilp_preempt_option); - gk20a_mem_wr(g, mem, + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_compute_preemption_options_o(), cilp_preempt_option); } if (gr_ctx->compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CTA) { gk20a_dbg_info("CTA: %x", cta_preempt_option); - gk20a_mem_wr(g, mem, + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_compute_preemption_options_o(), cta_preempt_option); } @@ -1147,7 +1147,7 @@ static void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, u32 size; u32 cbes_reserve; - gk20a_mem_wr(g, mem, + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_full_preemption_ptr_o(), gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va >> 8); @@ -2077,7 +2077,7 @@ static int gr_gp10b_set_boosted_ctx(struct channel_gk20a *ch, gr_ctx->boosted_ctx = boost; - if (gk20a_mem_begin(g, mem)) + if (nvgpu_mem_begin(g, mem)) return -ENOMEM; err = gk20a_disable_channel_tsg(g, ch); @@ -2096,7 +2096,7 @@ static int gr_gp10b_set_boosted_ctx(struct channel_gk20a *ch, enable_ch: gk20a_enable_channel_tsg(g, ch); unmap_ctx: - gk20a_mem_end(g, mem); + nvgpu_mem_end(g, mem); return err; } @@ -2107,7 +2107,7 @@ static void gr_gp10b_update_boosted_ctx(struct gk20a *g, struct mem_desc *mem, v = ctxsw_prog_main_image_pmu_options_boost_clock_frequencies_f( gr_ctx->boosted_ctx); - gk20a_mem_wr(g, mem, ctxsw_prog_main_image_pmu_options_o(), v); + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_pmu_options_o(), v); } static int gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, @@ -2164,7 +2164,7 @@ static int gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, } } - if (gk20a_mem_begin(g, mem)) + if (nvgpu_mem_begin(g, mem)) return -ENOMEM; err = gk20a_disable_channel_tsg(g, ch); @@ -2191,7 +2191,7 @@ static int gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, enable_ch: gk20a_enable_channel_tsg(g, ch); unmap_ctx: - gk20a_mem_end(g, mem); + nvgpu_mem_end(g, mem); return err; } diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index a5322bad..8c6340f0 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -107,7 +107,7 @@ static int gb10b_init_bar2_mm_hw_setup(struct gk20a *g) gk20a_dbg_info("bar2 inst block ptr: 0x%08x", (u32)inst_pa); gk20a_writel(g, bus_bar2_block_r(), - gk20a_aperture_mask(g, inst_block, + nvgpu_aperture_mask(g, inst_block, bus_bar2_block_target_sys_mem_ncoh_f(), bus_bar2_block_target_vid_mem_f()) | bus_bar2_block_mode_virtual_f() | @@ -162,7 +162,7 @@ static int update_gmmu_pde3_locked(struct vm_gk20a *vm, u32 kind_v, u64 *ctag, bool cacheable, bool unmapped_pte, int rw_flag, bool sparse, bool priv, - enum gk20a_aperture aperture) + enum nvgpu_aperture aperture) { struct gk20a *g = gk20a_from_vm(vm); u64 pte_addr = 0; @@ -174,7 +174,7 @@ static int update_gmmu_pde3_locked(struct vm_gk20a *vm, pte_addr = gk20a_pde_addr(g, pte) >> gmmu_new_pde_address_shift_v(); - pde_v[0] |= gk20a_aperture_mask(g, &pte->mem, + pde_v[0] |= nvgpu_aperture_mask(g, &pte->mem, gmmu_new_pde_aperture_sys_mem_ncoh_f(), gmmu_new_pde_aperture_video_memory_f()); pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(pte_addr)); @@ -205,7 +205,7 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm, u32 kind_v, u64 *ctag, bool cacheable, bool unmapped_pte, int rw_flag, bool sparse, bool priv, - enum gk20a_aperture aperture) + enum nvgpu_aperture aperture) { struct gk20a *g = gk20a_from_vm(vm); bool small_valid, big_valid; @@ -230,7 +230,7 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm, if (small_valid) { pde_v[2] |= gmmu_new_dual_pde_address_small_sys_f(pte_addr_small); - pde_v[2] |= gk20a_aperture_mask(g, &entry->mem, + pde_v[2] |= nvgpu_aperture_mask(g, &entry->mem, gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(), gmmu_new_dual_pde_aperture_small_video_memory_f()); pde_v[2] |= gmmu_new_dual_pde_vol_small_true_f(); @@ -240,7 +240,7 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm, if (big_valid) { pde_v[0] |= gmmu_new_dual_pde_address_big_sys_f(pte_addr_big); pde_v[0] |= gmmu_new_dual_pde_vol_big_true_f(); - pde_v[0] |= gk20a_aperture_mask(g, &entry->mem, + pde_v[0] |= nvgpu_aperture_mask(g, &entry->mem, gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(), gmmu_new_dual_pde_aperture_big_video_memory_f()); pde_v[1] |= pte_addr_big >> 28; @@ -268,7 +268,7 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm, u32 kind_v, u64 *ctag, bool cacheable, bool unmapped_pte, int rw_flag, bool sparse, bool priv, - enum gk20a_aperture aperture) + enum nvgpu_aperture aperture) { struct gk20a *g = vm->mm->g; u32 page_size = vm->gmmu_page_sizes[gmmu_pgsz_idx]; @@ -284,7 +284,7 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm, u32 pte_addr = aperture == APERTURE_SYSMEM ? gmmu_new_pte_address_sys_f(iova_v) : gmmu_new_pte_address_vid_f(iova_v); - u32 pte_tgt = __gk20a_aperture_mask(g, aperture, + u32 pte_tgt = __nvgpu_aperture_mask(g, aperture, gmmu_new_pte_aperture_sys_mem_ncoh_f(), gmmu_new_pte_aperture_video_memory_f()); @@ -384,15 +384,15 @@ static void gp10b_mm_init_pdb(struct gk20a *g, struct mem_desc *inst_block, gk20a_dbg_info("pde pa=0x%llx", pdb_addr); - gk20a_mem_wr32(g, inst_block, ram_in_page_dir_base_lo_w(), - gk20a_aperture_mask(g, &vm->pdb.mem, + nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_lo_w(), + nvgpu_aperture_mask(g, &vm->pdb.mem, ram_in_page_dir_base_target_sys_mem_ncoh_f(), ram_in_page_dir_base_target_vid_mem_f()) | ram_in_page_dir_base_vol_true_f() | ram_in_page_dir_base_lo_f(pdb_addr_lo) | 1 << 10); - gk20a_mem_wr32(g, inst_block, ram_in_page_dir_base_hi_w(), + nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_hi_w(), ram_in_page_dir_base_hi_f(pdb_addr_hi)); } diff --git a/drivers/gpu/nvgpu/include/nvgpu/mem_desc.h b/drivers/gpu/nvgpu/include/nvgpu/mem_desc.h index 528fd7bc..42d8854a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/mem_desc.h +++ b/drivers/gpu/nvgpu/include/nvgpu/mem_desc.h @@ -28,11 +28,11 @@ struct gk20a; struct nvgpu_allocator; /* - * Real location of a buffer - gk20a_aperture_mask() will deduce what will be + * Real location of a buffer - nvgpu_aperture_mask() will deduce what will be * told to the gpu about the aperture, but this flag designates where the * memory actually was allocated from. */ -enum gk20a_aperture { +enum nvgpu_aperture { APERTURE_INVALID, /* unallocated or N/A */ APERTURE_SYSMEM, APERTURE_VIDMEM @@ -42,7 +42,7 @@ struct mem_desc { void *cpu_va; /* sysmem only */ struct page **pages; /* sysmem only */ struct sg_table *sgt; - enum gk20a_aperture aperture; + enum nvgpu_aperture aperture; size_t size; u64 gpu_va; bool fixed; /* vidmem only */ @@ -65,7 +65,7 @@ struct mem_desc_sub { u32 size; }; -static inline const char *gk20a_aperture_str(enum gk20a_aperture aperture) +static inline const char *nvgpu_aperture_str(enum nvgpu_aperture aperture) { switch (aperture) { case APERTURE_INVALID: return "invalid"; @@ -80,32 +80,32 @@ static inline const char *gk20a_aperture_str(enum gk20a_aperture aperture) * kernel mapping for this buffer. */ -int gk20a_mem_begin(struct gk20a *g, struct mem_desc *mem); +int nvgpu_mem_begin(struct gk20a *g, struct mem_desc *mem); /* nop for null mem, like with free() or vunmap() */ -void gk20a_mem_end(struct gk20a *g, struct mem_desc *mem); +void nvgpu_mem_end(struct gk20a *g, struct mem_desc *mem); /* word-indexed offset */ -u32 gk20a_mem_rd32(struct gk20a *g, struct mem_desc *mem, u32 w); +u32 nvgpu_mem_rd32(struct gk20a *g, struct mem_desc *mem, u32 w); /* byte offset (32b-aligned) */ -u32 gk20a_mem_rd(struct gk20a *g, struct mem_desc *mem, u32 offset); +u32 nvgpu_mem_rd(struct gk20a *g, struct mem_desc *mem, u32 offset); /* memcpy to cpu, offset and size in bytes (32b-aligned) */ -void gk20a_mem_rd_n(struct gk20a *g, struct mem_desc *mem, u32 offset, +void nvgpu_mem_rd_n(struct gk20a *g, struct mem_desc *mem, u32 offset, void *dest, u32 size); /* word-indexed offset */ -void gk20a_mem_wr32(struct gk20a *g, struct mem_desc *mem, u32 w, u32 data); +void nvgpu_mem_wr32(struct gk20a *g, struct mem_desc *mem, u32 w, u32 data); /* byte offset (32b-aligned) */ -void gk20a_mem_wr(struct gk20a *g, struct mem_desc *mem, u32 offset, u32 data); +void nvgpu_mem_wr(struct gk20a *g, struct mem_desc *mem, u32 offset, u32 data); /* memcpy from cpu, offset and size in bytes (32b-aligned) */ -void gk20a_mem_wr_n(struct gk20a *g, struct mem_desc *mem, u32 offset, +void nvgpu_mem_wr_n(struct gk20a *g, struct mem_desc *mem, u32 offset, void *src, u32 size); /* size and offset in bytes (32b-aligned), filled with the constant byte c */ -void gk20a_memset(struct gk20a *g, struct mem_desc *mem, u32 offset, +void nvgpu_memset(struct gk20a *g, struct mem_desc *mem, u32 offset, u32 c, u32 size); -u32 __gk20a_aperture_mask(struct gk20a *g, enum gk20a_aperture aperture, +u32 __nvgpu_aperture_mask(struct gk20a *g, enum nvgpu_aperture aperture, u32 sysmem_mask, u32 vidmem_mask); -u32 gk20a_aperture_mask(struct gk20a *g, struct mem_desc *mem, +u32 nvgpu_aperture_mask(struct gk20a *g, struct mem_desc *mem, u32 sysmem_mask, u32 vidmem_mask); #endif diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c index 3d908b0d..2da18fb8 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c @@ -51,7 +51,7 @@ static u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, bool sparse, bool priv, struct vm_gk20a_mapping_batch *batch, - enum gk20a_aperture aperture) + enum nvgpu_aperture aperture) { int err = 0; struct device *d = dev_from_vm(vm); diff --git a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c index 54ac36db..11fcf925 100644 --- a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c @@ -86,7 +86,7 @@ static u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm, bool sparse, bool priv, struct vm_gk20a_mapping_batch *batch, - enum gk20a_aperture aperture) + enum nvgpu_aperture aperture) { int err = 0; struct device *d = dev_from_vm(vm); -- cgit v1.2.2