From af637c81fe6360dbe81373b6f1e5dbdd3ca35536 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Tue, 27 Sep 2016 14:54:50 +0530 Subject: gpu: nvgpu: Update volt pwm source & raw period - calculate raw period as per pwm source - update pwm source for logic & sram rails. JIRA DNVGPU-123 Change-Id: I50b41d51b6aba760710700522dced7859f815463 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1227626 (cherry picked from commit 6eb5a235dd7bf9031ef1bcfadd6312a2f8758fd4) Reviewed-on: http://git-master/r/1244663 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp106/clk_gp106.c | 6 ++++++ drivers/gpu/nvgpu/volt/volt_dev.c | 14 ++++++++++---- 2 files changed, 16 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c index 4bf03661..1dd3922a 100644 --- a/drivers/gpu/nvgpu/gp106/clk_gp106.c +++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c @@ -36,7 +36,12 @@ static int clk_gp106_debugfs_init(struct gk20a *g); #endif #define NUM_NAMEMAPS 4 +#define XTAL4X_KHZ 108000 +static u32 gp106_crystal_clk_hz(struct gk20a *g) +{ + return (XTAL4X_KHZ * 1000); +} static int gp106_init_clk_support(struct gk20a *g) { struct clk_gk20a *clk = &g->clk; u32 err = 0; @@ -221,6 +226,7 @@ err_out: void gp106_init_clk_ops(struct gpu_ops *gops) { gops->clk.init_clk_support = gp106_init_clk_support; + gops->clk.get_crystal_clk_hz = gp106_crystal_clk_hz; } diff --git a/drivers/gpu/nvgpu/volt/volt_dev.c b/drivers/gpu/nvgpu/volt/volt_dev.c index 89040658..3a7ed1b5 100644 --- a/drivers/gpu/nvgpu/volt/volt_dev.c +++ b/drivers/gpu/nvgpu/volt/volt_dev.c @@ -26,7 +26,6 @@ #include "include/bios.h" #include "volt.h" -#define RAW_PERIOD 160 #define VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID 0 #define VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT 1 @@ -257,17 +256,24 @@ static u32 volt_get_voltage_device_table_1x_psv(struct gk20a *g, if (ptmp_dev->super.operation_type == CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT) { - ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1; + if (volt_domain == CTRL_VOLT_DOMAIN_LOGIC) + ptmp_dev->source = + NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_0; + if (volt_domain == CTRL_VOLT_DOMAIN_SRAM) + ptmp_dev->source = + NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1; + ptmp_dev->raw_period = + g->ops.clk.get_crystal_clk_hz(g) / frequency_hz; } else if (ptmp_dev->super.operation_type == CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE) { ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_RSVD_0; + ptmp_dev->raw_period = 0; } else if (ptmp_dev->super.operation_type == CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE) { ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_RSVD_1; + ptmp_dev->raw_period = 0; } - ptmp_dev->raw_period = RAW_PERIOD; - /* Initialize data for parent class. */ ptmp_dev->super.super.type = CTRL_VOLT_DEVICE_TYPE_PWM; ptmp_dev->super.volt_domain = volt_domain; -- cgit v1.2.2