From 9ae69536b997db1ffa5ef81599a73e164efe8b9d Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 26 Mar 2018 18:23:52 -0700 Subject: gpu: nvgpu: gv11b: chip revision check for invalidates Only for T194 A01 version following invalidates are disabled: -CBM alpha and beta invalidations for L2 -SCC pagepool invalidates -SWDX spill buffer invalidates Bug 2053668 Change-Id: I7122b223946a1bfa4b11ed8ee782572215313dc1 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1680500 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/linux/soc.c | 8 ++++++++ drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 12 ++++++------ drivers/gpu/nvgpu/include/nvgpu/soc.h | 1 + 3 files changed, 15 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/common/linux/soc.c b/drivers/gpu/nvgpu/common/linux/soc.c index 305d8bd9..1b27d6f1 100644 --- a/drivers/gpu/nvgpu/common/linux/soc.c +++ b/drivers/gpu/nvgpu/common/linux/soc.c @@ -12,6 +12,7 @@ */ #include +#include #include #ifdef CONFIG_TEGRA_HV_MANAGER #include @@ -46,6 +47,13 @@ bool nvgpu_is_bpmp_running(struct gk20a *g) return tegra_bpmp_running(); } +bool nvgpu_is_soc_t194_a01(struct gk20a *g) +{ + return ((tegra_get_chip_id() == TEGRA194 && + tegra_chip_get_revision() == TEGRA194_REVISION_A01) ? + true : false); +} + #ifdef CONFIG_TEGRA_HV_MANAGER /* When nvlink is enabled on dGPU, we need to use physical memory addresses. * There is no SMMU translation. However, the device initially enumerates as a diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 536d9dcb..df323da1 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -31,6 +31,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/gr_gk20a.h" @@ -2860,7 +2861,6 @@ int gr_gv11b_init_fs_state(struct gk20a *g) u32 data; int err; u32 ver = g->params.gpu_arch + g->params.gpu_impl; - u32 rev = g->params.gpu_rev; nvgpu_log_fn(g, " "); @@ -2869,9 +2869,9 @@ int gr_gv11b_init_fs_state(struct gk20a *g) gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f()); gk20a_writel(g, gr_gpcs_tpcs_sm_texio_control_r(), data); - if (ver == NVGPU_GPUID_GV11B && rev == 0xa1) { - - /* Disable CBM alpha and beta invalidations for l2 for gv11b A01 */ + if (ver == NVGPU_GPUID_GV11B && nvgpu_is_soc_t194_a01(g)) + { + /* Disable CBM alpha and beta invalidations for l2 for t194 A01 */ data = gk20a_readl(g, gr_gpcs_ppcs_cbm_debug_r()); data = set_field(data, gr_gpcs_ppcs_cbm_debug_invalidate_alpha_m(), @@ -2881,14 +2881,14 @@ int gr_gv11b_init_fs_state(struct gk20a *g) gr_gpcs_ppcs_cbm_debug_invalidate_beta_disable_f()); gk20a_writel(g, gr_gpcs_ppcs_cbm_debug_r(), data); - /* Disable SCC pagepool invalidates for gv11b A01 */ + /* Disable SCC pagepool invalidates for t194 A01 */ data = gk20a_readl(g, gr_scc_debug_r()); data = set_field(data, gr_scc_debug_pagepool_invalidates_m(), gr_scc_debug_pagepool_invalidates_disable_f()); gk20a_writel(g, gr_scc_debug_r(), data); - /* Disable SWDX spill buffer invalidates for gv11b A01 */ + /* Disable SWDX spill buffer invalidates */ data = gk20a_readl(g, gr_gpcs_swdx_spill_unit_r()); data = set_field(data, gr_gpcs_swdx_spill_unit_spill_buffer_cache_mgmt_mode_m(), diff --git a/drivers/gpu/nvgpu/include/nvgpu/soc.h b/drivers/gpu/nvgpu/include/nvgpu/soc.h index 3a3490d2..fc7f6341 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/soc.h +++ b/drivers/gpu/nvgpu/include/nvgpu/soc.h @@ -31,6 +31,7 @@ bool nvgpu_platform_is_simulation(struct gk20a *g); bool nvgpu_platform_is_fpga(struct gk20a *g); bool nvgpu_is_hypervisor_mode(struct gk20a *g); bool nvgpu_is_bpmp_running(struct gk20a *g); +bool nvgpu_is_soc_t194_a01(struct gk20a *g); int nvgpu_init_soc_vars(struct gk20a *g); #endif -- cgit v1.2.2