From 96d4842c0dbae051258408480b981ed034163c13 Mon Sep 17 00:00:00 2001 From: Vinod G Date: Tue, 12 Jun 2018 17:24:53 -0700 Subject: gpu: nvgpu: gv11b: fix PMA list alignment in ctxsw buffer ucode changed so that it expects LIST_nv_perf_pma_ctx_reg list in ctxsw buffer to be 256 byte aligned. This change was added to gv100 before, adding similar change to gv11b. bug 2045640 Change-Id: I1f92d38e607f70d5602ef6d5c607b9dc20807245 Signed-off-by: Vinod G Reviewed-on: https://git-master.nvidia.com/r/1747895 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 270d4dd4..2bd35f0c 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -407,7 +407,7 @@ static const struct gpu_ops gv11b_ops = { .handle_notify_pending = gk20a_gr_handle_notify_pending, .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa, - .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, + .add_ctxsw_reg_perf_pma = gr_gv100_add_ctxsw_reg_perf_pma, .decode_priv_addr = gr_gv11b_decode_priv_addr, .create_priv_addr_table = gr_gv11b_create_priv_addr_table, .get_pmm_per_chiplet_offset = -- cgit v1.2.2