From 911dcedb489ebef5758e5533f73e8653cc7770b7 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 12 Oct 2016 15:16:47 -0700 Subject: gpu: nvgpu: support t19x zbc Added infrastructure for supporting new zbc features JIRA GV11B-9 Change-Id: Id8408348759488e8b0393dd89dd0faacfb111f01 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1235525 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c | 4 +++- drivers/gpu/nvgpu/gk20a/gk20a.h | 13 +++++++++++ drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 42 ++++++++++++++++++++++++++++++++---- drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 17 +++++++++++++-- 4 files changed, 69 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c index 26eea610..aa2c4959 100644 --- a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2016, NVIDIA Corporation. All rights reserved. + * Copyright (c) 2011-2017, NVIDIA Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -1413,6 +1413,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg } break; case GK20A_ZBC_TYPE_DEPTH: + case T19X_ZBC: zbc_val->depth = set_table_args->depth; break; default: @@ -1452,6 +1453,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg } break; case GK20A_ZBC_TYPE_DEPTH: + case T19X_ZBC: query_table_args->depth = zbc_tbl->depth; break; case GK20A_ZBC_TYPE_INVALID: diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index a78ff506..00a580dd 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -142,6 +142,9 @@ struct gpu_ops { void (*set_zbc_depth_entry)(struct gk20a *g, struct zbc_entry *depth_val, u32 index); + void (*set_zbc_s_entry)(struct gk20a *g, + struct zbc_entry *s_val, + u32 index); void (*init_cbc)(struct gk20a *g, struct gr_gk20a *gr); void (*sync_debugfs)(struct gk20a *g); void (*init_fs_state)(struct gk20a *g); @@ -223,13 +226,23 @@ struct gpu_ops { struct zbc_entry *color_val, u32 index); int (*add_zbc_depth)(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *depth_val, u32 index); + int (*add_zbc_s)(struct gk20a *g, struct gr_gk20a *gr, + struct zbc_entry *s_val, u32 index); int (*zbc_set_table)(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *zbc_val); int (*zbc_query_table)(struct gk20a *g, struct gr_gk20a *gr, struct zbc_query_params *query_params); + int (*zbc_s_query_table)(struct gk20a *g, struct gr_gk20a *gr, + struct zbc_query_params *query_params); + int (*load_zbc_s_default_tbl)(struct gk20a *g, + struct gr_gk20a *gr); + int (*load_zbc_s_tbl)(struct gk20a *g, + struct gr_gk20a *gr); void (*pmu_save_zbc)(struct gk20a *g, u32 entries); int (*add_zbc)(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *zbc_val); + bool (*add_zbc_type_s)(struct gk20a *g, struct gr_gk20a *gr, + struct zbc_entry *zbc_val, int *ret_val); u32 (*pagepool_default_size)(struct gk20a *g); int (*init_ctx_state)(struct gk20a *g); int (*alloc_gr_ctx)(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index f1ef8be2..c5e927c1 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -4018,7 +4018,8 @@ int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr, { struct zbc_color_table *c_tbl; struct zbc_depth_table *d_tbl; - u32 i, ret = -ENOMEM; + u32 i; + int ret = -ENOMEM; bool added = false; u32 entries; @@ -4094,6 +4095,16 @@ int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr, gr->max_used_depth_index++; } break; + case T19X_ZBC: + if (g->ops.gr.add_zbc_type_s) { + added = g->ops.gr.add_zbc_type_s(g, gr, zbc_val, &ret); + } else { + gk20a_err(dev_from_gk20a(g), + "invalid zbc table type %d", zbc_val->type); + ret = -EINVAL; + goto err_mutex; + } + break; default: gk20a_err(dev_from_gk20a(g), "invalid zbc table type %d", zbc_val->type); @@ -4150,6 +4161,16 @@ int gr_gk20a_query_zbc(struct gk20a *g, struct gr_gk20a *gr, query_params->format = gr->zbc_dep_tbl[index].format; query_params->ref_cnt = gr->zbc_dep_tbl[index].ref_cnt; break; + case T19X_ZBC: + if (g->ops.gr.zbc_s_query_table) { + return g->ops.gr.zbc_s_query_table(g, gr, + query_params); + } else { + gk20a_err(dev_from_gk20a(g), + "invalid zbc table type\n"); + return -EINVAL; + } + break; default: gk20a_err(dev_from_gk20a(g), "invalid zbc table type\n"); @@ -4192,6 +4213,13 @@ static int gr_gk20a_load_zbc_table(struct gk20a *g, struct gr_gk20a *gr) if (ret) return ret; } + + if (g->ops.gr.load_zbc_s_tbl) { + ret = g->ops.gr.load_zbc_s_tbl(g, gr); + if (ret) + return ret; + } + return 0; } @@ -4221,7 +4249,7 @@ int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr) zbc_val.color_ds[i] = 0; zbc_val.color_l2[i] = 0; } - err = gr_gk20a_add_zbc(g, gr, &zbc_val); + err |= gr_gk20a_add_zbc(g, gr, &zbc_val); /* Opaque white (i.e. solid white) = (fmt 2 = uniform 1) */ zbc_val.format = gr_ds_zbc_color_fmt_val_unorm_one_v(); @@ -4244,11 +4272,11 @@ int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr) zbc_val.format = gr_ds_zbc_z_fmt_val_fp32_v(); zbc_val.depth = 0x3f800000; - err |= gr_gk20a_add_zbc(g, gr, &zbc_val); + err = gr_gk20a_add_zbc(g, gr, &zbc_val); zbc_val.format = gr_ds_zbc_z_fmt_val_fp32_v(); zbc_val.depth = 0; - err = gr_gk20a_add_zbc(g, gr, &zbc_val); + err |= gr_gk20a_add_zbc(g, gr, &zbc_val); if (!err) gr->max_default_depth_index = 2; @@ -4258,6 +4286,12 @@ int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr) return err; } + if (g->ops.gr.load_zbc_s_default_tbl) { + err = g->ops.gr.load_zbc_s_default_tbl(g, gr); + if (err) + return err; + } + return 0; } diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 33176df7..40b3bd44 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h @@ -1,7 +1,7 @@ /* * GK20A Graphics Engine * - * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -22,6 +22,10 @@ #ifdef CONFIG_ARCH_TEGRA_18x_SOC #include "gr_t18x.h" #endif +#ifdef CONFIG_TEGRA_19x_GPU +#include "gr_t19x.h" +#endif + #include "tsg_gk20a.h" #include "gr_ctx_gk20a.h" @@ -141,6 +145,7 @@ struct gr_zcull_info { #define GK20A_ZBC_TYPE_INVALID 0 #define GK20A_ZBC_TYPE_COLOR 1 #define GK20A_ZBC_TYPE_DEPTH 2 +#define T19X_ZBC 3 struct zbc_color_table { u32 color_ds[GK20A_ZBC_COLOR_VALUE_SIZE]; @@ -330,12 +335,20 @@ struct gr_gk20a { struct mutex zbc_lock; struct zbc_color_table zbc_col_tbl[GK20A_ZBC_TABLE_SIZE]; struct zbc_depth_table zbc_dep_tbl[GK20A_ZBC_TABLE_SIZE]; - +#ifdef CONFIG_TEGRA_19x_GPU + struct zbc_s_table zbc_s_tbl[GK20A_ZBC_TABLE_SIZE]; +#endif s32 max_default_color_index; s32 max_default_depth_index; +#ifdef CONFIG_TEGRA_19x_GPU + s32 max_default_s_index; +#endif u32 max_used_color_index; u32 max_used_depth_index; +#ifdef CONFIG_TEGRA_19x_GPU + u32 max_used_s_index; +#endif #define GR_CHANNEL_MAP_TLB_SIZE 2 /* must of power of 2 */ struct gr_channel_map_tlb_entry chid_tlb[GR_CHANNEL_MAP_TLB_SIZE]; -- cgit v1.2.2