From 8ec63298789a0912b9cbd90ee47c76f0701f0dca Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Mon, 16 Nov 2015 16:30:28 -0800 Subject: gpu: nvgpu: correct register setting for debug mode correct register settings for both set mmu debug mode and set sm debug mode. JIRA VFND-1005 Bug 1594604 Change-Id: I1d4b1d4b4cdd9d24d3b00481e0e22c4217f5a4b3 Signed-off-by: Richard Zhao Reviewed-on: http://git-master/r/833490 Reviewed-by: Aingara Paramakuru Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov --- drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c | 33 +++++++++++++++++++++------------ drivers/gpu/nvgpu/gk20a/hw_fb_gk20a.h | 8 ++++++++ drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | 20 ++++++++++++++++++++ drivers/gpu/nvgpu/gm20b/hw_fb_gm20b.h | 8 ++++++++ drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | 24 ++++++++++++++++++++++++ 5 files changed, 81 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c index 6dc92713..18567064 100644 --- a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c @@ -314,7 +314,7 @@ static int nvgpu_gpu_ioctl_set_mmu_debug_mode( struct nvgpu_gpu_mmu_debug_mode_args *args) { int err = 0; - u32 mmu_debug_ctrl; + u32 reg_val, mmu_debug_ctrl; err = gk20a_busy(g->dev); if (err) { @@ -325,16 +325,17 @@ static int nvgpu_gpu_ioctl_set_mmu_debug_mode( mutex_lock(&g->dbg_sessions_lock); if (args->state == 1) { - mmu_debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_v(); + mmu_debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f(); g->mmu_debug_ctrl = true; } else { - mmu_debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_v(); + mmu_debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f(); g->mmu_debug_ctrl = false; } - mmu_debug_ctrl = gk20a_readl(g, fb_mmu_debug_ctrl_r()); - mmu_debug_ctrl = set_field(mmu_debug_ctrl, fb_mmu_debug_ctrl_debug_m(), mmu_debug_ctrl); - gk20a_writel(g, fb_mmu_debug_ctrl_r(), mmu_debug_ctrl); + reg_val = gk20a_readl(g, fb_mmu_debug_ctrl_r()); + reg_val = set_field(reg_val, + fb_mmu_debug_ctrl_debug_m(), mmu_debug_ctrl); + gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val); mutex_unlock(&g->dbg_sessions_lock); gk20a_idle(g->dev); @@ -376,12 +377,20 @@ static int nvgpu_gpu_ioctl_set_debug_mode( sm_dbgr_ctrl0 = ops.value_lo; if (args->enable) { - sm_dbgr_ctrl0 = gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v() | - gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f() | - gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f() | - sm_dbgr_ctrl0; - } else - sm_dbgr_ctrl0 = gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v() | sm_dbgr_ctrl0; + sm_dbgr_ctrl0 = set_field(sm_dbgr_ctrl0, + gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(), + gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_f()); + sm_dbgr_ctrl0 = set_field(sm_dbgr_ctrl0, + gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(), + gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f()); + sm_dbgr_ctrl0 = set_field(sm_dbgr_ctrl0, + gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(), + gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f()); + } else { + sm_dbgr_ctrl0 = set_field(sm_dbgr_ctrl0, + gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(), + gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_f()); + } if (!err) { ops.op = REGOP(WRITE_32); diff --git a/drivers/gpu/nvgpu/gk20a/hw_fb_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_fb_gk20a.h index a0a3ae33..0234265a 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_fb_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_fb_gk20a.h @@ -202,10 +202,18 @@ static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) { return 0x00000001; } +static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void) +{ + return 0x10000; +} static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) { return 0x00000000; } +static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void) +{ + return 0x0; +} static inline u32 fb_mmu_vpr_info_r(void) { return 0x00100cd0; diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h index abe6b119..726d0ad3 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h @@ -3038,6 +3038,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void) { return 0x00504610; } +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void) +{ + return 0x1 << 0; +} static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r) { return (r >> 0) & 0x1; @@ -3046,10 +3050,18 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void) { return 0x00000001; } +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_f(void) +{ + return 0x1; +} static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void) { return 0x00000000; } +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_f(void) +{ + return 0x0; +} static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) { return 0x80000000; @@ -3062,6 +3074,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) { return 0x40000000; } +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void) +{ + return 0x1 << 1; +} static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r) { return (r >> 1) & 0x1; @@ -3070,6 +3086,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void) { return 0x0; } +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void) +{ + return 0x1 << 2; +} static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r) { return (r >> 2) & 0x1; diff --git a/drivers/gpu/nvgpu/gm20b/hw_fb_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_fb_gm20b.h index 214306cb..5ec4a46e 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_fb_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_fb_gm20b.h @@ -222,10 +222,18 @@ static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) { return 0x00000001; } +static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void) +{ + return 0x10000; +} static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) { return 0x00000000; } +static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void) +{ + return 0x0; +} static inline u32 fb_mmu_vpr_info_r(void) { return 0x00100cd0; diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h index d91d40af..a941eb59 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h @@ -3070,6 +3070,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void) { return 0x00504610; } +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void) +{ + return 0x1 << 0; +} static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r) { return (r >> 0) & 0x1; @@ -3078,6 +3082,18 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void) { return 0x00000001; } +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_f(void) +{ + return 0x1; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_f(void) +{ + return 0x0; +} static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) { return 0x80000000; @@ -3090,6 +3106,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) { return 0x40000000; } +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void) +{ + return 0x1 << 1; +} static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r) { return (r >> 1) & 0x1; @@ -3098,6 +3118,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void) { return 0x0; } +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void) +{ + return 0x1 << 2; +} static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r) { return (r >> 2) & 0x1; -- cgit v1.2.2