From 8c9b64dc4249b2785c01485eb9b499c41cc7ed78 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 9 Mar 2017 15:12:09 -0800 Subject: gpu: nvgpu: Do not query SEC2 freq from CCF dGPU's SEC2 is passed frequency, which is queried with clk_get_rate(). dGPU clocks are not represented in CCF, so the query always returned an error. The value is ignored, so this went unnoticed. Replace the call to clk_get_rate() by just hard coding 0 as the clock rate. Change-Id: I86fec3726d2b6683cdadd86cab1672f3b199378f Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1319068 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Reviewed-by: Alex Waterman Reviewed-by: Navneet Kumar --- drivers/gpu/nvgpu/gp106/sec2_gp106.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c index 92f99165..0032bce7 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c @@ -12,7 +12,6 @@ */ #include /* for udelay */ -#include #include "gk20a/gk20a.h" #include "gk20a/pmu_gk20a.h" @@ -289,7 +288,6 @@ void init_pmu_setup_hw1(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; struct pmu_gk20a *pmu = &g->pmu; - struct gk20a_platform *platform = dev_get_drvdata(g->dev); /* PMU TRANSCFG */ /* setup apertures - virtual */ @@ -322,8 +320,7 @@ void init_pmu_setup_hw1(struct gk20a *g) pwr_pmu_new_instblk_target_fb_f())); /*Copying pmu cmdline args*/ - g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, - clk_get_rate(platform->clk[1])); + g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, 0); g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1); g->ops.pmu_ver.set_pmu_cmdline_args_trace_size( pmu, GK20A_PMU_TRACE_BUFSIZE); -- cgit v1.2.2