From 876953fbb85f9440bbcc1d7d59435593886b53c4 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 6 Jul 2018 12:37:10 -0700 Subject: gpu: nvgpu: Move FB MMU query to FB HAL Move queries of FB MMU configuration to FB HAL. Also use g->ltc_count instead of reading the number of LTCs from FB. These changes together remove last direct uses of FB registers from GR. JIRA NVGPU-714 Change-Id: I1b4b46fc2f636f5c1904e4174040a47a27948999 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1773076 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gk20a.h | 4 ++++ drivers/gpu/nvgpu/gm20b/fb_gm20b.c | 20 ++++++++++++++++++++ drivers/gpu/nvgpu/gm20b/fb_gm20b.h | 4 ++++ drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 12 +++++------- drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 4 ++++ drivers/gpu/nvgpu/gp106/hal_gp106.c | 4 ++++ drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 4 ++++ drivers/gpu/nvgpu/gv100/hal_gv100.c | 4 ++++ drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 9 ++++----- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 4 ++++ 10 files changed, 57 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 4f02ce23..23ed2f15 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -505,6 +505,10 @@ struct gpu_ops { void (*init_kind_attr)(struct gk20a *g); void (*set_mmu_page_size)(struct gk20a *g); bool (*set_use_full_comp_tag_line)(struct gk20a *g); + u32 (*mmu_ctrl)(struct gk20a *g); + u32 (*mmu_debug_ctrl)(struct gk20a *g); + u32 (*mmu_debug_wr)(struct gk20a *g); + u32 (*mmu_debug_rd)(struct gk20a *g); /* * Compression tag line coverage. When mapping a compressible diff --git a/drivers/gpu/nvgpu/gm20b/fb_gm20b.c b/drivers/gpu/nvgpu/gm20b/fb_gm20b.c index 2ca8d86c..37a7944b 100644 --- a/drivers/gpu/nvgpu/gm20b/fb_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fb_gm20b.c @@ -68,6 +68,26 @@ bool gm20b_fb_set_use_full_comp_tag_line(struct gk20a *g) return true; } +u32 gm20b_fb_mmu_ctrl(struct gk20a *g) +{ + return gk20a_readl(g, fb_mmu_ctrl_r()); +} + +u32 gm20b_fb_mmu_debug_ctrl(struct gk20a *g) +{ + return gk20a_readl(g, fb_mmu_debug_ctrl_r()); +} + +u32 gm20b_fb_mmu_debug_wr(struct gk20a *g) +{ + return gk20a_readl(g, fb_mmu_debug_wr_r()); +} + +u32 gm20b_fb_mmu_debug_rd(struct gk20a *g) +{ + return gk20a_readl(g, fb_mmu_debug_rd_r()); +} + unsigned int gm20b_fb_compression_page_size(struct gk20a *g) { return SZ_128K; diff --git a/drivers/gpu/nvgpu/gm20b/fb_gm20b.h b/drivers/gpu/nvgpu/gm20b/fb_gm20b.h index 1d1d5899..1a5e9187 100644 --- a/drivers/gpu/nvgpu/gm20b/fb_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/fb_gm20b.h @@ -29,6 +29,10 @@ struct gk20a; void fb_gm20b_init_fs_state(struct gk20a *g); void gm20b_fb_set_mmu_page_size(struct gk20a *g); bool gm20b_fb_set_use_full_comp_tag_line(struct gk20a *g); +u32 gm20b_fb_mmu_ctrl(struct gk20a *g); +u32 gm20b_fb_mmu_debug_ctrl(struct gk20a *g); +u32 gm20b_fb_mmu_debug_wr(struct gk20a *g); +u32 gm20b_fb_mmu_debug_rd(struct gk20a *g); unsigned int gm20b_fb_compression_page_size(struct gk20a *g); unsigned int gm20b_fb_compressible_page_size(struct gk20a *g); u32 gm20b_fb_compression_align_mask(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 85da0d35..32ab58c1 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -36,7 +36,6 @@ #include #include -#include #include #include #include @@ -49,7 +48,7 @@ void gr_gm20b_init_gpc_mmu(struct gk20a *g) nvgpu_log_info(g, "initialize gpc mmu"); - temp = gk20a_readl(g, fb_mmu_ctrl_r()); + temp = g->ops.fb.mmu_ctrl(g); temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() | gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() | gr_gpcs_pri_mmu_ctrl_use_full_comp_tag_line_m() | @@ -65,14 +64,13 @@ void gr_gm20b_init_gpc_mmu(struct gk20a *g) gk20a_writel(g, gr_gpcs_pri_mmu_pm_req_mask_r(), 0); gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), - gk20a_readl(g, fb_mmu_debug_ctrl_r())); + g->ops.fb.mmu_debug_ctrl(g)); gk20a_writel(g, gr_gpcs_pri_mmu_debug_wr_r(), - gk20a_readl(g, fb_mmu_debug_wr_r())); + g->ops.fb.mmu_debug_wr(g)); gk20a_writel(g, gr_gpcs_pri_mmu_debug_rd_r(), - gk20a_readl(g, fb_mmu_debug_rd_r())); + g->ops.fb.mmu_debug_rd(g)); - gk20a_writel(g, gr_gpcs_mmu_num_active_ltcs_r(), - gk20a_readl(g, fb_fbhub_num_active_ltcs_r())); + gk20a_writel(g, gr_gpcs_mmu_num_active_ltcs_r(), g->ltc_count); } void gr_gm20b_bundle_cb_defaults(struct gk20a *g) diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 798b5f06..02355450 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -340,6 +340,10 @@ static const struct gpu_ops gm20b_ops = { .set_mmu_page_size = gm20b_fb_set_mmu_page_size, .set_use_full_comp_tag_line = gm20b_fb_set_use_full_comp_tag_line, + .mmu_ctrl = gm20b_fb_mmu_ctrl, + .mmu_debug_ctrl = gm20b_fb_mmu_debug_ctrl, + .mmu_debug_wr = gm20b_fb_mmu_debug_wr, + .mmu_debug_rd = gm20b_fb_mmu_debug_rd, .compression_page_size = gm20b_fb_compression_page_size, .compressible_page_size = gm20b_fb_compressible_page_size, .compression_align_mask = gm20b_fb_compression_align_mask, diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 9427d3bf..75e2f5a1 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -411,6 +411,10 @@ static const struct gpu_ops gp106_ops = { .set_mmu_page_size = gm20b_fb_set_mmu_page_size, .set_use_full_comp_tag_line = gm20b_fb_set_use_full_comp_tag_line, + .mmu_ctrl = gm20b_fb_mmu_ctrl, + .mmu_debug_ctrl = gm20b_fb_mmu_debug_ctrl, + .mmu_debug_wr = gm20b_fb_mmu_debug_wr, + .mmu_debug_rd = gm20b_fb_mmu_debug_rd, .compression_page_size = gp10b_fb_compression_page_size, .compressible_page_size = gp10b_fb_compressible_page_size, .compression_align_mask = gm20b_fb_compression_align_mask, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index a1c32a5f..a40608df 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -374,6 +374,10 @@ static const struct gpu_ops gp10b_ops = { .set_mmu_page_size = gm20b_fb_set_mmu_page_size, .set_use_full_comp_tag_line = gm20b_fb_set_use_full_comp_tag_line, + .mmu_ctrl = gm20b_fb_mmu_ctrl, + .mmu_debug_ctrl = gm20b_fb_mmu_debug_ctrl, + .mmu_debug_wr = gm20b_fb_mmu_debug_wr, + .mmu_debug_rd = gm20b_fb_mmu_debug_rd, .compression_page_size = gp10b_fb_compression_page_size, .compressible_page_size = gp10b_fb_compressible_page_size, .compression_align_mask = gm20b_fb_compression_align_mask, diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 00007044..07c71a04 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -461,6 +461,10 @@ static const struct gpu_ops gv100_ops = { .set_mmu_page_size = gm20b_fb_set_mmu_page_size, .set_use_full_comp_tag_line = gm20b_fb_set_use_full_comp_tag_line, + .mmu_ctrl = gm20b_fb_mmu_ctrl, + .mmu_debug_ctrl = gm20b_fb_mmu_debug_ctrl, + .mmu_debug_wr = gm20b_fb_mmu_debug_wr, + .mmu_debug_rd = gm20b_fb_mmu_debug_rd, .compression_page_size = gp10b_fb_compression_page_size, .compressible_page_size = gp10b_fb_compressible_page_size, .compression_align_mask = gm20b_fb_compression_align_mask, diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index ef482ba8..6ceaa47a 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -57,7 +57,6 @@ #include #include #include -#include #include #define GFXP_WFI_TIMEOUT_COUNT_IN_USEC_DEFAULT 100 @@ -4248,7 +4247,7 @@ void gr_gv11b_init_gpc_mmu(struct gk20a *g) nvgpu_log_info(g, "initialize gpc mmu"); - temp = gk20a_readl(g, fb_mmu_ctrl_r()); + temp = g->ops.fb.mmu_ctrl(g); temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() | gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() | gr_gpcs_pri_mmu_ctrl_vol_fault_m() | @@ -4269,11 +4268,11 @@ void gr_gv11b_init_gpc_mmu(struct gk20a *g) gk20a_writel(g, gr_gpcs_pri_mmu_pm_req_mask_r(), 0); gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), - gk20a_readl(g, fb_mmu_debug_ctrl_r())); + g->ops.fb.mmu_debug_ctrl(g)); gk20a_writel(g, gr_gpcs_pri_mmu_debug_wr_r(), - gk20a_readl(g, fb_mmu_debug_wr_r())); + g->ops.fb.mmu_debug_wr(g)); gk20a_writel(g, gr_gpcs_pri_mmu_debug_rd_r(), - gk20a_readl(g, fb_mmu_debug_rd_r())); + g->ops.fb.mmu_debug_rd(g)); } int gr_gv11b_init_preemption_state(struct gk20a *g) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 5bfa85da..6132a2dd 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -429,6 +429,10 @@ static const struct gpu_ops gv11b_ops = { .set_mmu_page_size = gm20b_fb_set_mmu_page_size, .set_use_full_comp_tag_line = gm20b_fb_set_use_full_comp_tag_line, + .mmu_ctrl = gm20b_fb_mmu_ctrl, + .mmu_debug_ctrl = gm20b_fb_mmu_debug_ctrl, + .mmu_debug_wr = gm20b_fb_mmu_debug_wr, + .mmu_debug_rd = gm20b_fb_mmu_debug_rd, .compression_page_size = gp10b_fb_compression_page_size, .compressible_page_size = gp10b_fb_compressible_page_size, .compression_align_mask = gm20b_fb_compression_align_mask, -- cgit v1.2.2