From 850f2ad8ada4f4c2c753644f387d75e6d75ac28b Mon Sep 17 00:00:00 2001 From: absalam Date: Thu, 20 Sep 2018 12:21:33 +0530 Subject: gpu: nvgpu:Add sysfs node for GV100 clocks Creates sysfs nodes to read clk freq on GV100 Following sysfs nodes are created: gpcclk,xbarclk,sysclk Uses default clock source and counters for measurement Bug 200446261 Change-Id: I6903ba77fbe34e3f486f4b663e70eab4e7c5d662 Signed-off-by: absalam Reviewed-on: https://git-master.nvidia.com/r/1828030 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 6 +- drivers/gpu/nvgpu/Makefile.sources | 3 +- drivers/gpu/nvgpu/gv100/clk_gv100.c | 193 +++++++++++++++++++++ drivers/gpu/nvgpu/gv100/clk_gv100.h | 63 +++++++ drivers/gpu/nvgpu/gv100/hal_gv100.c | 13 +- .../nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h | 48 +++++ drivers/gpu/nvgpu/os/linux/debug_clk_gv100.c | 193 +++++++++++++++++++++ drivers/gpu/nvgpu/os/linux/debug_clk_gv100.h | 29 ++++ drivers/gpu/nvgpu/os/linux/os_ops_gv100.c | 4 +- 9 files changed, 540 insertions(+), 12 deletions(-) create mode 100644 drivers/gpu/nvgpu/gv100/clk_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/clk_gv100.h create mode 100644 drivers/gpu/nvgpu/os/linux/debug_clk_gv100.c create mode 100644 drivers/gpu/nvgpu/os/linux/debug_clk_gv100.h (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index d7944088..d704de83 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -113,7 +113,8 @@ nvgpu-$(CONFIG_DEBUG_FS) += \ os/linux/debug_therm_gp106.o \ os/linux/debug_bios.o \ os/linux/debug_ltc.o \ - os/linux/debug_xve.o + os/linux/debug_xve.o \ + os/linux/debug_clk_gv100.o ifeq ($(CONFIG_NVGPU_TRACK_MEM_USAGE),y) nvgpu-$(CONFIG_DEBUG_FS) += \ @@ -363,4 +364,5 @@ nvgpu-y += \ therm/thrmchannel.o \ therm/thrmpmu.o \ lpwr/rppg.o \ - lpwr/lpwr.o + lpwr/lpwr.o \ + gv100/clk_gv100.o diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index a5325980..cc612e07 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -217,4 +217,5 @@ srcs := os/posix/nvgpu.c \ gv100/hal_gv100.c \ gv100/pmu_gv100.c \ gv100/perf_gv100.c \ - gv100/gsp_gv100.c + gv100/gsp_gv100.c \ + gv100/clk_gv100.c diff --git a/drivers/gpu/nvgpu/gv100/clk_gv100.c b/drivers/gpu/nvgpu/gv100/clk_gv100.c new file mode 100644 index 00000000..7855aa41 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/clk_gv100.c @@ -0,0 +1,193 @@ +/* + * GV100 Clocks + * + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifdef CONFIG_DEBUG_FS +#include +#include "os/linux/os_linux.h" +#endif + +#include +#include +#include +#include +#include + +#include "gk20a/gk20a.h" + +#include "clk_gv100.h" + +#include + + +u32 gv100_crystal_clk_hz(struct gk20a *g) +{ + return (XTAL4X_KHZ * 1000); +} + +unsigned long gv100_clk_measure_freq(struct gk20a *g, u32 api_domain) +{ + struct clk_gk20a *clk = &g->clk; + u32 freq_khz; + u32 i; + struct namemap_cfg *c = NULL; + + for (i = 0; i < clk->namemap_num; i++) { + if (api_domain == clk->namemap_xlat_table[i]) { + c = &clk->clk_namemap[i]; + break; + } + } + + if (c == NULL) { + return 0; + } + if (c->is_counter != 0U) { + freq_khz = c->scale * gv100_get_rate_cntr(g, c); + } else { + freq_khz = 0U; + /* TODO: PLL read */ + } + + /* Convert to HZ */ + return freq_khz * 1000UL; +} + +int gv100_init_clk_support(struct gk20a *g) +{ + struct clk_gk20a *clk = &g->clk; + int err = 0; + + nvgpu_log_fn(g, " "); + + err = nvgpu_mutex_init(&clk->clk_mutex); + if (err != 0) { + return err; + } + + clk->clk_namemap = (struct namemap_cfg *) + nvgpu_kzalloc(g, sizeof(struct namemap_cfg) * NUM_NAMEMAPS); + + if (clk->clk_namemap == NULL) { + nvgpu_mutex_destroy(&clk->clk_mutex); + return -ENOMEM; + } + + clk->namemap_xlat_table = nvgpu_kcalloc(g, NUM_NAMEMAPS, sizeof(u32)); + + if (clk->namemap_xlat_table == NULL) { + nvgpu_kfree(g, clk->clk_namemap); + nvgpu_mutex_destroy(&clk->clk_mutex); + return -ENOMEM; + } + + clk->clk_namemap[0] = (struct namemap_cfg) { + .namemap = CLK_NAMEMAP_INDEX_GPCCLK, + .is_enable = 1, + .is_counter = 1, + .g = g, + .cntr = { + .reg_ctrl_addr = trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_r(), + .reg_ctrl_idx = trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_source_gpcclk_f(), + .reg_cntr_addr[0] = trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cnt0_r(), + .reg_cntr_addr[1] = trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cnt1_r() + }, + .name = "gpcclk", + .scale = 1 + }; + clk->namemap_xlat_table[0] = CTRL_CLK_DOMAIN_GPCCLK; + + clk->clk_namemap[1] = (struct namemap_cfg) { + .namemap = CLK_NAMEMAP_INDEX_SYSCLK, + .is_enable = 1, + .is_counter = 1, + .g = g, + .cntr = { + .reg_ctrl_addr = trim_sys_fr_clk_cntr_sysclk_cfg_r(), + .reg_ctrl_idx = trim_sys_fr_clk_cntr_sysclk_cfg_source_sysclk_f(), + .reg_cntr_addr[0] = trim_sys_fr_clk_cntr_sysclk_cntr0_r(), + .reg_cntr_addr[1] = trim_sys_fr_clk_cntr_sysclk_cntr1_r() + }, + .name = "sysclk", + .scale = 1 + }; + clk->namemap_xlat_table[1] = CTRL_CLK_DOMAIN_SYSCLK; + + clk->clk_namemap[2] = (struct namemap_cfg) { + .namemap = CLK_NAMEMAP_INDEX_XBARCLK, + .is_enable = 1, + .is_counter = 1, + .g = g, + .cntr = { + .reg_ctrl_addr = trim_sys_nafll_fr_clk_cntr_xbarclk_cfg_r(), + .reg_ctrl_idx = trim_sys_nafll_fr_clk_cntr_xbarclk_cfg_source_xbarclk_f(), + .reg_cntr_addr[0] = trim_sys_nafll_fr_clk_cntr_xbarclk_cntr0_r(), + .reg_cntr_addr[1] = trim_sys_nafll_fr_clk_cntr_xbarclk_cntr1_r() + }, + .name = "xbarclk", + .scale = 1 + }; + clk->namemap_xlat_table[2] = CTRL_CLK_DOMAIN_XBARCLK; + + clk->namemap_num = NUM_NAMEMAPS; + + clk->g = g; + + return err; +} + +u32 gv100_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) { + u32 cntr = 0; + u64 cntr_start = 0; + u64 cntr_stop = 0; + + struct clk_gk20a *clk = &g->clk; + + if ((c == NULL) || (c->cntr.reg_ctrl_addr == 0U) || + (c->cntr.reg_cntr_addr[0] == 0U) || + (c->cntr.reg_cntr_addr[1]) == 0U) { + return 0; + } + + nvgpu_mutex_acquire(&clk->clk_mutex); + + /* Read the counter values */ + /* Counter is 36bits , 32 bits on addr[0] and 4 lsb on addr[1] others zero*/ + cntr_start = (u64)gk20a_readl(g, c->cntr.reg_cntr_addr[0]); + cntr_start += ((u64)gk20a_readl(g, c->cntr.reg_cntr_addr[1]) << 32); + nvgpu_udelay(XTAL_CNTR_DELAY); + cntr_stop = (u64) gk20a_readl(g, c->cntr.reg_cntr_addr[0]); + cntr_stop += ((u64)gk20a_readl(g, c->cntr.reg_cntr_addr[1]) << 32); + /*Calculate the difference and convert to KHz*/ + cntr = (u32)((cntr_stop - cntr_start) / 10ULL); + nvgpu_mutex_release(&clk->clk_mutex); + + return cntr; + +} + +int gv100_suspend_clk_support(struct gk20a *g) +{ + nvgpu_mutex_destroy(&g->clk.clk_mutex); + return 0; +} diff --git a/drivers/gpu/nvgpu/gv100/clk_gv100.h b/drivers/gpu/nvgpu/gv100/clk_gv100.h new file mode 100644 index 00000000..d3356a7f --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/clk_gv100.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef CLK_GV100_H +#define CLK_GV100_H + +#include +#include "gk20a/gk20a.h" + +#define CLK_NAMEMAP_INDEX_GPCCLK 0x00 +#define CLK_NAMEMAP_INDEX_XBARCLK 0x02 +#define CLK_NAMEMAP_INDEX_SYSCLK 0x07 /* SYSPLL */ +#define CLK_NAMEMAP_INDEX_DRAMCLK 0x20 /* DRAMPLL */ + +#define CLK_DEFAULT_CNTRL_SETTLE_RETRIES 10 +#define CLK_DEFAULT_CNTRL_SETTLE_USECS 5 +#define CLK_MAX_CNTRL_REGISTERS 2 + +#define XTAL_CNTR_CLKS 27000 /* 1000usec at 27KHz XTAL */ +#define XTAL_CNTR_DELAY 10000 /* we need acuracy up to the 10ms */ +#define XTAL_SCALE_TO_KHZ 1 +#define NUM_NAMEMAPS (3U) +#define XTAL4X_KHZ 108000 + +u32 gv100_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c); +struct namemap_cfg { + u32 namemap; + u32 is_enable; /* Namemap enabled */ + u32 is_counter; /* Using cntr */ + struct gk20a *g; + struct { + u32 reg_ctrl_addr; + u32 reg_ctrl_idx; + u32 reg_cntr_addr[CLK_MAX_CNTRL_REGISTERS]; + } cntr; + u32 scale; + char name[24]; +}; + +int gv100_init_clk_support(struct gk20a *g); +u32 gv100_crystal_clk_hz(struct gk20a *g); +unsigned long gv100_clk_measure_freq(struct gk20a *g, u32 api_domain); +int gv100_suspend_clk_support(struct gk20a *g); + +#endif /* CLK_GV100_H */ diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 041422e0..7cd466c3 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -66,13 +66,11 @@ #include "gm20b/pmu_gm20b.h" #include "gm20b/acr_gm20b.h" -#include "gp106/clk_gp106.h" #include "gp106/clk_arb_gp106.h" #include "gp106/pmu_gp106.h" #include "gp106/acr_gp106.h" #include "gp106/sec2_gp106.h" #include "gp106/bios_gp106.h" -#include "gp106/clk_gp106.h" #include "gp106/flcn_gp106.h" #include "gp10b/gr_gp10b.h" @@ -107,6 +105,7 @@ #include "gv100/nvlink_gv100.h" #include "gv100/regops_gv100.h" #include "gv100/perf_gv100.h" +#include "gv100/clk_gv100.h" #include #include @@ -768,11 +767,11 @@ static const struct gpu_ops gv100_ops = { .secured_pmu_start = gm20b_secured_pmu_start, }, .clk = { - .init_clk_support = gp106_init_clk_support, - .get_crystal_clk_hz = gp106_crystal_clk_hz, - .get_rate_cntr = gp106_get_rate_cntr, - .measure_freq = gp106_clk_measure_freq, - .suspend_clk_support = gp106_suspend_clk_support, + .init_clk_support = gv100_init_clk_support, + .get_crystal_clk_hz = gv100_crystal_clk_hz, + .get_rate_cntr = gv100_get_rate_cntr, + .measure_freq = gv100_clk_measure_freq, + .suspend_clk_support = gv100_suspend_clk_support, .perf_pmu_vfe_load = gv100_perf_pmu_vfe_load, }, .clk_arb = { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h index 9e7ceaff..f1b6da28 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h @@ -196,4 +196,52 @@ static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_onesrcclk_f(void) { return 0x3U; } +static inline u32 trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_r(void) +{ + return 0x00132a70U; +} +static inline u32 trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_source_gpcclk_f(void) +{ + return 0x10000000U; +} +static inline u32 trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cnt0_r(void) +{ + return 0x00132a74U; +} +static inline u32 trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cnt1_r(void) +{ + return 0x00132a78U; +} +static inline u32 trim_sys_nafll_fr_clk_cntr_xbarclk_cfg_r(void) +{ + return 0x00136470U; +} +static inline u32 trim_sys_nafll_fr_clk_cntr_xbarclk_cfg_source_xbarclk_f(void) +{ + return 0x10000000U; +} +static inline u32 trim_sys_nafll_fr_clk_cntr_xbarclk_cntr0_r(void) +{ + return 0x00136474U; +} +static inline u32 trim_sys_nafll_fr_clk_cntr_xbarclk_cntr1_r(void) +{ + return 0x00136478U; +} +static inline u32 trim_sys_fr_clk_cntr_sysclk_cfg_r(void) +{ + return 0x0013762cU; +} +static inline u32 trim_sys_fr_clk_cntr_sysclk_cfg_source_sysclk_f(void) +{ + return 0x20000000U; +} +static inline u32 trim_sys_fr_clk_cntr_sysclk_cntr0_r(void) +{ + return 0x00137630U; +} +static inline u32 trim_sys_fr_clk_cntr_sysclk_cntr1_r(void) +{ + return 0x00137634U; +} #endif diff --git a/drivers/gpu/nvgpu/os/linux/debug_clk_gv100.c b/drivers/gpu/nvgpu/os/linux/debug_clk_gv100.c new file mode 100644 index 00000000..623f2b6b --- /dev/null +++ b/drivers/gpu/nvgpu/os/linux/debug_clk_gv100.c @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2018, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +#include "gv100/clk_gv100.h" + +#include "os_linux.h" + +void nvgpu_clk_arb_pstate_change_lock(struct gk20a *g, bool lock); + +static int gv100_get_rate_show(void *data , u64 *val) +{ + struct namemap_cfg *c = (struct namemap_cfg *)data; + struct gk20a *g = c->g; + + if (!g->ops.clk.get_rate_cntr) + return -EINVAL; + + *val = c->is_counter ? (u64)c->scale * g->ops.clk.get_rate_cntr(g, c) : + 0 /* TODO PLL read */; + + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(get_rate_fops, gv100_get_rate_show, NULL, "%llu\n"); + +static int sys_cfc_read(void *data , u64 *val) +{ + struct gk20a *g = (struct gk20a *)data; + bool bload = boardobjgrpmask_bitget( + &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super, + CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS); + + /* val = 1 implies CLFC is loaded or enabled */ + *val = bload ? 1 : 0; + return 0; +} +static int sys_cfc_write(void *data , u64 val) +{ + struct gk20a *g = (struct gk20a *)data; + int status; + /* val = 1 implies load or enable the CLFC */ + bool bload = val ? true : false; + + nvgpu_clk_arb_pstate_change_lock(g, true); + status = clk_pmu_freq_controller_load(g, bload, + CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS); + nvgpu_clk_arb_pstate_change_lock(g, false); + + return status; +} +DEFINE_SIMPLE_ATTRIBUTE(sys_cfc_fops, sys_cfc_read, sys_cfc_write, "%llu\n"); + +static int ltc_cfc_read(void *data , u64 *val) +{ + struct gk20a *g = (struct gk20a *)data; + bool bload = boardobjgrpmask_bitget( + &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super, + CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC); + + /* val = 1 implies CLFC is loaded or enabled */ + *val = bload ? 1 : 0; + return 0; +} +static int ltc_cfc_write(void *data , u64 val) +{ + struct gk20a *g = (struct gk20a *)data; + int status; + /* val = 1 implies load or enable the CLFC */ + bool bload = val ? true : false; + + nvgpu_clk_arb_pstate_change_lock(g, true); + status = clk_pmu_freq_controller_load(g, bload, + CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC); + nvgpu_clk_arb_pstate_change_lock(g, false); + + return status; +} +DEFINE_SIMPLE_ATTRIBUTE(ltc_cfc_fops, ltc_cfc_read, ltc_cfc_write, "%llu\n"); + +static int xbar_cfc_read(void *data , u64 *val) +{ + struct gk20a *g = (struct gk20a *)data; + bool bload = boardobjgrpmask_bitget( + &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super, + CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR); + + /* val = 1 implies CLFC is loaded or enabled */ + *val = bload ? 1 : 0; + return 0; +} +static int xbar_cfc_write(void *data , u64 val) +{ + struct gk20a *g = (struct gk20a *)data; + int status; + /* val = 1 implies load or enable the CLFC */ + bool bload = val ? true : false; + + nvgpu_clk_arb_pstate_change_lock(g, true); + status = clk_pmu_freq_controller_load(g, bload, + CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR); + nvgpu_clk_arb_pstate_change_lock(g, false); + + return status; +} +DEFINE_SIMPLE_ATTRIBUTE(xbar_cfc_fops, xbar_cfc_read, + xbar_cfc_write, "%llu\n"); + +static int gpc_cfc_read(void *data , u64 *val) +{ + struct gk20a *g = (struct gk20a *)data; + bool bload = boardobjgrpmask_bitget( + &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super, + CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0); + + /* val = 1 implies CLFC is loaded or enabled */ + *val = bload ? 1 : 0; + return 0; +} +static int gpc_cfc_write(void *data , u64 val) +{ + struct gk20a *g = (struct gk20a *)data; + int status; + /* val = 1 implies load or enable the CLFC */ + bool bload = val ? true : false; + + nvgpu_clk_arb_pstate_change_lock(g, true); + status = clk_pmu_freq_controller_load(g, bload, + CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0); + nvgpu_clk_arb_pstate_change_lock(g, false); + + return status; +} +DEFINE_SIMPLE_ATTRIBUTE(gpc_cfc_fops, gpc_cfc_read, gpc_cfc_write, "%llu\n"); + +int gv100_clk_init_debugfs(struct gk20a *g) +{ + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + struct dentry *gpu_root = l->debugfs; + struct dentry *clocks_root, *clk_freq_ctlr_root; + struct dentry *d; + unsigned int i; + + if (NULL == (clocks_root = debugfs_create_dir("clocks", gpu_root))) + return -ENOMEM; + + clk_freq_ctlr_root = debugfs_create_dir("clk_freq_ctlr", gpu_root); + if (clk_freq_ctlr_root == NULL) + return -ENOMEM; + + d = debugfs_create_file("sys", S_IRUGO | S_IWUSR, clk_freq_ctlr_root, + g, &sys_cfc_fops); + d = debugfs_create_file("ltc", S_IRUGO | S_IWUSR, clk_freq_ctlr_root, + g, <c_cfc_fops); + d = debugfs_create_file("xbar", S_IRUGO | S_IWUSR, clk_freq_ctlr_root, + g, &xbar_cfc_fops); + d = debugfs_create_file("gpc", S_IRUGO | S_IWUSR, clk_freq_ctlr_root, + g, &gpc_cfc_fops); + + nvgpu_log(g, gpu_dbg_info, "g=%p", g); + + for (i = 0; i < g->clk.namemap_num; i++) { + if (g->clk.clk_namemap[i].is_enable) { + d = debugfs_create_file( + g->clk.clk_namemap[i].name, + S_IRUGO, + clocks_root, + &g->clk.clk_namemap[i], + &get_rate_fops); + if (!d) + goto err_out; + } + } + return 0; + +err_out: + pr_err("%s: Failed to make debugfs node\n", __func__); + debugfs_remove_recursive(clocks_root); + return -ENOMEM; +} diff --git a/drivers/gpu/nvgpu/os/linux/debug_clk_gv100.h b/drivers/gpu/nvgpu/os/linux/debug_clk_gv100.h new file mode 100644 index 00000000..38ba61bd --- /dev/null +++ b/drivers/gpu/nvgpu/os/linux/debug_clk_gv100.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2018, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __DEBUG_CLK_GV100_H +#define __DEBUG_CLK_GV100_H + +#ifdef CONFIG_DEBUG_FS +int gv100_clk_init_debugfs(struct gk20a *g); +#else +inline int gv100_clk_init_debugfs(struct gk20a *g) +{ + return 0; +} +#endif + +#endif diff --git a/drivers/gpu/nvgpu/os/linux/os_ops_gv100.c b/drivers/gpu/nvgpu/os/linux/os_ops_gv100.c index f5c5a604..9d92bdfb 100644 --- a/drivers/gpu/nvgpu/os/linux/os_ops_gv100.c +++ b/drivers/gpu/nvgpu/os/linux/os_ops_gv100.c @@ -16,13 +16,13 @@ #include "os_linux.h" -#include "debug_clk_gp106.h" +#include "debug_clk_gv100.h" #include "debug_therm_gp106.h" #include "debug_fecs_trace.h" static struct nvgpu_os_linux_ops gv100_os_linux_ops = { .clk = { - .init_debugfs = gp106_clk_init_debugfs, + .init_debugfs = gv100_clk_init_debugfs, }, .therm = { .init_debugfs = gp106_therm_init_debugfs, -- cgit v1.2.2