From 7d584bf868e53638f5c05b588dcd307e71cf9c82 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Tue, 27 Jun 2017 11:20:58 -0700 Subject: gpu: nvgpu: rename hw_chid to chid hw_chid is a relative id for vgpu. For native it's same as hw id. Renaming it to chid to avoid confusing. Jira VFND-3796 Change-Id: I1c7924da1757330ace715a7c52ac61ec9dc7065c Signed-off-by: Richard Zhao Reviewed-on: https://git-master/r/1509530 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/linux/debug_fifo.c | 4 +- drivers/gpu/nvgpu/common/linux/ioctl_channel.c | 14 +-- drivers/gpu/nvgpu/common/semaphore.c | 2 +- drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 54 ++++++------ drivers/gpu/nvgpu/gk20a/channel_gk20a.h | 2 +- drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c | 12 +-- drivers/gpu/nvgpu/gk20a/ctxsw_trace_gk20a.c | 2 +- drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c | 8 +- drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c | 4 +- drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 116 ++++++++++++------------- drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 16 ++-- drivers/gpu/nvgpu/gk20a/gk20a.h | 6 +- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 22 ++--- drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 2 +- drivers/gpu/nvgpu/gk20a/mm_gk20a.h | 2 +- drivers/gpu/nvgpu/gk20a/sync_gk20a.c | 2 +- drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | 4 +- drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 8 +- drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | 6 +- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 16 ++-- drivers/gpu/nvgpu/include/nvgpu/semaphore.h | 4 +- drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 32 +++---- drivers/gpu/nvgpu/vgpu/tsg_vgpu.c | 2 +- 23 files changed, 170 insertions(+), 170 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/common/linux/debug_fifo.c b/drivers/gpu/nvgpu/common/linux/debug_fifo.c index 6a28b1a5..04937dbe 100644 --- a/drivers/gpu/nvgpu/common/linux/debug_fifo.c +++ b/drivers/gpu/nvgpu/common/linux/debug_fifo.c @@ -77,7 +77,7 @@ static int gk20a_fifo_sched_debugfs_seq_show( ret = 0; } - if (!test_bit(ch->hw_chid, runlist->active_channels)) + if (!test_bit(ch->chid, runlist->active_channels)) return ret; if (gk20a_channel_get(ch)) { @@ -85,7 +85,7 @@ static int gk20a_fifo_sched_debugfs_seq_show( tsg = &f->tsg[ch->tsgid]; seq_printf(s, "%-8d %-8d %-8d %-9d %-8d %-10d %-8d %-8d\n", - ch->hw_chid, + ch->chid, ch->tsgid, ch->tgid, tsg ? tsg->timeslice_us : ch->timeslice_us, diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c index 2466db40..5905e5a6 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c @@ -42,7 +42,7 @@ static void gk20a_channel_trace_sched_param( const char *compute_preempt_mode), struct channel_gk20a *ch) { - (trace)(ch->hw_chid, ch->tsgid, ch->pid, + (trace)(ch->chid, ch->tsgid, ch->pid, gk20a_is_channel_marked_as_tsg(ch) ? tsg_gk20a_from_ch(ch)->timeslice_us : ch->timeslice_us, ch->timeout_ms_max, @@ -525,7 +525,7 @@ static int gk20a_channel_wait(struct channel_gk20a *ch, notif->timestamp.nanoseconds[0] = tv.tv_nsec; notif->timestamp.nanoseconds[1] = tv.tv_sec; notif->info32 = 0xDEADBEEF; /* should be object name */ - notif->info16 = ch->hw_chid; /* should be method offset */ + notif->info16 = ch->chid; /* should be method offset */ notif_clean_up: dma_buf_vunmap(dmabuf, notif); @@ -578,7 +578,7 @@ static unsigned int gk20a_event_id_poll(struct file *filep, poll_table *wait) if (event_id_data->event_posted) { gk20a_dbg_info( "found pending event_id=%d on chid=%d\n", - event_id, ch->hw_chid); + event_id, ch->chid); mask = (POLLPRI | POLLIN); event_id_data->event_posted = false; } @@ -662,7 +662,7 @@ void gk20a_channel_event_id_post_event(struct channel_gk20a *ch, gk20a_dbg_info( "posting event for event_id=%d on ch=%d\n", - event_id, ch->hw_chid); + event_id, ch->chid); event_id_data->event_posted = true; wake_up_interruptible_all(&event_id_data->event_id_wq); @@ -713,7 +713,7 @@ static int gk20a_channel_event_id_enable(struct channel_gk20a *ch, goto clean_up_file; } event_id_data->g = g; - event_id_data->id = ch->hw_chid; + event_id_data->id = ch->chid; event_id_data->is_tsg = false; event_id_data->event_id = event_id; @@ -1006,7 +1006,7 @@ long gk20a_channel_ioctl(struct file *filp, u32 timeout = (u32)((struct nvgpu_set_timeout_args *)buf)->timeout; gk20a_dbg(gpu_dbg_gpu_dbg, "setting timeout (%d ms) for chid %d", - timeout, ch->hw_chid); + timeout, ch->chid); ch->timeout_ms_max = timeout; gk20a_channel_trace_sched_param( trace_gk20a_channel_set_timeout, ch); @@ -1020,7 +1020,7 @@ long gk20a_channel_ioctl(struct file *filp, ((struct nvgpu_set_timeout_ex_args *)buf)->flags & (1 << NVGPU_TIMEOUT_FLAG_DISABLE_DUMP)); gk20a_dbg(gpu_dbg_gpu_dbg, "setting timeout (%d ms) for chid %d", - timeout, ch->hw_chid); + timeout, ch->chid); ch->timeout_ms_max = timeout; ch->timeout_debug_dump = timeout_debug_dump; gk20a_channel_trace_sched_param( diff --git a/drivers/gpu/nvgpu/common/semaphore.c b/drivers/gpu/nvgpu/common/semaphore.c index a54ce831..3e916b9d 100644 --- a/drivers/gpu/nvgpu/common/semaphore.c +++ b/drivers/gpu/nvgpu/common/semaphore.c @@ -433,7 +433,7 @@ struct nvgpu_semaphore *nvgpu_semaphore_alloc(struct channel_gk20a *ch) */ nvgpu_semaphore_pool_get(s->hw_sema->p); - gpu_sema_dbg(ch->g, "Allocated semaphore (c=%d)", ch->hw_chid); + gpu_sema_dbg(ch->g, "Allocated semaphore (c=%d)", ch->chid); return s; } diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index ef9ad731..bca201cf 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c @@ -118,7 +118,7 @@ static void free_channel(struct fifo_gk20a *f, { struct gk20a *g = f->g; - trace_gk20a_release_used_channel(ch->hw_chid); + trace_gk20a_release_used_channel(ch->chid); /* refcount is zero here and channel is in a freed/dead state */ nvgpu_mutex_acquire(&f->free_chs_mutex); /* add to head to increase visibility of timing-related bugs */ @@ -189,7 +189,7 @@ int gk20a_channel_get_timescale_from_timeslice(struct gk20a *g, static int channel_gk20a_update_runlist(struct channel_gk20a *c, bool add) { - return c->g->ops.fifo.update_runlist(c->g, c->runlist_id, c->hw_chid, add, true); + return c->g->ops.fifo.update_runlist(c->g, c->runlist_id, c->chid, add, true); } int gk20a_enable_channel_tsg(struct gk20a *g, struct channel_gk20a *ch) @@ -295,7 +295,7 @@ void gk20a_channel_abort(struct channel_gk20a *ch, bool channel_preempt) ch->g->ops.fifo.disable_channel(ch); if (channel_preempt && ch->ch_ctx.gr_ctx) - ch->g->ops.fifo.preempt_channel(ch->g, ch->hw_chid); + ch->g->ops.fifo.preempt_channel(ch->g, ch->chid); gk20a_channel_abort_clean_up(ch); } @@ -320,7 +320,7 @@ int gk20a_wait_channel_idle(struct channel_gk20a *ch) if (!channel_idle) { nvgpu_err(ch->g, "jobs not freed for channel %d", - ch->hw_chid); + ch->chid); return -EBUSY; } @@ -348,7 +348,7 @@ int gk20a_channel_set_runlist_interleave(struct channel_gk20a *ch, case NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW: case NVGPU_RUNLIST_INTERLEAVE_LEVEL_MEDIUM: case NVGPU_RUNLIST_INTERLEAVE_LEVEL_HIGH: - ret = g->ops.fifo.set_runlist_interleave(g, ch->hw_chid, + ret = g->ops.fifo.set_runlist_interleave(g, ch->chid, false, 0, level); break; default: @@ -356,7 +356,7 @@ int gk20a_channel_set_runlist_interleave(struct channel_gk20a *ch, break; } - gk20a_dbg(gpu_dbg_sched, "chid=%u interleave=%u", ch->hw_chid, level); + gk20a_dbg(gpu_dbg_sched, "chid=%u interleave=%u", ch->chid, level); return ret ? ret : g->ops.fifo.update_runlist(g, ch->runlist_id, ~0, true, true); } @@ -381,7 +381,7 @@ void gk20a_set_error_notifier_locked(struct channel_gk20a *ch, __u32 error) ch->error_notifier->status = 0xffff; nvgpu_err(ch->g, - "error notifier set to %d for ch %d", error, ch->hw_chid); + "error notifier set to %d for ch %d", error, ch->chid); } } @@ -405,7 +405,7 @@ static void gk20a_wait_until_counter_is_N( nvgpu_warn(ch->g, "%s: channel %d, still waiting, %s left: %d, waiting for: %d", - caller, ch->hw_chid, counter_name, + caller, ch->chid, counter_name, atomic_read(counter), wait_value); gk20a_channel_dump_ref_actions(ch); @@ -462,7 +462,7 @@ static void gk20a_free_channel(struct channel_gk20a *ch, bool force) WARN_ON(ch->g == NULL); - trace_gk20a_free_channel(ch->hw_chid); + trace_gk20a_free_channel(ch->chid); /* abort channel and remove from runlist */ gk20a_disable_channel(ch); @@ -483,7 +483,7 @@ static void gk20a_free_channel(struct channel_gk20a *ch, bool force) nvgpu_spinlock_release(&ch->ref_obtain_lock); nvgpu_err(ch->g, "Extra %s() called to channel %u", - __func__, ch->hw_chid); + __func__, ch->chid); return; } ch->referenceable = false; @@ -597,7 +597,7 @@ unbind: nvgpu_mutex_acquire(&dbg_s->ch_list_lock); list_for_each_entry_safe(ch_data, tmp, &dbg_s->ch_list, ch_entry) { - if (ch_data->chid == ch->hw_chid) + if (ch_data->chid == ch->chid) dbg_unbind_single_channel_gk20a(dbg_s, ch_data); } nvgpu_mutex_release(&dbg_s->ch_list_lock); @@ -634,7 +634,7 @@ static void gk20a_channel_dump_ref_actions(struct channel_gk20a *ch) nvgpu_spinlock_acquire(&ch->ref_actions_lock); dev_info(dev, "ch %d: refs %d. Actions, most recent last:\n", - ch->hw_chid, atomic_read(&ch->ref_count)); + ch->chid, atomic_read(&ch->ref_count)); /* start at the oldest possible entry. put is next insertion point */ get = ch->ref_actions_put; @@ -695,7 +695,7 @@ static void gk20a_channel_save_ref_source(struct channel_gk20a *ch, * reference must be held to it - either by you or the caller, which should be * documented well or otherwise clearly seen. This usually boils down to the * file from ioctls directly, or an explicit get in exception handlers when the - * channel is found by a hw_chid. + * channel is found by a chid. * * Most global functions in this file require a reference to be held by the * caller. @@ -716,7 +716,7 @@ struct channel_gk20a *_gk20a_channel_get(struct channel_gk20a *ch, nvgpu_spinlock_release(&ch->ref_obtain_lock); if (ret) - trace_gk20a_channel_get(ch->hw_chid, caller); + trace_gk20a_channel_get(ch->chid, caller); return ret; } @@ -724,7 +724,7 @@ struct channel_gk20a *_gk20a_channel_get(struct channel_gk20a *ch, void _gk20a_channel_put(struct channel_gk20a *ch, const char *caller) { gk20a_channel_save_ref_source(ch, channel_gk20a_ref_action_put); - trace_gk20a_channel_put(ch->hw_chid, caller); + trace_gk20a_channel_put(ch->chid, caller); atomic_dec(&ch->ref_count); nvgpu_cond_broadcast(&ch->ref_count_dec_wq); @@ -809,7 +809,7 @@ struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g, return NULL; } - trace_gk20a_open_new_channel(ch->hw_chid); + trace_gk20a_open_new_channel(ch->chid); BUG_ON(ch->g); ch->g = g; @@ -951,7 +951,7 @@ int gk20a_channel_alloc_priv_cmdbuf(struct channel_gk20a *c, u32 orig_size, if (!e) { nvgpu_err(c->g, "ch %d: priv cmd entry is null", - c->hw_chid); + c->chid); return -EINVAL; } @@ -961,7 +961,7 @@ int gk20a_channel_alloc_priv_cmdbuf(struct channel_gk20a *c, u32 orig_size, size = orig_size + (q->size - q->put); gk20a_dbg_info("ch %d: priv cmd queue get:put %d:%d", - c->hw_chid, q->get, q->put); + c->chid, q->get, q->put); free_count = (q->size - (q->put - q->get) - 1) % q->size; @@ -1268,7 +1268,7 @@ int gk20a_channel_alloc_gpfifo(struct channel_gk20a *c, if (c->gpfifo.mem.size) { nvgpu_err(g, "channel %d :" - "gpfifo already allocated", c->hw_chid); + "gpfifo already allocated", c->chid); err = -EEXIST; goto clean_up_idle; } @@ -1294,7 +1294,7 @@ int gk20a_channel_alloc_gpfifo(struct channel_gk20a *c, c->gpfifo.get = c->gpfifo.put = 0; gk20a_dbg_info("channel %d : gpfifo_base 0x%016llx, size %d", - c->hw_chid, c->gpfifo.mem.gpu_va, c->gpfifo.entry_num); + c->chid, c->gpfifo.mem.gpu_va, c->gpfifo.entry_num); g->ops.fifo.setup_userd(c); @@ -1653,7 +1653,7 @@ static void gk20a_channel_timeout_handler(struct channel_gk20a *ch) } nvgpu_err(g, "Job on channel %d timed out", - ch->hw_chid); + ch->chid); gk20a_debug_dump(g); gk20a_gr_debug_dump(g); @@ -1934,7 +1934,7 @@ int gk20a_free_priv_cmdbuf(struct channel_gk20a *c, struct priv_cmd_entry *e) rmb(); if ((q->get != e->off) && e->off != 0) nvgpu_err(g, "requests out-of-order, ch=%d", - c->hw_chid); + c->chid); q->get = e->off + e->size; } @@ -2161,7 +2161,7 @@ void gk20a_channel_update(struct channel_gk20a *c) return; } - trace_gk20a_channel_update(c->hw_chid); + trace_gk20a_channel_update(c->chid); /* A queued channel is always checked for job cleanup. */ gk20a_channel_worker_enqueue(c); } @@ -2492,7 +2492,7 @@ int gk20a_submit_channel_gpfifo(struct channel_gk20a *c, g->ops.ltc.sync_debugfs(g); #endif - gk20a_dbg_info("channel %d", c->hw_chid); + gk20a_dbg_info("channel %d", c->chid); /* * Job tracking is necessary for any of the following conditions: @@ -2585,7 +2585,7 @@ int gk20a_submit_channel_gpfifo(struct channel_gk20a *c, down_read(&g->deterministic_busy); trace_gk20a_channel_submit_gpfifo(g->name, - c->hw_chid, + c->chid, num_entries, flags, fence ? fence->id : 0, @@ -2661,7 +2661,7 @@ int gk20a_submit_channel_gpfifo(struct channel_gk20a *c, up_read(&g->deterministic_busy); trace_gk20a_channel_submitted_gpfifo(g->name, - c->hw_chid, + c->chid, num_entries, flags, post_fence ? post_fence->syncpt_id : 0, @@ -2771,7 +2771,7 @@ int gk20a_init_channel_support(struct gk20a *g, u32 chid) int err; c->g = NULL; - c->hw_chid = chid; + c->chid = chid; atomic_set(&c->bound, false); nvgpu_spinlock_init(&c->ref_obtain_lock); atomic_set(&c->ref_count, 0); diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h index 8cf00e7c..380440b9 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h @@ -185,7 +185,7 @@ struct channel_gk20a { struct nvgpu_semaphore_int *hw_sema; - int hw_chid; + int chid; bool wdt_enabled; atomic_t bound; bool first_init; diff --git a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c index 1b650cdd..c9c03d37 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c @@ -331,10 +331,10 @@ gk20a_channel_syncpt_create(struct channel_gk20a *c) sp->nvhost_dev = c->g->nvhost_dev; snprintf(syncpt_name, sizeof(syncpt_name), - "%s_%d", c->g->name, c->hw_chid); + "%s_%d", c->g->name, c->chid); sp->id = nvgpu_nvhost_get_syncpt_host_managed(sp->nvhost_dev, - c->hw_chid, syncpt_name); + c->chid, syncpt_name); if (!sp->id) { nvgpu_kfree(c->g, sp); nvgpu_err(c->g, "failed to get free syncpt"); @@ -497,7 +497,7 @@ static void add_sema_cmd(struct gk20a *g, struct channel_gk20a *c, struct nvgpu_semaphore *s, struct priv_cmd_entry *cmd, int cmd_size, bool acquire, bool wfi) { - int ch = c->hw_chid; + int ch = c->chid; u32 ob, off = cmd->off; u64 va; @@ -557,7 +557,7 @@ static void add_sema_cmd(struct gk20a *g, struct channel_gk20a *c, gpu_sema_verbose_dbg(g, "(A) c=%d ACQ_GE %-4u owner=%-3d" "va=0x%llx cmd_mem=0x%llx b=0x%llx off=%u", ch, nvgpu_semaphore_get_value(s), - s->hw_sema->ch->hw_chid, va, cmd->gva, + s->hw_sema->ch->chid, va, cmd->gva, cmd->mem->gpu_va, ob); else gpu_sema_verbose_dbg(g, "(R) c=%d INCR %u (%u) va=0x%llx " @@ -911,12 +911,12 @@ gk20a_channel_semaphore_create(struct channel_gk20a *c) if (c->vm->as_share) asid = c->vm->as_share->id; - sprintf(pool_name, "semaphore_pool-%d", c->hw_chid); + sprintf(pool_name, "semaphore_pool-%d", c->chid); sema->pool = c->vm->sema_pool; #ifdef CONFIG_SYNC sema->timeline = gk20a_sync_timeline_create( - "gk20a_ch%d_as%d", c->hw_chid, asid); + "gk20a_ch%d_as%d", c->chid, asid); if (!sema->timeline) { gk20a_channel_semaphore_destroy(&sema->ops); return NULL; diff --git a/drivers/gpu/nvgpu/gk20a/ctxsw_trace_gk20a.c b/drivers/gpu/nvgpu/gk20a/ctxsw_trace_gk20a.c index c189a00c..f3866d6a 100644 --- a/drivers/gpu/nvgpu/gk20a/ctxsw_trace_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ctxsw_trace_gk20a.c @@ -693,7 +693,7 @@ void gk20a_ctxsw_trace_channel_reset(struct gk20a *g, struct channel_gk20a *ch) gk20a_ctxsw_trace_write(g, &entry); gk20a_ctxsw_trace_wake_up(g, 0); #endif - trace_gk20a_channel_reset(ch->hw_chid, ch->tsgid); + trace_gk20a_channel_reset(ch->chid, ch->tsgid); } void gk20a_ctxsw_trace_tsg_reset(struct gk20a *g, struct tsg_gk20a *tsg) diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c index 9b0d9456..c7552f04 100644 --- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c @@ -445,7 +445,7 @@ int dbg_unbind_single_channel_gk20a(struct dbg_session_gk20a *dbg_s, nvgpu_list_for_each_entry_safe(prof_obj, tmp_obj, &g->profiler_objects, dbg_profiler_object_data, prof_obj_entry) { if ((prof_obj->session_id == dbg_s->id) && - (prof_obj->ch->hw_chid == chid)) { + (prof_obj->ch->chid == chid)) { if (prof_obj->has_reservation) { g->ops.dbg_session_ops. release_profiler_reservation(dbg_s, prof_obj); @@ -504,7 +504,7 @@ static int dbg_unbind_channel_gk20a(struct dbg_session_gk20a *dbg_s, nvgpu_mutex_acquire(&dbg_s->ch_list_lock); nvgpu_list_for_each_entry(ch_data, &dbg_s->ch_list, dbg_session_channel_data, ch_entry) { - if (ch->hw_chid == ch_data->chid) { + if (ch->chid == ch_data->chid) { channel_found = true; break; } @@ -601,7 +601,7 @@ static int dbg_bind_channel_gk20a(struct dbg_session_gk20a *dbg_s, return -EINVAL; } - gk20a_dbg_fn("%s hwchid=%d", g->name, ch->hw_chid); + gk20a_dbg_fn("%s hwchid=%d", g->name, ch->chid); nvgpu_mutex_acquire(&g->dbg_sessions_lock); nvgpu_mutex_acquire(&ch->dbg_s_lock); @@ -613,7 +613,7 @@ static int dbg_bind_channel_gk20a(struct dbg_session_gk20a *dbg_s, } ch_data->ch_f = f; ch_data->channel_fd = args->channel_fd; - ch_data->chid = ch->hw_chid; + ch_data->chid = ch->chid; nvgpu_init_list_node(&ch_data->ch_entry); session_data = nvgpu_kzalloc(g, sizeof(*session_data)); diff --git a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c index 4589b83e..4235788b 100644 --- a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c @@ -628,8 +628,8 @@ static int gk20a_fecs_trace_bind_channel(struct gk20a *g, u32 aperture; gk20a_dbg(gpu_dbg_fn|gpu_dbg_ctxsw, - "hw_chid=%d context_ptr=%x inst_block=%llx", - ch->hw_chid, context_ptr, + "chid=%d context_ptr=%x inst_block=%llx", + ch->chid, context_ptr, gk20a_mm_inst_block_addr(g, &ch->inst_block)); if (!trace) diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 69a3e706..17f3743f 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -46,7 +46,7 @@ #define FECS_METHOD_WFI_RESTORE 0x80000 static int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id, - u32 hw_chid, bool add, + u32 chid, bool add, bool wait_for_finish); static u32 gk20a_fifo_engines_on_id(struct gk20a *g, u32 id, bool is_tsg); @@ -1395,7 +1395,7 @@ void gk20a_fifo_set_ctx_mmu_error_ch(struct gk20a *g, struct channel_gk20a *refch) { nvgpu_err(g, - "channel %d generated a mmu fault", refch->hw_chid); + "channel %d generated a mmu fault", refch->chid); gk20a_set_error_notifier(refch, NVGPU_CHANNEL_FIFO_ERROR_MMU_ERR_FLT); } @@ -1455,7 +1455,7 @@ int gk20a_fifo_deferred_reset(struct gk20a *g, struct channel_gk20a *ch) if (gk20a_is_channel_marked_as_tsg(ch)) engines = gk20a_fifo_engines_on_id(g, ch->tsgid, true); else - engines = gk20a_fifo_engines_on_id(g, ch->hw_chid, false); + engines = gk20a_fifo_engines_on_id(g, ch->chid, false); if (!engines) goto clean_up; @@ -1673,7 +1673,7 @@ static bool gk20a_fifo_handle_mmu_fault( } else { nvgpu_err(g, "mmu error in freed channel %d", - ch->hw_chid); + ch->chid); } } else if (mmfault_info.inst_ptr == gk20a_mm_inst_block_addr(g, &g->mm.bar1.inst_block)) { @@ -1794,7 +1794,7 @@ static u32 gk20a_fifo_engines_on_id(struct gk20a *g, u32 id, bool is_tsg) return engines; } -void gk20a_fifo_recover_ch(struct gk20a *g, u32 hw_chid, bool verbose) +void gk20a_fifo_recover_ch(struct gk20a *g, u32 chid, bool verbose) { u32 engines; @@ -1803,12 +1803,12 @@ void gk20a_fifo_recover_ch(struct gk20a *g, u32 hw_chid, bool verbose) nvgpu_mutex_acquire(&g->dbg_sessions_lock); gr_gk20a_disable_ctxsw(g); - engines = gk20a_fifo_engines_on_id(g, hw_chid, false); + engines = gk20a_fifo_engines_on_id(g, chid, false); if (engines) - gk20a_fifo_recover(g, engines, hw_chid, false, true, verbose); + gk20a_fifo_recover(g, engines, chid, false, true, verbose); else { - struct channel_gk20a *ch = &g->fifo.channel[hw_chid]; + struct channel_gk20a *ch = &g->fifo.channel[chid]; if (gk20a_channel_get(ch)) { gk20a_channel_abort(ch, false); @@ -1976,7 +1976,7 @@ int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch, gk20a_fifo_recover_tsg(g, ch->tsgid, verbose); } else { gk20a_set_error_notifier(ch, err_code); - gk20a_fifo_recover_ch(g, ch->hw_chid, verbose); + gk20a_fifo_recover_ch(g, ch->chid, verbose); } return 0; @@ -2102,7 +2102,7 @@ bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg, */ if (progress) { gk20a_dbg_info("progress on tsg=%d ch=%d", - tsg->tsgid, ch->hw_chid); + tsg->tsgid, ch->chid); gk20a_channel_put(ch); *ms = GRFIFO_TIMEOUT_CHECK_PERIOD_US / 1000; list_for_each_entry(ch, &tsg->ch_list, ch_entry) { @@ -2119,7 +2119,7 @@ bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg, */ if (recover) { gk20a_dbg_info("timeout on tsg=%d ch=%d", - tsg->tsgid, ch->hw_chid); + tsg->tsgid, ch->chid); *ms = ch->timeout_accumulated_ms; gk20a_channel_put(ch); list_for_each_entry(ch, &tsg->ch_list, ch_entry) { @@ -2629,7 +2629,7 @@ int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg) return ret; } -int gk20a_fifo_preempt_channel(struct gk20a *g, u32 hw_chid) +int gk20a_fifo_preempt_channel(struct gk20a *g, u32 chid) { struct fifo_gk20a *f = &g->fifo; u32 ret = 0; @@ -2637,7 +2637,7 @@ int gk20a_fifo_preempt_channel(struct gk20a *g, u32 hw_chid) u32 mutex_ret = 0; u32 i; - gk20a_dbg_fn("%d", hw_chid); + gk20a_dbg_fn("%d", chid); /* we have no idea which runlist we are using. lock all */ for (i = 0; i < g->fifo.max_runlists; i++) @@ -2645,7 +2645,7 @@ int gk20a_fifo_preempt_channel(struct gk20a *g, u32 hw_chid) mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); - ret = __locked_fifo_preempt(g, hw_chid, false); + ret = __locked_fifo_preempt(g, chid, false); if (!mutex_ret) nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); @@ -2690,7 +2690,7 @@ int gk20a_fifo_preempt(struct gk20a *g, struct channel_gk20a *ch) if (gk20a_is_channel_marked_as_tsg(ch)) err = g->ops.fifo.preempt_tsg(ch->g, ch->tsgid); else - err = g->ops.fifo.preempt_channel(ch->g, ch->hw_chid); + err = g->ops.fifo.preempt_channel(ch->g, ch->chid); return err; } @@ -2973,7 +2973,7 @@ u32 gk20a_fifo_default_timeslice_us(struct gk20a *g) void gk20a_get_ch_runlist_entry(struct channel_gk20a *ch, u32 *runlist) { - runlist[0] = ram_rl_entry_chid_f(ch->hw_chid); + runlist[0] = ram_rl_entry_chid_f(ch->chid); runlist[1] = 0; } @@ -3066,7 +3066,7 @@ static u32 *gk20a_runlist_construct_locked(struct fifo_gk20a *f, down_read(&tsg->ch_list_lock); /* add runnable channels bound to this TSG */ list_for_each_entry(ch, &tsg->ch_list, ch_entry) { - if (!test_bit(ch->hw_chid, + if (!test_bit(ch->chid, runlist->active_channels)) continue; @@ -3076,7 +3076,7 @@ static u32 *gk20a_runlist_construct_locked(struct fifo_gk20a *f, } gk20a_dbg_info("add channel %d to runlist", - ch->hw_chid); + ch->chid); f->g->ops.fifo.get_ch_runlist_entry(ch, runlist_entry); gk20a_dbg_info( "run list count %d runlist [0] %x [1] %x\n", @@ -3148,7 +3148,7 @@ int gk20a_fifo_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice) } static int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id, - u32 hw_chid, bool add, + u32 chid, bool add, bool wait_for_finish) { int ret = 0; @@ -3166,24 +3166,24 @@ static int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id, /* valid channel, add/remove it from active list. Otherwise, keep active list untouched for suspend/resume. */ - if (hw_chid != FIFO_INVAL_CHANNEL_ID) { - ch = &f->channel[hw_chid]; + if (chid != FIFO_INVAL_CHANNEL_ID) { + ch = &f->channel[chid]; if (gk20a_is_channel_marked_as_tsg(ch)) tsg = &f->tsg[ch->tsgid]; if (add) { - if (test_and_set_bit(hw_chid, + if (test_and_set_bit(chid, runlist->active_channels) == 1) return 0; if (tsg && ++tsg->num_active_channels) - set_bit(f->channel[hw_chid].tsgid, + set_bit(f->channel[chid].tsgid, runlist->active_tsgs); } else { - if (test_and_clear_bit(hw_chid, + if (test_and_clear_bit(chid, runlist->active_channels) == 0) return 0; if (tsg && --tsg->num_active_channels == 0) - clear_bit(f->channel[hw_chid].tsgid, + clear_bit(f->channel[chid].tsgid, runlist->active_tsgs); } } @@ -3208,7 +3208,7 @@ static int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id, goto clean_up; } - if (hw_chid != FIFO_INVAL_CHANNEL_ID || /* add/remove a valid channel */ + if (chid != FIFO_INVAL_CHANNEL_ID || /* add/remove a valid channel */ add /* resume to add all channels back */) { u32 max_entries = f->num_runlist_entries; u32 *runlist_end; @@ -3270,7 +3270,7 @@ clean_up: return ret; } -int gk20a_fifo_update_runlist_ids(struct gk20a *g, u32 runlist_ids, u32 hw_chid, +int gk20a_fifo_update_runlist_ids(struct gk20a *g, u32 runlist_ids, u32 chid, bool add, bool wait_for_finish) { u32 ret = -EINVAL; @@ -3284,7 +3284,7 @@ int gk20a_fifo_update_runlist_ids(struct gk20a *g, u32 runlist_ids, u32 hw_chid, ret = 0; for_each_set_bit(runlist_id, &ulong_runlist_ids, 32) { /* Capture the last failure error code */ - errcode = g->ops.fifo.update_runlist(g, runlist_id, hw_chid, add, wait_for_finish); + errcode = g->ops.fifo.update_runlist(g, runlist_id, chid, add, wait_for_finish); if (errcode) { nvgpu_err(g, "failed to update_runlist %d %d", runlist_id, errcode); @@ -3297,9 +3297,9 @@ end: /* add/remove a channel from runlist special cases below: runlist->active_channels will NOT be changed. - (hw_chid == ~0 && !add) means remove all active channels from runlist. - (hw_chid == ~0 && add) means restore all active channels on runlist. */ -int gk20a_fifo_update_runlist(struct gk20a *g, u32 runlist_id, u32 hw_chid, + (chid == ~0 && !add) means remove all active channels from runlist. + (chid == ~0 && add) means restore all active channels on runlist. */ +int gk20a_fifo_update_runlist(struct gk20a *g, u32 runlist_id, u32 chid, bool add, bool wait_for_finish) { struct fifo_runlist_info_gk20a *runlist = NULL; @@ -3316,7 +3316,7 @@ int gk20a_fifo_update_runlist(struct gk20a *g, u32 runlist_id, u32 hw_chid, mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); - ret = gk20a_fifo_update_runlist_locked(g, runlist_id, hw_chid, add, + ret = gk20a_fifo_update_runlist_locked(g, runlist_id, chid, add, wait_for_finish); if (!mutex_ret) @@ -3427,11 +3427,11 @@ u32 gk20a_fifo_get_pbdma_signature(struct gk20a *g) return pbdma_signature_hw_valid_f() | pbdma_signature_sw_zero_f(); } -struct channel_gk20a *gk20a_fifo_channel_from_hw_chid(struct gk20a *g, - u32 hw_chid) +struct channel_gk20a *gk20a_fifo_channel_from_chid(struct gk20a *g, + u32 chid) { - if (hw_chid != FIFO_INVAL_CHANNEL_ID) - return g->fifo.channel + hw_chid; + if (chid != FIFO_INVAL_CHANNEL_ID) + return g->fifo.channel + chid; else return NULL; } @@ -3487,14 +3487,14 @@ const char *gk20a_decode_pbdma_chan_eng_ctx_status(u32 index) void gk20a_dump_channel_status_ramfc(struct gk20a *g, struct gk20a_debug_output *o, - u32 hw_chid, + u32 chid, struct ch_state *ch_state) { - u32 channel = gk20a_readl(g, ccsr_channel_r(hw_chid)); + u32 channel = gk20a_readl(g, ccsr_channel_r(chid)); u32 status = ccsr_channel_status_v(channel); u32 syncpointa, syncpointb; u32 *inst_mem; - struct channel_gk20a *c = g->fifo.channel + hw_chid; + struct channel_gk20a *c = g->fifo.channel + chid; struct nvgpu_semaphore_int *hw_sema = NULL; if (c->hw_sema) @@ -3508,7 +3508,7 @@ void gk20a_dump_channel_status_ramfc(struct gk20a *g, syncpointa = inst_mem[ram_fc_syncpointa_w()]; syncpointb = inst_mem[ram_fc_syncpointb_w()]; - gk20a_debug_output(o, "%d-%s, pid %d, refs %d%s: ", hw_chid, + gk20a_debug_output(o, "%d-%s, pid %d, refs %d%s: ", chid, g->name, ch_state->pid, ch_state->refs, @@ -3673,16 +3673,16 @@ void gk20a_dump_eng_status(struct gk20a *g, void gk20a_fifo_enable_channel(struct channel_gk20a *ch) { - gk20a_writel(ch->g, ccsr_channel_r(ch->hw_chid), - gk20a_readl(ch->g, ccsr_channel_r(ch->hw_chid)) | + gk20a_writel(ch->g, ccsr_channel_r(ch->chid), + gk20a_readl(ch->g, ccsr_channel_r(ch->chid)) | ccsr_channel_enable_set_true_f()); } void gk20a_fifo_disable_channel(struct channel_gk20a *ch) { - gk20a_writel(ch->g, ccsr_channel_r(ch->hw_chid), + gk20a_writel(ch->g, ccsr_channel_r(ch->chid), gk20a_readl(ch->g, - ccsr_channel_r(ch->hw_chid)) | + ccsr_channel_r(ch->chid)) | ccsr_channel_enable_clr_true_f()); } @@ -3693,23 +3693,23 @@ static void gk20a_fifo_channel_bind(struct channel_gk20a *c) ram_in_base_shift_v(); gk20a_dbg_info("bind channel %d inst ptr 0x%08x", - c->hw_chid, inst_ptr); + c->chid, inst_ptr); - gk20a_writel(g, ccsr_channel_r(c->hw_chid), - (gk20a_readl(g, ccsr_channel_r(c->hw_chid)) & + gk20a_writel(g, ccsr_channel_r(c->chid), + (gk20a_readl(g, ccsr_channel_r(c->chid)) & ~ccsr_channel_runlist_f(~0)) | ccsr_channel_runlist_f(c->runlist_id)); - gk20a_writel(g, ccsr_channel_inst_r(c->hw_chid), + gk20a_writel(g, ccsr_channel_inst_r(c->chid), ccsr_channel_inst_ptr_f(inst_ptr) | nvgpu_aperture_mask(g, &c->inst_block, ccsr_channel_inst_target_sys_mem_ncoh_f(), ccsr_channel_inst_target_vid_mem_f()) | ccsr_channel_inst_bind_true_f()); - gk20a_writel(g, ccsr_channel_r(c->hw_chid), - (gk20a_readl(g, ccsr_channel_r(c->hw_chid)) & + gk20a_writel(g, ccsr_channel_r(c->chid), + (gk20a_readl(g, ccsr_channel_r(c->chid)) & ~ccsr_channel_enable_set_f(~0)) | ccsr_channel_enable_set_true_f()); @@ -3725,7 +3725,7 @@ void gk20a_fifo_channel_unbind(struct channel_gk20a *ch_gk20a) gk20a_dbg_fn(""); if (atomic_cmpxchg(&ch_gk20a->bound, true, false)) { - gk20a_writel(g, ccsr_channel_inst_r(ch_gk20a->hw_chid), + gk20a_writel(g, ccsr_channel_inst_r(ch_gk20a->chid), ccsr_channel_inst_ptr_f(0) | ccsr_channel_inst_bind_false_f()); } @@ -3743,7 +3743,7 @@ static int gk20a_fifo_commit_userd(struct channel_gk20a *c) addr_hi = u64_hi32(c->userd_iova); gk20a_dbg_info("channel %d : set ramfc userd 0x%16llx", - c->hw_chid, (u64)c->userd_iova); + c->chid, (u64)c->userd_iova); nvgpu_mem_wr32(g, &c->inst_block, ram_in_ramfc_w() + ram_fc_userd_w(), @@ -3815,7 +3815,7 @@ int gk20a_fifo_setup_ramfc(struct channel_gk20a *c, fifo_pb_timeslice_timescale_0_f() | fifo_pb_timeslice_enable_true_f()); - nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid)); + nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->chid)); if (c->is_privileged_channel) gk20a_fifo_setup_ramfc_for_privileged_channel(c); @@ -3834,7 +3834,7 @@ static int channel_gk20a_set_schedule_params(struct channel_gk20a *c) c->g->ops.fifo.disable_channel(c); /* preempt the channel */ - WARN_ON(c->g->ops.fifo.preempt_channel(c->g, c->hw_chid)); + WARN_ON(c->g->ops.fifo.preempt_channel(c->g, c->chid)); /* set new timeslice */ nvgpu_mem_wr32(c->g, &c->inst_block, ram_fc_runlist_timeslice_w(), @@ -3863,7 +3863,7 @@ int gk20a_fifo_set_timeslice(struct channel_gk20a *ch, u32 timeslice) ch->timeslice_us = timeslice; gk20a_dbg(gpu_dbg_sched, "chid=%u timeslice=%u us", - ch->hw_chid, timeslice); + ch->chid, timeslice); return channel_gk20a_set_schedule_params(ch); } @@ -3899,7 +3899,7 @@ void gk20a_fifo_setup_ramfc_for_privileged_channel(struct channel_gk20a *c) struct gk20a *g = c->g; struct nvgpu_mem *mem = &c->inst_block; - gk20a_dbg_info("channel %d : set ramfc privileged_channel", c->hw_chid); + gk20a_dbg_info("channel %d : set ramfc privileged_channel", c->chid); /* Enable HCE priv mode for phys mode transfer */ nvgpu_mem_wr32(g, mem, ram_fc_hce_ctrl_w(), @@ -3910,7 +3910,7 @@ int gk20a_fifo_setup_userd(struct channel_gk20a *c) { struct gk20a *g = c->g; struct nvgpu_mem *mem = &g->fifo.userd; - u32 offset = c->hw_chid * g->fifo.userd_entry_size / sizeof(u32); + u32 offset = c->chid * g->fifo.userd_entry_size / sizeof(u32); gk20a_dbg_fn(""); @@ -3939,7 +3939,7 @@ int gk20a_fifo_alloc_inst(struct gk20a *g, struct channel_gk20a *ch) return err; gk20a_dbg_info("channel %d inst block physical addr: 0x%16llx", - ch->hw_chid, gk20a_mm_inst_block_addr(g, &ch->inst_block)); + ch->chid, gk20a_mm_inst_block_addr(g, &ch->inst_block)); gk20a_dbg_fn("done"); return 0; diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index 7e919346..6537b00f 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h @@ -227,7 +227,7 @@ int gk20a_init_fifo_setup_hw(struct gk20a *g); void gk20a_fifo_isr(struct gk20a *g); int gk20a_fifo_nonstall_isr(struct gk20a *g); -int gk20a_fifo_preempt_channel(struct gk20a *g, u32 hw_chid); +int gk20a_fifo_preempt_channel(struct gk20a *g, u32 chid); int gk20a_fifo_preempt_tsg(struct gk20a *g, u32 tsgid); int gk20a_fifo_preempt(struct gk20a *g, struct channel_gk20a *ch); @@ -239,9 +239,9 @@ int gk20a_fifo_disable_engine_activity(struct gk20a *g, bool wait_for_idle); int gk20a_fifo_disable_all_engine_activity(struct gk20a *g, bool wait_for_idle); -u32 gk20a_fifo_engines_on_ch(struct gk20a *g, u32 hw_chid); +u32 gk20a_fifo_engines_on_ch(struct gk20a *g, u32 chid); -int gk20a_fifo_update_runlist(struct gk20a *g, u32 engine_id, u32 hw_chid, +int gk20a_fifo_update_runlist(struct gk20a *g, u32 engine_id, u32 chid, bool add, bool wait_for_finish); int gk20a_fifo_suspend(struct gk20a *g); @@ -253,7 +253,7 @@ void gk20a_fifo_recover(struct gk20a *g, u32 hw_id, /* if ~0, will be queried from HW */ bool hw_id_is_tsg, /* ignored if hw_id == ~0 */ bool id_is_known, bool verbose); -void gk20a_fifo_recover_ch(struct gk20a *g, u32 hw_chid, bool verbose); +void gk20a_fifo_recover_ch(struct gk20a *g, u32 chid, bool verbose); void gk20a_fifo_recover_tsg(struct gk20a *g, u32 tsgid, bool verbose); int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch, u32 err_code, bool verbose); @@ -277,8 +277,8 @@ void gk20a_fifo_set_ctx_mmu_error_ch(struct gk20a *g, bool gk20a_fifo_error_tsg(struct gk20a *g, struct tsg_gk20a *tsg); bool gk20a_fifo_error_ch(struct gk20a *g, struct channel_gk20a *refch); -struct channel_gk20a *gk20a_fifo_channel_from_hw_chid(struct gk20a *g, - u32 hw_chid); +struct channel_gk20a *gk20a_fifo_channel_from_chid(struct gk20a *g, + u32 chid); void gk20a_fifo_issue_preempt(struct gk20a *g, u32 id, bool is_tsg); int gk20a_fifo_set_runlist_interleave(struct gk20a *g, @@ -316,7 +316,7 @@ u32 gk20a_fifo_get_gr_runlist_id(struct gk20a *g); bool gk20a_fifo_is_valid_runlist_id(struct gk20a *g, u32 runlist_id); -int gk20a_fifo_update_runlist_ids(struct gk20a *g, u32 runlist_ids, u32 hw_chid, +int gk20a_fifo_update_runlist_ids(struct gk20a *g, u32 runlist_ids, u32 chid, bool add, bool wait_for_finish); int gk20a_fifo_init_engine_info(struct fifo_gk20a *f); @@ -339,7 +339,7 @@ void gk20a_fifo_profile_release(struct gk20a *g, void gk20a_dump_channel_status_ramfc(struct gk20a *g, struct gk20a_debug_output *o, - u32 hw_chid, + u32 chid, struct ch_state *ch_state); void gk20a_debug_dump_all_channel_status_ramfc(struct gk20a *g, struct gk20a_debug_output *o); diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index ce84a93e..06db2b7f 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -426,10 +426,10 @@ struct gpu_ops { unsigned long acquire_timeout, u32 flags); int (*resetup_ramfc)(struct channel_gk20a *c); - int (*preempt_channel)(struct gk20a *g, u32 hw_chid); + int (*preempt_channel)(struct gk20a *g, u32 chid); int (*preempt_tsg)(struct gk20a *g, u32 tsgid); int (*update_runlist)(struct gk20a *g, u32 runlist_id, - u32 hw_chid, bool add, + u32 chid, bool add, bool wait_for_finish); void (*trigger_mmu_fault)(struct gk20a *g, unsigned long engine_ids); @@ -477,7 +477,7 @@ struct gpu_ops { void (*dump_eng_status)(struct gk20a *g, struct gk20a_debug_output *o); void (*dump_channel_status_ramfc)(struct gk20a *g, - struct gk20a_debug_output *o, u32 hw_chid, + struct gk20a_debug_output *o, u32 chid, struct ch_state *ch_state); u32 (*intr_0_error_mask)(struct gk20a *g); int (*is_preempt_pending)(struct gk20a *g, u32 id, diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 2ee2048c..a9632eaa 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -725,7 +725,7 @@ static int gr_gk20a_fecs_ctx_bind_channel(struct gk20a *g, u32 ret; gk20a_dbg_info("bind channel %d inst ptr 0x%08x", - c->hw_chid, inst_base_ptr); + c->chid, inst_base_ptr); ret = gr_gk20a_submit_fecs_method_op(g, (struct fecs_method_op_gk20a) { @@ -5933,7 +5933,7 @@ static struct channel_gk20a *gk20a_gr_get_channel_from_ctx( /* check cache first */ for (i = 0; i < GR_CHANNEL_MAP_TLB_SIZE; i++) { if (gr->chid_tlb[i].curr_ctx == curr_ctx) { - chid = gr->chid_tlb[i].hw_chid; + chid = gr->chid_tlb[i].chid; tsgid = gr->chid_tlb[i].tsgid; ret = gk20a_channel_get(&f->channel[chid]); goto unlock; @@ -5964,7 +5964,7 @@ static struct channel_gk20a *gk20a_gr_get_channel_from_ctx( for (i = 0; i < GR_CHANNEL_MAP_TLB_SIZE; i++) { if (gr->chid_tlb[i].curr_ctx == 0) { gr->chid_tlb[i].curr_ctx = curr_ctx; - gr->chid_tlb[i].hw_chid = chid; + gr->chid_tlb[i].chid = chid; gr->chid_tlb[i].tsgid = tsgid; goto unlock; } @@ -5972,7 +5972,7 @@ static struct channel_gk20a *gk20a_gr_get_channel_from_ctx( /* no free entry, flush one */ gr->chid_tlb[gr->channel_tlb_flush_index].curr_ctx = curr_ctx; - gr->chid_tlb[gr->channel_tlb_flush_index].hw_chid = chid; + gr->chid_tlb[gr->channel_tlb_flush_index].chid = chid; gr->chid_tlb[gr->channel_tlb_flush_index].tsgid = tsgid; gr->channel_tlb_flush_index = @@ -6514,7 +6514,7 @@ int gk20a_gr_isr(struct gk20a *g) ch = gk20a_gr_get_channel_from_ctx(g, isr_data.curr_ctx, &tsgid); if (ch) { - isr_data.chid = ch->hw_chid; + isr_data.chid = ch->chid; } else { isr_data.chid = FIFO_INVAL_CHANNEL_ID; nvgpu_err(g, "ch id is INVALID 0xffffffff"); @@ -6626,7 +6626,7 @@ int gk20a_gr_isr(struct gk20a *g) gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, "GPC exception pending"); - fault_ch = gk20a_fifo_channel_from_hw_chid(g, + fault_ch = gk20a_fifo_channel_from_chid(g, isr_data.chid); /*isr_data.chid can be ~0 and fault_ch can be NULL */ @@ -6673,7 +6673,7 @@ int gk20a_gr_isr(struct gk20a *g) tsgid, true, true, true); else if (ch) gk20a_fifo_recover(g, gr_engine_id, - ch->hw_chid, false, true, true); + ch->chid, false, true, true); else gk20a_fifo_recover(g, gr_engine_id, 0, false, false, true); @@ -8337,16 +8337,16 @@ bool gk20a_is_channel_ctx_resident(struct channel_gk20a *ch) gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "curr_gr_chid=%d curr_tsgid=%d, ch->tsgid=%d" - " ch->hw_chid=%d", - curr_ch ? curr_ch->hw_chid : -1, + " ch->chid=%d", + curr_ch ? curr_ch->chid : -1, curr_gr_tsgid, ch->tsgid, - ch->hw_chid); + ch->chid); if (!curr_ch) return false; - if (ch->hw_chid == curr_ch->hw_chid) + if (ch->chid == curr_ch->chid) ret = true; if (gk20a_is_channel_marked_as_tsg(ch) && (ch->tsgid == curr_gr_tsgid)) diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 745848ab..109ae0a3 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h @@ -112,7 +112,7 @@ enum { struct gr_channel_map_tlb_entry { u32 curr_ctx; - u32 hw_chid; + u32 chid; u32 tsgid; }; diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h index 2581bc0d..7c476526 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h @@ -171,7 +171,7 @@ struct mmu_fault_info { u32 faulted_pbdma; u32 faulted_engine; u32 faulted_subid; - u32 hw_chid; + u32 chid; struct channel_gk20a *refch; const char *client_type_desc; const char *fault_type_desc; diff --git a/drivers/gpu/nvgpu/gk20a/sync_gk20a.c b/drivers/gpu/nvgpu/gk20a/sync_gk20a.c index 10c4f57b..247f3d63 100644 --- a/drivers/gpu/nvgpu/gk20a/sync_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/sync_gk20a.c @@ -360,7 +360,7 @@ static void gk20a_sync_pt_value_str_for_sema(struct gk20a_sync_pt *pt, struct nvgpu_semaphore *s = pt->sema; snprintf(str, size, "S: c=%d [v=%u,r_v=%u]", - s->hw_sema->ch->hw_chid, + s->hw_sema->ch->chid, nvgpu_semaphore_get_value(s), nvgpu_semaphore_read(s)); } diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c index 46db3dd3..0d07c790 100644 --- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c @@ -61,7 +61,7 @@ static bool gk20a_is_channel_active(struct gk20a *g, struct channel_gk20a *ch) for (i = 0; i < f->max_runlists; ++i) { runlist = &f->runlist_info[i]; - if (test_bit(ch->hw_chid, runlist->active_channels)) + if (test_bit(ch->chid, runlist->active_channels)) return true; } @@ -107,7 +107,7 @@ int gk20a_tsg_bind_channel(struct tsg_gk20a *tsg, kref_get(&tsg->refcount); gk20a_dbg(gpu_dbg_fn, "BIND tsg:%d channel:%d\n", - tsg->tsgid, ch->hw_chid); + tsg->tsgid, ch->chid); gk20a_dbg_fn("done"); return 0; diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index efa0c589..19782412 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c @@ -36,18 +36,18 @@ static void channel_gm20b_bind(struct channel_gk20a *c) >> ram_in_base_shift_v(); gk20a_dbg_info("bind channel %d inst ptr 0x%08x", - c->hw_chid, inst_ptr); + c->chid, inst_ptr); - gk20a_writel(g, ccsr_channel_inst_r(c->hw_chid), + gk20a_writel(g, ccsr_channel_inst_r(c->chid), ccsr_channel_inst_ptr_f(inst_ptr) | nvgpu_aperture_mask(g, &c->inst_block, ccsr_channel_inst_target_sys_mem_ncoh_f(), ccsr_channel_inst_target_vid_mem_f()) | ccsr_channel_inst_bind_true_f()); - gk20a_writel(g, ccsr_channel_r(c->hw_chid), - (gk20a_readl(g, ccsr_channel_r(c->hw_chid)) & + gk20a_writel(g, ccsr_channel_r(c->chid), + (gk20a_readl(g, ccsr_channel_r(c->chid)) & ~ccsr_channel_enable_set_f(~0)) | ccsr_channel_enable_set_true_f()); wmb(); diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c index cfc2eb8d..633fbfb7 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c @@ -64,7 +64,7 @@ int channel_gp10b_commit_userd(struct channel_gk20a *c) addr_hi = u64_hi32(c->userd_iova); gk20a_dbg_info("channel %d : set ramfc userd 0x%16llx", - c->hw_chid, (u64)c->userd_iova); + c->chid, (u64)c->userd_iova); nvgpu_mem_wr32(g, &c->inst_block, ram_in_ramfc_w() + ram_fc_userd_w(), @@ -134,7 +134,7 @@ static int channel_gp10b_setup_ramfc(struct channel_gk20a *c, gp10b_set_pdb_fault_replay_flags(c->g, mem); - nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid)); + nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->chid)); if (c->is_privileged_channel) { /* Set privilege level for channel */ @@ -176,7 +176,7 @@ static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c) v = pbdma_allowed_syncpoints_0_valid_f(1); gk20a_dbg_info("Channel %d, syncpt id %d\n", - c->hw_chid, new_syncpt); + c->chid, new_syncpt); v |= pbdma_allowed_syncpoints_0_index_f(new_syncpt); diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 2356f9f3..9ff34325 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -1653,7 +1653,7 @@ static int gr_gp10b_disable_channel_or_tsg(struct gk20a *g, struct channel_gk20a gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP: preempted tsg"); } else { - gk20a_fifo_issue_preempt(g, fault_ch->hw_chid, false); + gk20a_fifo_issue_preempt(g, fault_ch->chid, false); gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP: preempted channel"); } @@ -1675,7 +1675,7 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, if (gr_ctx->t18x.cilp_preempt_pending) { gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP is already pending for chid %d", - fault_ch->hw_chid); + fault_ch->chid); return 0; } @@ -1718,7 +1718,7 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP: disabling channel %d", - fault_ch->hw_chid); + fault_ch->chid); ret = gr_gp10b_disable_channel_or_tsg(g, fault_ch); if (ret) { @@ -1728,7 +1728,7 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, /* set cilp_preempt_pending = true and record the channel */ gr_ctx->t18x.cilp_preempt_pending = true; - g->gr.t18x.cilp_preempt_pending_chid = fault_ch->hw_chid; + g->gr.t18x.cilp_preempt_pending_chid = fault_ch->chid; if (gk20a_is_channel_marked_as_tsg(fault_ch)) { struct tsg_gk20a *tsg = &g->fifo.tsg[fault_ch->tsgid]; @@ -1758,7 +1758,7 @@ static int gr_gp10b_clear_cilp_preempt_pending(struct gk20a *g, if (!gr_ctx->t18x.cilp_preempt_pending) { gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP is already cleared for chid %d\n", - fault_ch->hw_chid); + fault_ch->chid); return 0; } @@ -1879,7 +1879,7 @@ static int gr_gp10b_get_cilp_preempt_pending_chid(struct gk20a *g, int *__chid) chid = g->gr.t18x.cilp_preempt_pending_chid; - ch = gk20a_channel_get(gk20a_fifo_channel_from_hw_chid(g, chid)); + ch = gk20a_channel_get(gk20a_fifo_channel_from_chid(g, chid)); if (!ch) return ret; @@ -1923,7 +1923,7 @@ int gr_gp10b_handle_fecs_error(struct gk20a *g, goto clean_up; ch = gk20a_channel_get( - gk20a_fifo_channel_from_hw_chid(g, chid)); + gk20a_fifo_channel_from_chid(g, chid)); if (!ch) goto clean_up; @@ -2171,7 +2171,7 @@ static int gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, gk20a_dbg(gpu_dbg_sched, "chid=%d tsgid=%d pid=%d " "graphics_preempt=%d compute_preempt=%d", - ch->hw_chid, + ch->chid, ch->tsgid, ch->tgid, graphics_preempt_mode, diff --git a/drivers/gpu/nvgpu/include/nvgpu/semaphore.h b/drivers/gpu/nvgpu/include/nvgpu/semaphore.h index 45a3af5a..faa8d945 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/semaphore.h +++ b/drivers/gpu/nvgpu/include/nvgpu/semaphore.h @@ -299,7 +299,7 @@ static inline void __nvgpu_semaphore_release(struct nvgpu_semaphore *s, nvgpu_mem_wr(hw_sema->ch->g, &hw_sema->p->rw_mem, hw_sema->offset, val); gpu_sema_verbose_dbg(hw_sema->p->sema_sea->gk20a, - "(c=%d) WRITE %u", hw_sema->ch->hw_chid, val); + "(c=%d) WRITE %u", hw_sema->ch->chid, val); } static inline void nvgpu_semaphore_release(struct nvgpu_semaphore *s) @@ -325,7 +325,7 @@ static inline void nvgpu_semaphore_incr(struct nvgpu_semaphore *s) gpu_sema_verbose_dbg(s->hw_sema->p->sema_sea->gk20a, "INCR sema for c=%d (%u)", - s->hw_sema->ch->hw_chid, + s->hw_sema->ch->chid, nvgpu_semaphore_next_value(s)); } #endif diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index 8d12bb42..55b3de07 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c @@ -34,7 +34,7 @@ static void vgpu_channel_bind(struct channel_gk20a *ch) &msg.params.channel_config; int err; - gk20a_dbg_info("bind channel %d", ch->hw_chid); + gk20a_dbg_info("bind channel %d", ch->chid); msg.cmd = TEGRA_VGPU_CMD_CHANNEL_BIND; msg.handle = vgpu_get_handle(ch->g); @@ -76,7 +76,7 @@ static int vgpu_channel_alloc_inst(struct gk20a *g, struct channel_gk20a *ch) msg.cmd = TEGRA_VGPU_CMD_CHANNEL_ALLOC_HWCTX; msg.handle = vgpu_get_handle(g); - p->id = ch->hw_chid; + p->id = ch->chid; p->pid = (u64)current->tgid; err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); if (err || msg.ret) { @@ -407,10 +407,10 @@ int vgpu_init_fifo_support(struct gk20a *g) return err; } -static int vgpu_fifo_preempt_channel(struct gk20a *g, u32 hw_chid) +static int vgpu_fifo_preempt_channel(struct gk20a *g, u32 chid) { struct fifo_gk20a *f = &g->fifo; - struct channel_gk20a *ch = &f->channel[hw_chid]; + struct channel_gk20a *ch = &f->channel[chid]; struct tegra_vgpu_cmd_msg msg; struct tegra_vgpu_channel_config_params *p = &msg.params.channel_config; @@ -428,7 +428,7 @@ static int vgpu_fifo_preempt_channel(struct gk20a *g, u32 hw_chid) if (err || msg.ret) { nvgpu_err(g, - "preempt channel %d failed", hw_chid); + "preempt channel %d failed", chid); err = -ENOMEM; } @@ -497,7 +497,7 @@ done: } static int vgpu_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id, - u32 hw_chid, bool add, + u32 chid, bool add, bool wait_for_finish) { struct fifo_gk20a *f = &g->fifo; @@ -511,19 +511,19 @@ static int vgpu_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id, /* valid channel, add/remove it from active list. Otherwise, keep active list untouched for suspend/resume. */ - if (hw_chid != (u32)~0) { + if (chid != (u32)~0) { if (add) { - if (test_and_set_bit(hw_chid, + if (test_and_set_bit(chid, runlist->active_channels) == 1) return 0; } else { - if (test_and_clear_bit(hw_chid, + if (test_and_clear_bit(chid, runlist->active_channels) == 0) return 0; } } - if (hw_chid != (u32)~0 || /* add/remove a valid channel */ + if (chid != (u32)~0 || /* add/remove a valid channel */ add /* resume to add all channels back */) { u32 chid; @@ -544,10 +544,10 @@ static int vgpu_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id, /* add/remove a channel from runlist special cases below: runlist->active_channels will NOT be changed. - (hw_chid == ~0 && !add) means remove all active channels from runlist. - (hw_chid == ~0 && add) means restore all active channels on runlist. */ + (chid == ~0 && !add) means remove all active channels from runlist. + (chid == ~0 && add) means restore all active channels on runlist. */ static int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id, - u32 hw_chid, bool add, bool wait_for_finish) + u32 chid, bool add, bool wait_for_finish) { struct fifo_runlist_info_gk20a *runlist = NULL; struct fifo_gk20a *f = &g->fifo; @@ -559,7 +559,7 @@ static int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id, nvgpu_mutex_acquire(&runlist->mutex); - ret = vgpu_fifo_update_runlist_locked(g, runlist_id, hw_chid, add, + ret = vgpu_fifo_update_runlist_locked(g, runlist_id, chid, add, wait_for_finish); nvgpu_mutex_release(&runlist->mutex); @@ -580,7 +580,7 @@ static int vgpu_channel_set_priority(struct channel_gk20a *ch, u32 priority) &msg.params.channel_priority; int err; - gk20a_dbg_info("channel %d set priority %u", ch->hw_chid, priority); + gk20a_dbg_info("channel %d set priority %u", ch->chid, priority); msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY; msg.handle = vgpu_get_handle(ch->g); @@ -739,7 +739,7 @@ int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info) nvgpu_err(g, "fifo intr (%d) on ch %u", info->type, info->chid); - trace_gk20a_channel_reset(ch->hw_chid, ch->tsgid); + trace_gk20a_channel_reset(ch->chid, ch->tsgid); switch (info->type) { case TEGRA_VGPU_FIFO_INTR_PBDMA: diff --git a/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c index 3f6b6fd9..3ce4aa1f 100644 --- a/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c @@ -69,7 +69,7 @@ static int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg, if (err) { nvgpu_err(tsg->g, "vgpu_tsg_bind_channel failed, ch %d tsgid %d", - ch->hw_chid, tsg->tsgid); + ch->chid, tsg->tsgid); gk20a_tsg_unbind_channel(ch); } -- cgit v1.2.2