From 7ac0b046a538daa1a3532d3d5ae7cba1ef3295ba Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 30 Aug 2018 14:05:16 -0700 Subject: gpu: nvgpu: Move MC HAL to common Move implementation of MC HAL to common/mc. Also bump gk20a implementation to gm20b. gk20a_mc_boot_0 was used via a HAL, but we have only one possible implementation. It also has to be anyway called directly to detect which HALs to assign, so make it a true common function. mc_gk20a_handle_intr_nonstall was also used only in os/linux/intr.c so move it there. JIRA NVGPU-954 Change-Id: I79aedc9158f90d578db0edc17b714617b52690ac Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1813519 Reviewed-by: svc-misra-checker GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 11 +- drivers/gpu/nvgpu/Makefile.sources | 9 +- drivers/gpu/nvgpu/common/mc/mc.c | 54 +++++ drivers/gpu/nvgpu/common/mc/mc_gm20b.c | 294 +++++++++++++++++++++++ drivers/gpu/nvgpu/common/mc/mc_gm20b.h | 51 ++++ drivers/gpu/nvgpu/common/mc/mc_gp10b.c | 224 +++++++++++++++++ drivers/gpu/nvgpu/common/mc/mc_gp10b.h | 47 ++++ drivers/gpu/nvgpu/common/mc/mc_gv100.c | 91 +++++++ drivers/gpu/nvgpu/common/mc/mc_gv100.h | 34 +++ drivers/gpu/nvgpu/common/mc/mc_gv11b.c | 90 +++++++ drivers/gpu/nvgpu/common/mc/mc_gv11b.h | 34 +++ drivers/gpu/nvgpu/gk20a/gk20a.c | 11 +- drivers/gpu/nvgpu/gk20a/gk20a.h | 2 +- drivers/gpu/nvgpu/gk20a/mc_gk20a.c | 331 -------------------------- drivers/gpu/nvgpu/gk20a/mc_gk20a.h | 48 ---- drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 35 ++- drivers/gpu/nvgpu/gp106/hal_gp106.c | 13 +- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 13 +- drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 223 ----------------- drivers/gpu/nvgpu/gp10b/mc_gp10b.h | 46 ---- drivers/gpu/nvgpu/gv100/hal_gv100.c | 17 +- drivers/gpu/nvgpu/gv100/mc_gv100.c | 91 ------- drivers/gpu/nvgpu/gv100/mc_gv100.h | 31 --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 1 - drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 15 +- drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 90 ------- drivers/gpu/nvgpu/gv11b/mc_gv11b.h | 31 --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 1 - drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 1 - drivers/gpu/nvgpu/include/nvgpu/mc.h | 35 +++ drivers/gpu/nvgpu/os/linux/intr.c | 16 +- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 3 - drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 4 - 33 files changed, 1028 insertions(+), 969 deletions(-) create mode 100644 drivers/gpu/nvgpu/common/mc/mc.c create mode 100644 drivers/gpu/nvgpu/common/mc/mc_gm20b.c create mode 100644 drivers/gpu/nvgpu/common/mc/mc_gm20b.h create mode 100644 drivers/gpu/nvgpu/common/mc/mc_gp10b.c create mode 100644 drivers/gpu/nvgpu/common/mc/mc_gp10b.h create mode 100644 drivers/gpu/nvgpu/common/mc/mc_gv100.c create mode 100644 drivers/gpu/nvgpu/common/mc/mc_gv100.h create mode 100644 drivers/gpu/nvgpu/common/mc/mc_gv11b.c create mode 100644 drivers/gpu/nvgpu/common/mc/mc_gv11b.h delete mode 100644 drivers/gpu/nvgpu/gk20a/mc_gk20a.c delete mode 100644 drivers/gpu/nvgpu/gk20a/mc_gk20a.h delete mode 100644 drivers/gpu/nvgpu/gp10b/mc_gp10b.c delete mode 100644 drivers/gpu/nvgpu/gp10b/mc_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gv100/mc_gv100.c delete mode 100644 drivers/gpu/nvgpu/gv100/mc_gv100.h delete mode 100644 drivers/gpu/nvgpu/gv11b/mc_gv11b.c delete mode 100644 drivers/gpu/nvgpu/gv11b/mc_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/mc.h (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index d7399c5d..d0dd252e 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -45,7 +45,12 @@ nvgpu-y += common/bus/bus_gk20a.o \ common/fuse/fuse_gm20b.o \ common/fuse/fuse_gp10b.o \ common/fuse/fuse_gp106.o \ - common/top/top_gv100.o + common/top/top_gv100.o \ + common/mc/mc.o \ + common/mc/mc_gm20b.o \ + common/mc/mc_gp10b.o \ + common/mc/mc_gv11b.o \ + common/mc/mc_gv100.o # Linux specific parts of nvgpu. nvgpu-y += \ @@ -236,7 +241,6 @@ nvgpu-y += \ gk20a/hal.o \ gk20a/tsg_gk20a.o \ gk20a/fecs_trace_gk20a.o \ - gk20a/mc_gk20a.o \ gm20b/hal_gm20b.o \ gm20b/gr_gm20b.o \ gm20b/clk_gm20b.o \ @@ -285,7 +289,6 @@ nvgpu-y += \ gp10b/gr_gp10b.o \ gp10b/gr_ctx_gp10b.o \ gp10b/ce_gp10b.o \ - gp10b/mc_gp10b.o \ gp10b/fifo_gp10b.o \ gp10b/mm_gp10b.o \ gp10b/pmu_gp10b.o \ @@ -308,7 +311,6 @@ nvgpu-y += \ gv11b/gv11b.o \ gv11b/css_gr_gv11b.o \ gv11b/dbg_gpu_gv11b.o \ - gv11b/mc_gv11b.o \ gv11b/hal_gv11b.o \ gv11b/gr_gv11b.o \ gv11b/fifo_gv11b.o \ @@ -327,7 +329,6 @@ nvgpu-y += \ gv100/gr_gv100.o \ gv100/regops_gv100.o \ gv100/flcn_gv100.o \ - gv100/mc_gv100.o \ gv100/nvlink_gv100.o \ gv100/hal_gv100.o \ gv100/pmu_gv100.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index ceec9116..a53548f4 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -107,6 +107,11 @@ srcs := os/posix/nvgpu.c \ common/clock_gating/gv100_gating_reglist.c \ common/fifo/channel.c \ common/fifo/submit.c \ + common/mc/mc.c \ + common/mc/mc_gm20b.c \ + common/mc/mc_gp10b.c \ + common/mc/mc_gv11b.c \ + common/mc/mc_gv100.c \ boardobj/boardobj.c \ boardobj/boardobjgrp.c \ boardobj/boardobjgrpmask.c \ @@ -154,7 +159,6 @@ srcs := os/posix/nvgpu.c \ gk20a/gr_ctx_gk20a.c \ gk20a/hal.c \ gk20a/tsg_gk20a.c \ - gk20a/mc_gk20a.c \ gm20b/hal_gm20b.c \ gm20b/gr_gm20b.c \ gm20b/clk_gm20b.c \ @@ -167,7 +171,6 @@ srcs := os/posix/nvgpu.c \ gp10b/gr_gp10b.c \ gp10b/gr_ctx_gp10b.c \ gp10b/ce_gp10b.c \ - gp10b/mc_gp10b.c \ gp10b/fifo_gp10b.c \ gp10b/mm_gp10b.c \ gp10b/pmu_gp10b.c \ @@ -178,7 +181,6 @@ srcs := os/posix/nvgpu.c \ gp10b/ecc_gp10b.c \ gv11b/gv11b.c \ gv11b/dbg_gpu_gv11b.c \ - gv11b/mc_gv11b.c \ gv11b/hal_gv11b.c \ gv11b/gr_gv11b.c \ gv11b/fifo_gv11b.c \ @@ -210,7 +212,6 @@ srcs := os/posix/nvgpu.c \ gv100/gr_gv100.c \ gv100/regops_gv100.c \ gv100/flcn_gv100.c \ - gv100/mc_gv100.c \ gv100/nvlink_gv100.c \ gv100/hal_gv100.c \ gv100/pmu_gv100.c diff --git a/drivers/gpu/nvgpu/common/mc/mc.c b/drivers/gpu/nvgpu/common/mc/mc.c new file mode 100644 index 00000000..77416ef9 --- /dev/null +++ b/drivers/gpu/nvgpu/common/mc/mc.c @@ -0,0 +1,54 @@ +/* + * GK20A Master Control + * + * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +#include "gk20a/gk20a.h" + +#include + +u32 nvgpu_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev) +{ + u32 val = __nvgpu_readl(g, mc_boot_0_r()); + + if (val != 0xffffffffU) { + + if (arch != NULL) { + *arch = mc_boot_0_architecture_v(val) << + NVGPU_GPU_ARCHITECTURE_SHIFT; + } + + if (impl != NULL) { + *impl = mc_boot_0_implementation_v(val); + } + + if (rev != NULL) { + *rev = (mc_boot_0_major_revision_v(val) << 4) | + mc_boot_0_minor_revision_v(val); + } + } + + return val; +} diff --git a/drivers/gpu/nvgpu/common/mc/mc_gm20b.c b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c new file mode 100644 index 00000000..88666b1d --- /dev/null +++ b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c @@ -0,0 +1,294 @@ +/* + * GK20A Master Control + * + * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include + +#include "gk20a/gk20a.h" +#include "mc_gm20b.h" + +#include + +void gm20b_mc_isr_stall(struct gk20a *g) +{ + u32 mc_intr_0; + u32 engine_id_idx; + u32 active_engine_id = 0; + u32 engine_enum = ENGINE_INVAL_GK20A; + + mc_intr_0 = g->ops.mc.intr_stall(g); + + nvgpu_log(g, gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); + + for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) { + active_engine_id = g->fifo.active_engines_list[engine_id_idx]; + + if ((mc_intr_0 & g->fifo.engine_info[active_engine_id].intr_mask) != 0U) { + engine_enum = g->fifo.engine_info[active_engine_id].engine_enum; + /* GR Engine */ + if (engine_enum == ENGINE_GR_GK20A) { + gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); + } + + /* CE Engine */ + if (((engine_enum == ENGINE_GRCE_GK20A) || + (engine_enum == ENGINE_ASYNC_CE_GK20A)) && + (g->ops.ce2.isr_stall != NULL)) { + g->ops.ce2.isr_stall(g, + g->fifo.engine_info[active_engine_id].inst_id, + g->fifo.engine_info[active_engine_id].pri_base); + } + } + } + if ((mc_intr_0 & mc_intr_pfifo_pending_f()) != 0U) { + gk20a_fifo_isr(g); + } + if ((mc_intr_0 & mc_intr_pmu_pending_f()) != 0U) { + g->ops.pmu.pmu_isr(g); + } + if ((mc_intr_0 & mc_intr_priv_ring_pending_f()) != 0U) { + g->ops.priv_ring.isr(g); + } + if ((mc_intr_0 & mc_intr_ltc_pending_f()) != 0U) { + g->ops.ltc.isr(g); + } + if ((mc_intr_0 & mc_intr_pbus_pending_f()) != 0U) { + g->ops.bus.isr(g); + } +} + +u32 gm20b_mc_isr_nonstall(struct gk20a *g) +{ + u32 ops = 0; + u32 mc_intr_1; + u32 engine_id_idx; + u32 active_engine_id = 0; + u32 engine_enum = ENGINE_INVAL_GK20A; + + mc_intr_1 = g->ops.mc.intr_nonstall(g); + + if (g->ops.mc.is_intr1_pending(g, NVGPU_UNIT_FIFO, mc_intr_1) != 0U) { + ops |= gk20a_fifo_nonstall_isr(g); + } + + for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; + engine_id_idx++) { + struct fifo_engine_info_gk20a *engine_info; + + active_engine_id = g->fifo.active_engines_list[engine_id_idx]; + engine_info = &g->fifo.engine_info[active_engine_id]; + + if ((mc_intr_1 & engine_info->intr_mask) != 0U) { + engine_enum = engine_info->engine_enum; + /* GR Engine */ + if (engine_enum == ENGINE_GR_GK20A) { + ops |= gk20a_gr_nonstall_isr(g); + } + /* CE Engine */ + if (((engine_enum == ENGINE_GRCE_GK20A) || + (engine_enum == ENGINE_ASYNC_CE_GK20A)) && + (g->ops.ce2.isr_nonstall != NULL)) { + ops |= g->ops.ce2.isr_nonstall(g, + engine_info->inst_id, + engine_info->pri_base); + } + } + } + + return ops; +} + +void gm20b_mc_intr_mask(struct gk20a *g) +{ + nvgpu_writel(g, mc_intr_en_0_r(), + mc_intr_en_0_inta_disabled_f()); + nvgpu_writel(g, mc_intr_en_1_r(), + mc_intr_en_1_inta_disabled_f()); +} + +void gm20b_mc_intr_enable(struct gk20a *g) +{ + u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); + + gk20a_writel(g, mc_intr_mask_1_r(), + mc_intr_pfifo_pending_f() + | eng_intr_mask); + gk20a_writel(g, mc_intr_en_1_r(), + mc_intr_en_1_inta_hardware_f()); + + gk20a_writel(g, mc_intr_mask_0_r(), + mc_intr_pfifo_pending_f() + | mc_intr_priv_ring_pending_f() + | mc_intr_ltc_pending_f() + | mc_intr_pbus_pending_f() + | eng_intr_mask); + gk20a_writel(g, mc_intr_en_0_r(), + mc_intr_en_0_inta_hardware_f()); +} + +void gm20b_mc_intr_unit_config(struct gk20a *g, bool enable, + bool is_stalling, u32 mask) +{ + u32 mask_reg = (is_stalling ? mc_intr_mask_0_r() : + mc_intr_mask_1_r()); + + if (enable) { + gk20a_writel(g, mask_reg, + gk20a_readl(g, mask_reg) | + mask); + } else { + gk20a_writel(g, mask_reg, + gk20a_readl(g, mask_reg) & + ~mask); + } +} + +void gm20b_mc_intr_stall_pause(struct gk20a *g) +{ + gk20a_writel(g, mc_intr_en_0_r(), + mc_intr_en_0_inta_disabled_f()); + + /* flush previous write */ + (void) gk20a_readl(g, mc_intr_en_0_r()); +} + +void gm20b_mc_intr_stall_resume(struct gk20a *g) +{ + gk20a_writel(g, mc_intr_en_0_r(), + mc_intr_en_0_inta_hardware_f()); + + /* flush previous write */ + (void) gk20a_readl(g, mc_intr_en_0_r()); +} + +void gm20b_mc_intr_nonstall_pause(struct gk20a *g) +{ + gk20a_writel(g, mc_intr_en_1_r(), + mc_intr_en_0_inta_disabled_f()); + + /* flush previous write */ + (void) gk20a_readl(g, mc_intr_en_1_r()); +} + +void gm20b_mc_intr_nonstall_resume(struct gk20a *g) +{ + gk20a_writel(g, mc_intr_en_1_r(), + mc_intr_en_0_inta_hardware_f()); + + /* flush previous write */ + (void) gk20a_readl(g, mc_intr_en_1_r()); +} + +u32 gm20b_mc_intr_stall(struct gk20a *g) +{ + return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING)); +} + +u32 gm20b_mc_intr_nonstall(struct gk20a *g) +{ + return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_NONSTALLING)); +} + +void gm20b_mc_disable(struct gk20a *g, u32 units) +{ + u32 pmc; + + nvgpu_log(g, gpu_dbg_info, "pmc disable: %08x\n", units); + + nvgpu_spinlock_acquire(&g->mc_enable_lock); + pmc = gk20a_readl(g, mc_enable_r()); + pmc &= ~units; + gk20a_writel(g, mc_enable_r(), pmc); + nvgpu_spinlock_release(&g->mc_enable_lock); +} + +void gm20b_mc_enable(struct gk20a *g, u32 units) +{ + u32 pmc; + + nvgpu_log(g, gpu_dbg_info, "pmc enable: %08x\n", units); + + nvgpu_spinlock_acquire(&g->mc_enable_lock); + pmc = gk20a_readl(g, mc_enable_r()); + pmc |= units; + gk20a_writel(g, mc_enable_r(), pmc); + pmc = gk20a_readl(g, mc_enable_r()); + nvgpu_spinlock_release(&g->mc_enable_lock); + + nvgpu_udelay(20); +} + +void gm20b_mc_reset(struct gk20a *g, u32 units) +{ + g->ops.mc.disable(g, units); + if ((units & gk20a_fifo_get_all_ce_engine_reset_mask(g)) != 0U) { + nvgpu_udelay(500); + } else { + nvgpu_udelay(20); + } + g->ops.mc.enable(g, units); +} + +bool gm20b_mc_is_intr1_pending(struct gk20a *g, + enum nvgpu_unit unit, u32 mc_intr_1) +{ + u32 mask = 0U; + bool is_pending; + + switch (unit) { + case NVGPU_UNIT_FIFO: + mask = mc_intr_pfifo_pending_f(); + break; + default: + break; + } + + if (mask == 0U) { + nvgpu_err(g, "unknown unit %d", unit); + is_pending = false; + } else { + is_pending = ((mc_intr_1 & mask) != 0U) ? true : false; + } + + return is_pending; +} + +void gm20b_mc_log_pending_intrs(struct gk20a *g) +{ + u32 intr; + + intr = g->ops.mc.intr_stall(g); + if (intr != 0U) { + nvgpu_info(g, "Pending stall intr0=0x%08x", intr); + } + + intr = g->ops.mc.intr_nonstall(g); + if (intr != 0U) { + nvgpu_info(g, "Pending nonstall intr1=0x%08x", intr); + } +} + diff --git a/drivers/gpu/nvgpu/common/mc/mc_gm20b.h b/drivers/gpu/nvgpu/common/mc/mc_gm20b.h new file mode 100644 index 00000000..6700a48c --- /dev/null +++ b/drivers/gpu/nvgpu/common/mc/mc_gm20b.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_MC_GM20B_H +#define NVGPU_MC_GM20B_H + +#include + +struct gk20a; +enum nvgpu_unit; + +void gm20b_mc_intr_mask(struct gk20a *g); +void gm20b_mc_intr_enable(struct gk20a *g); +void gm20b_mc_intr_unit_config(struct gk20a *g, bool enable, + bool is_stalling, u32 mask); +void gm20b_mc_isr_stall(struct gk20a *g); +u32 gm20b_mc_intr_stall(struct gk20a *g); +void gm20b_mc_intr_stall_pause(struct gk20a *g); +void gm20b_mc_intr_stall_resume(struct gk20a *g); +u32 gm20b_mc_intr_nonstall(struct gk20a *g); +u32 gm20b_mc_isr_nonstall(struct gk20a *g); +void gm20b_mc_intr_nonstall_pause(struct gk20a *g); +void gm20b_mc_intr_nonstall_resume(struct gk20a *g); +void gm20b_mc_enable(struct gk20a *g, u32 units); +void gm20b_mc_disable(struct gk20a *g, u32 units); +void gm20b_mc_reset(struct gk20a *g, u32 units); +bool gm20b_mc_is_intr1_pending(struct gk20a *g, + enum nvgpu_unit unit, u32 mc_intr_1); +void gm20b_mc_log_pending_intrs(struct gk20a *g); +void gm20b_mc_handle_intr_nonstall(struct gk20a *g, u32 ops); + +#endif /* NVGPU_MC_GM20B_H */ diff --git a/drivers/gpu/nvgpu/common/mc/mc_gp10b.c b/drivers/gpu/nvgpu/common/mc/mc_gp10b.c new file mode 100644 index 00000000..a0f26dd3 --- /dev/null +++ b/drivers/gpu/nvgpu/common/mc/mc_gp10b.c @@ -0,0 +1,224 @@ +/* + * GP10B master + * + * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gk20a/gk20a.h" +#include +#include + +#include "mc_gp10b.h" + +#include +#include + +#include + +#define MAX_MC_INTR_REGS 2U + +void mc_gp10b_intr_mask(struct gk20a *g) +{ + nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), + 0xffffffffU); + + nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), + 0xffffffffU); +} + +void mc_gp10b_intr_enable(struct gk20a *g) +{ + u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); + + gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), + 0xffffffffU); + g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] = + mc_intr_pfifo_pending_f() | + mc_intr_priv_ring_pending_f() | + mc_intr_pbus_pending_f() | + mc_intr_ltc_pending_f() | + mc_intr_replayable_fault_pending_f() | + eng_intr_mask; + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), + g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]); + + gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), + 0xffffffffU); + g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = + mc_intr_pfifo_pending_f() | + eng_intr_mask; + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), + g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); +} + +void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable, + bool is_stalling, u32 mask) +{ + u32 intr_index = 0; + u32 reg = 0; + + intr_index = (is_stalling ? NVGPU_MC_INTR_STALLING : + NVGPU_MC_INTR_NONSTALLING); + if (enable) { + reg = mc_intr_en_set_r(intr_index); + g->mc_intr_mask_restore[intr_index] |= mask; + + } else { + reg = mc_intr_en_clear_r(intr_index); + g->mc_intr_mask_restore[intr_index] &= ~mask; + } + + gk20a_writel(g, reg, mask); +} + +void mc_gp10b_isr_stall(struct gk20a *g) +{ + u32 mc_intr_0; + + u32 engine_id_idx; + u32 active_engine_id = 0; + u32 engine_enum = ENGINE_INVAL_GK20A; + + mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); + + nvgpu_log(g, gpu_dbg_intr, "stall intr 0x%08x\n", mc_intr_0); + + for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) { + active_engine_id = g->fifo.active_engines_list[engine_id_idx]; + + if ((mc_intr_0 & g->fifo.engine_info[active_engine_id].intr_mask) != 0U) { + engine_enum = g->fifo.engine_info[active_engine_id].engine_enum; + /* GR Engine */ + if (engine_enum == ENGINE_GR_GK20A) { + gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); + } + + /* CE Engine */ + if (((engine_enum == ENGINE_GRCE_GK20A) || + (engine_enum == ENGINE_ASYNC_CE_GK20A)) && + (g->ops.ce2.isr_stall != NULL)) { + g->ops.ce2.isr_stall(g, + g->fifo.engine_info[active_engine_id].inst_id, + g->fifo.engine_info[active_engine_id].pri_base); + } + } + } + if ((g->ops.mc.is_intr_hub_pending != NULL) && + g->ops.mc.is_intr_hub_pending(g, mc_intr_0)) { + g->ops.fb.hub_isr(g); + } + if ((mc_intr_0 & mc_intr_pfifo_pending_f()) != 0U) { + gk20a_fifo_isr(g); + } + if ((mc_intr_0 & mc_intr_pmu_pending_f()) != 0U) { + g->ops.pmu.pmu_isr(g); + } + if ((mc_intr_0 & mc_intr_priv_ring_pending_f()) != 0U) { + g->ops.priv_ring.isr(g); + } + if ((mc_intr_0 & mc_intr_ltc_pending_f()) != 0U) { + g->ops.ltc.isr(g); + } + if ((mc_intr_0 & mc_intr_pbus_pending_f()) != 0U) { + g->ops.bus.isr(g); + } + if ((g->ops.mc.is_intr_nvlink_pending != NULL) && + g->ops.mc.is_intr_nvlink_pending(g, mc_intr_0)) { + g->ops.nvlink.isr(g); + } + if (mc_intr_0 & mc_intr_pfb_pending_f() && g->ops.fb.fbpa_isr) { + g->ops.fb.fbpa_isr(g); + } + + nvgpu_log(g, gpu_dbg_intr, "stall intr done 0x%08x\n", mc_intr_0); + +} + +u32 mc_gp10b_intr_stall(struct gk20a *g) +{ + return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING)); +} + +void mc_gp10b_intr_stall_pause(struct gk20a *g) +{ + gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), 0xffffffffU); +} + +void mc_gp10b_intr_stall_resume(struct gk20a *g) +{ + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), + g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]); +} + +u32 mc_gp10b_intr_nonstall(struct gk20a *g) +{ + return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_NONSTALLING)); +} + +void mc_gp10b_intr_nonstall_pause(struct gk20a *g) +{ + gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), + 0xffffffffU); +} + +void mc_gp10b_intr_nonstall_resume(struct gk20a *g) +{ + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), + g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); +} + +bool mc_gp10b_is_intr1_pending(struct gk20a *g, + enum nvgpu_unit unit, u32 mc_intr_1) +{ + u32 mask = 0; + bool is_pending; + + switch (unit) { + case NVGPU_UNIT_FIFO: + mask = mc_intr_pfifo_pending_f(); + break; + default: + break; + } + + if (mask == 0U) { + nvgpu_err(g, "unknown unit %d", unit); + is_pending = false; + } else { + is_pending = ((mc_intr_1 & mask) != 0U) ? true : false; + } + + return is_pending; +} + +void mc_gp10b_log_pending_intrs(struct gk20a *g) +{ + u32 i, intr; + + for (i = 0; i < MAX_MC_INTR_REGS; i++) { + intr = nvgpu_readl(g, mc_intr_r(i)); + if (intr == 0U) { + continue; + } + nvgpu_info(g, "Pending intr%d=0x%08x", i, intr); + } + +} diff --git a/drivers/gpu/nvgpu/common/mc/mc_gp10b.h b/drivers/gpu/nvgpu/common/mc/mc_gp10b.h new file mode 100644 index 00000000..ee3c0c3b --- /dev/null +++ b/drivers/gpu/nvgpu/common/mc/mc_gp10b.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef MC_GP10B_H +#define MC_GP10B_H + +#include + +struct gk20a; +enum nvgpu_unit; + +void mc_gp10b_intr_mask(struct gk20a *g); +void mc_gp10b_intr_enable(struct gk20a *g); +void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable, + bool is_stalling, u32 mask); +void mc_gp10b_isr_stall(struct gk20a *g); +bool mc_gp10b_is_intr1_pending(struct gk20a *g, + enum nvgpu_unit unit, u32 mc_intr_1); + +void mc_gp10b_log_pending_intrs(struct gk20a *g); +u32 mc_gp10b_intr_stall(struct gk20a *g); +void mc_gp10b_intr_stall_pause(struct gk20a *g); +void mc_gp10b_intr_stall_resume(struct gk20a *g); +u32 mc_gp10b_intr_nonstall(struct gk20a *g); +void mc_gp10b_intr_nonstall_pause(struct gk20a *g); +void mc_gp10b_intr_nonstall_resume(struct gk20a *g); + +#endif diff --git a/drivers/gpu/nvgpu/common/mc/mc_gv100.c b/drivers/gpu/nvgpu/common/mc/mc_gv100.c new file mode 100644 index 00000000..28c03434 --- /dev/null +++ b/drivers/gpu/nvgpu/common/mc/mc_gv100.c @@ -0,0 +1,91 @@ +/* + * GV100 master + * + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include "gk20a/gk20a.h" + +#include "mc_gp10b.h" +#include "mc_gv100.h" + +#include + +void mc_gv100_intr_enable(struct gk20a *g) +{ + u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); + + gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), + 0xffffffffU); + gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), + 0xffffffffU); + g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] = + mc_intr_pfifo_pending_f() | + mc_intr_hub_pending_f() | + mc_intr_priv_ring_pending_f() | + mc_intr_pbus_pending_f() | + mc_intr_ltc_pending_f() | + mc_intr_nvlink_pending_f() | + eng_intr_mask; + + g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = + mc_intr_pfifo_pending_f() + | eng_intr_mask; + + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), + g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]); + + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), + g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); + +} + +bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0) +{ + return (((mc_intr_0 & mc_intr_nvlink_pending_f()) != 0U) ? true : false); +} + +bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, + u32 *eng_intr_pending) +{ + u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); + u32 stall_intr, eng_intr_mask; + + eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id); + *eng_intr_pending = mc_intr_0 & eng_intr_mask; + + stall_intr = mc_intr_pfifo_pending_f() | + mc_intr_hub_pending_f() | + mc_intr_priv_ring_pending_f() | + mc_intr_pbus_pending_f() | + mc_intr_ltc_pending_f() | + mc_intr_nvlink_pending_f(); + + nvgpu_log(g, gpu_dbg_info | gpu_dbg_intr, + "mc_intr_0 = 0x%08x, eng_intr = 0x%08x", + mc_intr_0 & stall_intr, *eng_intr_pending); + + return (mc_intr_0 & (eng_intr_mask | stall_intr)) != 0U; +} diff --git a/drivers/gpu/nvgpu/common/mc/mc_gv100.h b/drivers/gpu/nvgpu/common/mc/mc_gv100.h new file mode 100644 index 00000000..c0a16ad9 --- /dev/null +++ b/drivers/gpu/nvgpu/common/mc/mc_gv100.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef MC_GV100_H +#define MC_GV100_H + +#include + +struct gk20a; + +void mc_gv100_intr_enable(struct gk20a *g); +bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0); +bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, + u32 *eng_intr_pending); +#endif diff --git a/drivers/gpu/nvgpu/common/mc/mc_gv11b.c b/drivers/gpu/nvgpu/common/mc/mc_gv11b.c new file mode 100644 index 00000000..fa4d4bfb --- /dev/null +++ b/drivers/gpu/nvgpu/common/mc/mc_gv11b.c @@ -0,0 +1,90 @@ +/* + * GV11B master + * + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include "gk20a/gk20a.h" + +#include "mc_gp10b.h" +#include "mc_gv11b.h" + +#include + +void mc_gv11b_intr_enable(struct gk20a *g) +{ + u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); + + gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), + 0xffffffffU); + gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), + 0xffffffffU); + + g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] = + mc_intr_pfifo_pending_f() | + mc_intr_hub_pending_f() | + mc_intr_priv_ring_pending_f() | + mc_intr_pbus_pending_f() | + mc_intr_ltc_pending_f() | + eng_intr_mask; + + g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = + mc_intr_pfifo_pending_f() + | eng_intr_mask; + + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), + g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]); + + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), + g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); + +} + +bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0) +{ + return (((mc_intr_0 & mc_intr_hub_pending_f()) != 0U) ? true : false); +} + +bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, + u32 *eng_intr_pending) +{ + u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); + u32 stall_intr, eng_intr_mask; + + eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id); + *eng_intr_pending = mc_intr_0 & eng_intr_mask; + + stall_intr = mc_intr_pfifo_pending_f() | + mc_intr_hub_pending_f() | + mc_intr_priv_ring_pending_f() | + mc_intr_pbus_pending_f() | + mc_intr_ltc_pending_f(); + + nvgpu_log(g, gpu_dbg_info | gpu_dbg_intr, + "mc_intr_0 = 0x%08x, eng_intr = 0x%08x", + mc_intr_0 & stall_intr, *eng_intr_pending); + + return (mc_intr_0 & (eng_intr_mask | stall_intr)) != 0U; +} diff --git a/drivers/gpu/nvgpu/common/mc/mc_gv11b.h b/drivers/gpu/nvgpu/common/mc/mc_gv11b.h new file mode 100644 index 00000000..48eba744 --- /dev/null +++ b/drivers/gpu/nvgpu/common/mc/mc_gv11b.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef MC_GV11B_H +#define MC_GV11B_H + +#include + +struct gk20a; + +void mc_gv11b_intr_enable(struct gk20a *g); +bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0); +bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, + u32 *eng_intr_pending); +#endif diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index 1c34c152..df16af85 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c @@ -37,6 +37,7 @@ #include #include #include +#include #include @@ -44,7 +45,6 @@ #include "channel_sync_gk20a.h" #include "dbg_gpu_gk20a.h" -#include "mc_gk20a.h" #include "hal.h" #include "pstate/pstate.h" @@ -52,12 +52,7 @@ void __nvgpu_check_gpu_state(struct gk20a *g) { u32 boot_0 = 0xffffffff; - if (!g->ops.mc.boot_0) { - nvgpu_err(g, "Can't determine GPU state, mc.boot_0 unset"); - return; - } - - boot_0 = g->ops.mc.boot_0(g, NULL, NULL, NULL); + boot_0 = nvgpu_mc_boot_0(g, NULL, NULL, NULL); if (boot_0 == 0xffffffff) { nvgpu_err(g, "GPU has disappeared from bus!!"); nvgpu_err(g, "Rebooting system!!"); @@ -78,7 +73,7 @@ int gk20a_detect_chip(struct gk20a *g) return 0; } - gk20a_mc_boot_0(g, &p->gpu_arch, &p->gpu_impl, &p->gpu_rev); + nvgpu_mc_boot_0(g, &p->gpu_arch, &p->gpu_impl, &p->gpu_rev); if ((p->gpu_arch + p->gpu_impl) == NVGPU_GPUID_GV11B) { diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 0df88edf..16a24531 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -30,4 +30,4 @@ /* no new headers should be added here */ #include -#endif \ No newline at end of file +#endif diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c deleted file mode 100644 index f9996e71..00000000 --- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c +++ /dev/null @@ -1,331 +0,0 @@ -/* - * GK20A Master Control - * - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "gk20a.h" -#include "mc_gk20a.h" - -#include -#include -#include -#include - -#include - -void mc_gk20a_isr_stall(struct gk20a *g) -{ - u32 mc_intr_0; - u32 engine_id_idx; - u32 active_engine_id = 0; - u32 engine_enum = ENGINE_INVAL_GK20A; - - mc_intr_0 = g->ops.mc.intr_stall(g); - - nvgpu_log(g, gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); - - for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) { - active_engine_id = g->fifo.active_engines_list[engine_id_idx]; - - if ((mc_intr_0 & g->fifo.engine_info[active_engine_id].intr_mask) != 0U) { - engine_enum = g->fifo.engine_info[active_engine_id].engine_enum; - /* GR Engine */ - if (engine_enum == ENGINE_GR_GK20A) { - gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); - } - - /* CE Engine */ - if (((engine_enum == ENGINE_GRCE_GK20A) || - (engine_enum == ENGINE_ASYNC_CE_GK20A)) && - (g->ops.ce2.isr_stall != NULL)) { - g->ops.ce2.isr_stall(g, - g->fifo.engine_info[active_engine_id].inst_id, - g->fifo.engine_info[active_engine_id].pri_base); - } - } - } - if ((mc_intr_0 & mc_intr_0_pfifo_pending_f()) != 0U) { - gk20a_fifo_isr(g); - } - if ((mc_intr_0 & mc_intr_0_pmu_pending_f()) != 0U) { - g->ops.pmu.pmu_isr(g); - } - if ((mc_intr_0 & mc_intr_0_priv_ring_pending_f()) != 0U) { - g->ops.priv_ring.isr(g); - } - if ((mc_intr_0 & mc_intr_0_ltc_pending_f()) != 0U) { - g->ops.ltc.isr(g); - } - if ((mc_intr_0 & mc_intr_0_pbus_pending_f()) != 0U) { - g->ops.bus.isr(g); - } -} - -u32 mc_gk20a_isr_nonstall(struct gk20a *g) -{ - u32 ops = 0; - u32 mc_intr_1; - u32 engine_id_idx; - u32 active_engine_id = 0; - u32 engine_enum = ENGINE_INVAL_GK20A; - - mc_intr_1 = g->ops.mc.intr_nonstall(g); - - if (g->ops.mc.is_intr1_pending(g, NVGPU_UNIT_FIFO, mc_intr_1) != 0U) { - ops |= gk20a_fifo_nonstall_isr(g); - } - - for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; - engine_id_idx++) { - struct fifo_engine_info_gk20a *engine_info; - - active_engine_id = g->fifo.active_engines_list[engine_id_idx]; - engine_info = &g->fifo.engine_info[active_engine_id]; - - if ((mc_intr_1 & engine_info->intr_mask) != 0U) { - engine_enum = engine_info->engine_enum; - /* GR Engine */ - if (engine_enum == ENGINE_GR_GK20A) { - ops |= gk20a_gr_nonstall_isr(g); - } - /* CE Engine */ - if (((engine_enum == ENGINE_GRCE_GK20A) || - (engine_enum == ENGINE_ASYNC_CE_GK20A)) && - (g->ops.ce2.isr_nonstall != NULL)) { - ops |= g->ops.ce2.isr_nonstall(g, - engine_info->inst_id, - engine_info->pri_base); - } - } - } - - return ops; -} - -void mc_gk20a_intr_mask(struct gk20a *g) -{ - nvgpu_writel(g, mc_intr_en_0_r(), - mc_intr_en_0_inta_disabled_f()); - nvgpu_writel(g, mc_intr_en_1_r(), - mc_intr_en_1_inta_disabled_f()); -} - -void mc_gk20a_intr_enable(struct gk20a *g) -{ - u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); - - gk20a_writel(g, mc_intr_mask_1_r(), - mc_intr_0_pfifo_pending_f() - | eng_intr_mask); - gk20a_writel(g, mc_intr_en_1_r(), - mc_intr_en_1_inta_hardware_f()); - - gk20a_writel(g, mc_intr_mask_0_r(), - mc_intr_0_pfifo_pending_f() - | mc_intr_0_priv_ring_pending_f() - | mc_intr_0_ltc_pending_f() - | mc_intr_0_pbus_pending_f() - | eng_intr_mask); - gk20a_writel(g, mc_intr_en_0_r(), - mc_intr_en_0_inta_hardware_f()); -} - -void mc_gk20a_intr_unit_config(struct gk20a *g, bool enable, - bool is_stalling, u32 mask) -{ - u32 mask_reg = (is_stalling ? mc_intr_mask_0_r() : - mc_intr_mask_1_r()); - - if (enable) { - gk20a_writel(g, mask_reg, - gk20a_readl(g, mask_reg) | - mask); - } else { - gk20a_writel(g, mask_reg, - gk20a_readl(g, mask_reg) & - ~mask); - } -} - -void mc_gk20a_intr_stall_pause(struct gk20a *g) -{ - gk20a_writel(g, mc_intr_en_0_r(), - mc_intr_en_0_inta_disabled_f()); - - /* flush previous write */ - (void) gk20a_readl(g, mc_intr_en_0_r()); -} - -void mc_gk20a_intr_stall_resume(struct gk20a *g) -{ - gk20a_writel(g, mc_intr_en_0_r(), - mc_intr_en_0_inta_hardware_f()); - - /* flush previous write */ - (void) gk20a_readl(g, mc_intr_en_0_r()); -} - -void mc_gk20a_intr_nonstall_pause(struct gk20a *g) -{ - gk20a_writel(g, mc_intr_en_1_r(), - mc_intr_en_0_inta_disabled_f()); - - /* flush previous write */ - (void) gk20a_readl(g, mc_intr_en_1_r()); -} - -void mc_gk20a_intr_nonstall_resume(struct gk20a *g) -{ - gk20a_writel(g, mc_intr_en_1_r(), - mc_intr_en_0_inta_hardware_f()); - - /* flush previous write */ - (void) gk20a_readl(g, mc_intr_en_1_r()); -} - -u32 mc_gk20a_intr_stall(struct gk20a *g) -{ - return gk20a_readl(g, mc_intr_0_r()); -} - -u32 mc_gk20a_intr_nonstall(struct gk20a *g) -{ - return gk20a_readl(g, mc_intr_1_r()); -} - -void gk20a_mc_disable(struct gk20a *g, u32 units) -{ - u32 pmc; - - nvgpu_log(g, gpu_dbg_info, "pmc disable: %08x\n", units); - - nvgpu_spinlock_acquire(&g->mc_enable_lock); - pmc = gk20a_readl(g, mc_enable_r()); - pmc &= ~units; - gk20a_writel(g, mc_enable_r(), pmc); - nvgpu_spinlock_release(&g->mc_enable_lock); -} - -void gk20a_mc_enable(struct gk20a *g, u32 units) -{ - u32 pmc; - - nvgpu_log(g, gpu_dbg_info, "pmc enable: %08x\n", units); - - nvgpu_spinlock_acquire(&g->mc_enable_lock); - pmc = gk20a_readl(g, mc_enable_r()); - pmc |= units; - gk20a_writel(g, mc_enable_r(), pmc); - pmc = gk20a_readl(g, mc_enable_r()); - nvgpu_spinlock_release(&g->mc_enable_lock); - - nvgpu_udelay(20); -} - -void gk20a_mc_reset(struct gk20a *g, u32 units) -{ - g->ops.mc.disable(g, units); - if ((units & gk20a_fifo_get_all_ce_engine_reset_mask(g)) != 0U) { - nvgpu_udelay(500); - } else { - nvgpu_udelay(20); - } - g->ops.mc.enable(g, units); -} - -u32 gk20a_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev) -{ - u32 val = __nvgpu_readl(g, mc_boot_0_r()); - - if (val != 0xffffffffU) { - - if (arch != NULL) { - *arch = mc_boot_0_architecture_v(val) << - NVGPU_GPU_ARCHITECTURE_SHIFT; - } - - if (impl != NULL) { - *impl = mc_boot_0_implementation_v(val); - } - - if (rev != NULL) { - *rev = (mc_boot_0_major_revision_v(val) << 4) | - mc_boot_0_minor_revision_v(val); - } - } - - return val; -} - -bool mc_gk20a_is_intr1_pending(struct gk20a *g, - enum nvgpu_unit unit, u32 mc_intr_1) -{ - u32 mask = 0U; - bool is_pending; - - switch (unit) { - case NVGPU_UNIT_FIFO: - mask = mc_intr_0_pfifo_pending_f(); - break; - default: - break; - } - - if (mask == 0U) { - nvgpu_err(g, "unknown unit %d", unit); - is_pending = false; - } else { - is_pending = ((mc_intr_1 & mask) != 0U) ? true : false; - } - - return is_pending; -} - -void mc_gk20a_log_pending_intrs(struct gk20a *g) -{ - u32 intr; - - intr = g->ops.mc.intr_stall(g); - if (intr != 0U) { - nvgpu_info(g, "Pending stall intr0=0x%08x", intr); - } - - intr = g->ops.mc.intr_nonstall(g); - if (intr != 0U) { - nvgpu_info(g, "Pending nonstall intr1=0x%08x", intr); - } -} - -void mc_gk20a_handle_intr_nonstall(struct gk20a *g, u32 ops) -{ - bool semaphore_wakeup, post_events; - - semaphore_wakeup = - (((ops & GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE) != 0U) ? - true : false); - post_events = (((ops & GK20A_NONSTALL_OPS_POST_EVENTS) != 0U) ? - true: false); - - if (semaphore_wakeup) { - g->ops.semaphore_wakeup(g, post_events); - } -} diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.h b/drivers/gpu/nvgpu/gk20a/mc_gk20a.h deleted file mode 100644 index 0dfdf906..00000000 --- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef MC_GK20A_H -#define MC_GK20A_H -struct gk20a; - -void mc_gk20a_intr_mask(struct gk20a *g); -void mc_gk20a_intr_enable(struct gk20a *g); -void mc_gk20a_intr_unit_config(struct gk20a *g, bool enable, - bool is_stalling, u32 mask); -void mc_gk20a_isr_stall(struct gk20a *g); -u32 mc_gk20a_intr_stall(struct gk20a *g); -void mc_gk20a_intr_stall_pause(struct gk20a *g); -void mc_gk20a_intr_stall_resume(struct gk20a *g); -u32 mc_gk20a_intr_nonstall(struct gk20a *g); -u32 mc_gk20a_isr_nonstall(struct gk20a *g); -void mc_gk20a_intr_nonstall_pause(struct gk20a *g); -void mc_gk20a_intr_nonstall_resume(struct gk20a *g); -void gk20a_mc_enable(struct gk20a *g, u32 units); -void gk20a_mc_disable(struct gk20a *g, u32 units); -void gk20a_mc_reset(struct gk20a *g, u32 units); -u32 gk20a_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev); -bool mc_gk20a_is_intr1_pending(struct gk20a *g, - enum nvgpu_unit unit, u32 mc_intr_1); -void mc_gk20a_log_pending_intrs(struct gk20a *g); -void mc_gk20a_handle_intr_nonstall(struct gk20a *g, u32 ops); - -#endif /* MC_GK20A_H */ diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index ca7081cf..f863aa72 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -32,6 +32,7 @@ #include "common/therm/therm_gm20b.h" #include "common/ltc/ltc_gm20b.h" #include "common/fuse/fuse_gm20b.h" +#include "common/mc/mc_gm20b.h" #include "gk20a/gk20a.h" #include "gk20a/ce2_gk20a.h" @@ -39,7 +40,6 @@ #include "gk20a/fifo_gk20a.h" #include "gk20a/mm_gk20a.h" #include "gk20a/css_gr_gk20a.h" -#include "gk20a/mc_gk20a.h" #include "gk20a/flcn_gk20a.h" #include "gk20a/regops_gk20a.h" #include "gk20a/pmu_gk20a.h" @@ -578,23 +578,22 @@ static const struct gpu_ops gm20b_ops = { .get_qctl_whitelist_count = gm20b_get_qctl_whitelist_count, }, .mc = { - .intr_mask = mc_gk20a_intr_mask, - .intr_enable = mc_gk20a_intr_enable, - .intr_unit_config = mc_gk20a_intr_unit_config, - .isr_stall = mc_gk20a_isr_stall, - .intr_stall = mc_gk20a_intr_stall, - .intr_stall_pause = mc_gk20a_intr_stall_pause, - .intr_stall_resume = mc_gk20a_intr_stall_resume, - .intr_nonstall = mc_gk20a_intr_nonstall, - .intr_nonstall_pause = mc_gk20a_intr_nonstall_pause, - .intr_nonstall_resume = mc_gk20a_intr_nonstall_resume, - .isr_nonstall = mc_gk20a_isr_nonstall, - .enable = gk20a_mc_enable, - .disable = gk20a_mc_disable, - .reset = gk20a_mc_reset, - .boot_0 = gk20a_mc_boot_0, - .is_intr1_pending = mc_gk20a_is_intr1_pending, - .log_pending_intrs = mc_gk20a_log_pending_intrs, + .intr_mask = gm20b_mc_intr_mask, + .intr_enable = gm20b_mc_intr_enable, + .intr_unit_config = gm20b_mc_intr_unit_config, + .isr_stall = gm20b_mc_isr_stall, + .intr_stall = gm20b_mc_intr_stall, + .intr_stall_pause = gm20b_mc_intr_stall_pause, + .intr_stall_resume = gm20b_mc_intr_stall_resume, + .intr_nonstall = gm20b_mc_intr_nonstall, + .intr_nonstall_pause = gm20b_mc_intr_nonstall_pause, + .intr_nonstall_resume = gm20b_mc_intr_nonstall_resume, + .isr_nonstall = gm20b_mc_isr_nonstall, + .enable = gm20b_mc_enable, + .disable = gm20b_mc_disable, + .reset = gm20b_mc_reset, + .is_intr1_pending = gm20b_mc_is_intr1_pending, + .log_pending_intrs = gm20b_mc_log_pending_intrs, }, .debug = { .show_dump = gk20a_debug_show_dump, diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 69a797a6..a1682c79 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -40,6 +40,8 @@ #include "common/fuse/fuse_gm20b.h" #include "common/fuse/fuse_gp10b.h" #include "common/fuse/fuse_gp106.h" +#include "common/mc/mc_gm20b.h" +#include "common/mc/mc_gp10b.h" #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" @@ -49,13 +51,11 @@ #include "gk20a/css_gr_gk20a.h" #include "gk20a/flcn_gk20a.h" #include "gk20a/regops_gk20a.h" -#include "gk20a/mc_gk20a.h" #include "gk20a/pmu_gk20a.h" #include "gk20a/gr_gk20a.h" #include "gp10b/gr_gp10b.h" #include "gp10b/fecs_trace_gp10b.h" -#include "gp10b/mc_gp10b.h" #include "gp10b/mm_gp10b.h" #include "gp10b/ce_gp10b.h" #include "gp10b/regops_gp10b.h" @@ -714,11 +714,10 @@ static const struct gpu_ops gp106_ops = { .intr_nonstall = mc_gp10b_intr_nonstall, .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, - .isr_nonstall = mc_gk20a_isr_nonstall, - .enable = gk20a_mc_enable, - .disable = gk20a_mc_disable, - .reset = gk20a_mc_reset, - .boot_0 = gk20a_mc_boot_0, + .isr_nonstall = gm20b_mc_isr_nonstall, + .enable = gm20b_mc_enable, + .disable = gm20b_mc_disable, + .reset = gm20b_mc_reset, .is_intr1_pending = mc_gp10b_is_intr1_pending, .log_pending_intrs = mc_gp10b_log_pending_intrs, }, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index af64d2a9..9430595b 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -37,6 +37,8 @@ #include "common/ltc/ltc_gp10b.h" #include "common/fuse/fuse_gm20b.h" #include "common/fuse/fuse_gp10b.h" +#include "common/mc/mc_gm20b.h" +#include "common/mc/mc_gp10b.h" #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" @@ -46,14 +48,12 @@ #include "gk20a/css_gr_gk20a.h" #include "gk20a/flcn_gk20a.h" #include "gk20a/regops_gk20a.h" -#include "gk20a/mc_gk20a.h" #include "gk20a/pmu_gk20a.h" #include "gk20a/gr_gk20a.h" #include "gk20a/tsg_gk20a.h" #include "gp10b/gr_gp10b.h" #include "gp10b/fecs_trace_gp10b.h" -#include "gp10b/mc_gp10b.h" #include "gp10b/mm_gp10b.h" #include "gp10b/ce_gp10b.h" #include "gp10b/pmu_gp10b.h" @@ -640,11 +640,10 @@ static const struct gpu_ops gp10b_ops = { .intr_nonstall = mc_gp10b_intr_nonstall, .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, - .isr_nonstall = mc_gk20a_isr_nonstall, - .enable = gk20a_mc_enable, - .disable = gk20a_mc_disable, - .reset = gk20a_mc_reset, - .boot_0 = gk20a_mc_boot_0, + .isr_nonstall = gm20b_mc_isr_nonstall, + .enable = gm20b_mc_enable, + .disable = gm20b_mc_disable, + .reset = gm20b_mc_reset, .is_intr1_pending = mc_gp10b_is_intr1_pending, .log_pending_intrs = mc_gp10b_log_pending_intrs, }, diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c deleted file mode 100644 index 033d02c5..00000000 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - * GP10B master - * - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "gk20a/gk20a.h" -#include - -#include "mc_gp10b.h" - -#include -#include - -#include - -#define MAX_MC_INTR_REGS 2U - -void mc_gp10b_intr_mask(struct gk20a *g) -{ - nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), - 0xffffffffU); - - nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), - 0xffffffffU); -} - -void mc_gp10b_intr_enable(struct gk20a *g) -{ - u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); - - gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), - 0xffffffffU); - g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] = - mc_intr_pfifo_pending_f() | - mc_intr_priv_ring_pending_f() | - mc_intr_pbus_pending_f() | - mc_intr_ltc_pending_f() | - mc_intr_replayable_fault_pending_f() | - eng_intr_mask; - gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), - g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]); - - gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), - 0xffffffffU); - g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = - mc_intr_pfifo_pending_f() | - eng_intr_mask; - gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), - g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); -} - -void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable, - bool is_stalling, u32 mask) -{ - u32 intr_index = 0; - u32 reg = 0; - - intr_index = (is_stalling ? NVGPU_MC_INTR_STALLING : - NVGPU_MC_INTR_NONSTALLING); - if (enable) { - reg = mc_intr_en_set_r(intr_index); - g->mc_intr_mask_restore[intr_index] |= mask; - - } else { - reg = mc_intr_en_clear_r(intr_index); - g->mc_intr_mask_restore[intr_index] &= ~mask; - } - - gk20a_writel(g, reg, mask); -} - -void mc_gp10b_isr_stall(struct gk20a *g) -{ - u32 mc_intr_0; - - u32 engine_id_idx; - u32 active_engine_id = 0; - u32 engine_enum = ENGINE_INVAL_GK20A; - - mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); - - nvgpu_log(g, gpu_dbg_intr, "stall intr 0x%08x\n", mc_intr_0); - - for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) { - active_engine_id = g->fifo.active_engines_list[engine_id_idx]; - - if ((mc_intr_0 & g->fifo.engine_info[active_engine_id].intr_mask) != 0U) { - engine_enum = g->fifo.engine_info[active_engine_id].engine_enum; - /* GR Engine */ - if (engine_enum == ENGINE_GR_GK20A) { - gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); - } - - /* CE Engine */ - if (((engine_enum == ENGINE_GRCE_GK20A) || - (engine_enum == ENGINE_ASYNC_CE_GK20A)) && - (g->ops.ce2.isr_stall != NULL)) { - g->ops.ce2.isr_stall(g, - g->fifo.engine_info[active_engine_id].inst_id, - g->fifo.engine_info[active_engine_id].pri_base); - } - } - } - if ((g->ops.mc.is_intr_hub_pending != NULL) && - g->ops.mc.is_intr_hub_pending(g, mc_intr_0)) { - g->ops.fb.hub_isr(g); - } - if ((mc_intr_0 & mc_intr_pfifo_pending_f()) != 0U) { - gk20a_fifo_isr(g); - } - if ((mc_intr_0 & mc_intr_pmu_pending_f()) != 0U) { - g->ops.pmu.pmu_isr(g); - } - if ((mc_intr_0 & mc_intr_priv_ring_pending_f()) != 0U) { - g->ops.priv_ring.isr(g); - } - if ((mc_intr_0 & mc_intr_ltc_pending_f()) != 0U) { - g->ops.ltc.isr(g); - } - if ((mc_intr_0 & mc_intr_pbus_pending_f()) != 0U) { - g->ops.bus.isr(g); - } - if ((g->ops.mc.is_intr_nvlink_pending != NULL) && - g->ops.mc.is_intr_nvlink_pending(g, mc_intr_0)) { - g->ops.nvlink.isr(g); - } - if (mc_intr_0 & mc_intr_pfb_pending_f() && g->ops.fb.fbpa_isr) { - g->ops.fb.fbpa_isr(g); - } - - nvgpu_log(g, gpu_dbg_intr, "stall intr done 0x%08x\n", mc_intr_0); - -} - -u32 mc_gp10b_intr_stall(struct gk20a *g) -{ - return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING)); -} - -void mc_gp10b_intr_stall_pause(struct gk20a *g) -{ - gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), 0xffffffffU); -} - -void mc_gp10b_intr_stall_resume(struct gk20a *g) -{ - gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), - g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]); -} - -u32 mc_gp10b_intr_nonstall(struct gk20a *g) -{ - return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_NONSTALLING)); -} - -void mc_gp10b_intr_nonstall_pause(struct gk20a *g) -{ - gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), - 0xffffffffU); -} - -void mc_gp10b_intr_nonstall_resume(struct gk20a *g) -{ - gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), - g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); -} - -bool mc_gp10b_is_intr1_pending(struct gk20a *g, - enum nvgpu_unit unit, u32 mc_intr_1) -{ - u32 mask = 0; - bool is_pending; - - switch (unit) { - case NVGPU_UNIT_FIFO: - mask = mc_intr_pfifo_pending_f(); - break; - default: - break; - } - - if (mask == 0U) { - nvgpu_err(g, "unknown unit %d", unit); - is_pending = false; - } else { - is_pending = ((mc_intr_1 & mask) != 0U) ? true : false; - } - - return is_pending; -} - -void mc_gp10b_log_pending_intrs(struct gk20a *g) -{ - u32 i, intr; - - for (i = 0; i < MAX_MC_INTR_REGS; i++) { - intr = nvgpu_readl(g, mc_intr_r(i)); - if (intr == 0U) { - continue; - } - nvgpu_info(g, "Pending intr%d=0x%08x", i, intr); - } - -} diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/mc_gp10b.h deleted file mode 100644 index 8c22de62..00000000 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef MC_GP20B_H -#define MC_GP20B_H -struct gk20a; - -#define NVGPU_MC_INTR_STALLING 0U -#define NVGPU_MC_INTR_NONSTALLING 1U - -void mc_gp10b_intr_mask(struct gk20a *g); -void mc_gp10b_intr_enable(struct gk20a *g); -void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable, - bool is_stalling, u32 mask); -void mc_gp10b_isr_stall(struct gk20a *g); -bool mc_gp10b_is_intr1_pending(struct gk20a *g, - enum nvgpu_unit unit, u32 mc_intr_1); - -void mc_gp10b_log_pending_intrs(struct gk20a *g); -u32 mc_gp10b_intr_stall(struct gk20a *g); -void mc_gp10b_intr_stall_pause(struct gk20a *g); -void mc_gp10b_intr_stall_resume(struct gk20a *g); -u32 mc_gp10b_intr_nonstall(struct gk20a *g); -void mc_gp10b_intr_nonstall_pause(struct gk20a *g); -void mc_gp10b_intr_nonstall_resume(struct gk20a *g); - -#endif diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 4af237b0..d6ee0139 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -45,12 +45,15 @@ #include "common/fuse/fuse_gp10b.h" #include "common/fuse/fuse_gp106.h" #include "common/top/top_gv100.h" +#include "common/mc/mc_gm20b.h" +#include "common/mc/mc_gp10b.h" +#include "common/mc/mc_gv11b.h" +#include "common/mc/mc_gv100.h" #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" #include "gk20a/fecs_trace_gk20a.h" #include "gk20a/css_gr_gk20a.h" -#include "gk20a/mc_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/flcn_gk20a.h" #include "gk20a/regops_gk20a.h" @@ -74,7 +77,6 @@ #include "gp106/flcn_gp106.h" #include "gp10b/gr_gp10b.h" -#include "gp10b/mc_gp10b.h" #include "gp10b/ce_gp10b.h" #include "gp10b/fifo_gp10b.h" #include "gp10b/fecs_trace_gp10b.h" @@ -85,7 +87,6 @@ #include "gv11b/dbg_gpu_gv11b.h" #include "gv11b/hal_gv11b.h" #include "gv11b/gr_gv11b.h" -#include "gv11b/mc_gv11b.h" #include "gv11b/gv11b.h" #include "gv11b/ce_gv11b.h" #include "gv11b/mm_gv11b.h" @@ -102,7 +103,6 @@ #include "gv100/flcn_gv100.h" #include "gv100/gr_ctx_gv100.h" #include "gv100/gr_gv100.h" -#include "gv100/mc_gv100.h" #include "gv100/mm_gv100.h" #include "gv100/pmu_gv100.h" #include "gv100/nvlink_gv100.h" @@ -805,11 +805,10 @@ static const struct gpu_ops gv100_ops = { .intr_nonstall = mc_gp10b_intr_nonstall, .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, - .isr_nonstall = mc_gk20a_isr_nonstall, - .enable = gk20a_mc_enable, - .disable = gk20a_mc_disable, - .reset = gk20a_mc_reset, - .boot_0 = gk20a_mc_boot_0, + .isr_nonstall = gm20b_mc_isr_nonstall, + .enable = gm20b_mc_enable, + .disable = gm20b_mc_disable, + .reset = gm20b_mc_reset, .log_pending_intrs = mc_gp10b_log_pending_intrs, .is_intr1_pending = mc_gp10b_is_intr1_pending, .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending, diff --git a/drivers/gpu/nvgpu/gv100/mc_gv100.c b/drivers/gpu/nvgpu/gv100/mc_gv100.c deleted file mode 100644 index 069a012a..00000000 --- a/drivers/gpu/nvgpu/gv100/mc_gv100.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * GV100 master - * - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -#include "gk20a/gk20a.h" - -#include "gp10b/mc_gp10b.h" - -#include "mc_gv100.h" - -#include - -void mc_gv100_intr_enable(struct gk20a *g) -{ - u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); - - gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), - 0xffffffffU); - gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), - 0xffffffffU); - g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] = - mc_intr_pfifo_pending_f() | - mc_intr_hub_pending_f() | - mc_intr_priv_ring_pending_f() | - mc_intr_pbus_pending_f() | - mc_intr_ltc_pending_f() | - mc_intr_nvlink_pending_f() | - eng_intr_mask; - - g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = - mc_intr_pfifo_pending_f() - | eng_intr_mask; - - gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), - g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]); - - gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), - g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); - -} - -bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0) -{ - return (((mc_intr_0 & mc_intr_nvlink_pending_f()) != 0U) ? true : false); -} - -bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, - u32 *eng_intr_pending) -{ - u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); - u32 stall_intr, eng_intr_mask; - - eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id); - *eng_intr_pending = mc_intr_0 & eng_intr_mask; - - stall_intr = mc_intr_pfifo_pending_f() | - mc_intr_hub_pending_f() | - mc_intr_priv_ring_pending_f() | - mc_intr_pbus_pending_f() | - mc_intr_ltc_pending_f() | - mc_intr_nvlink_pending_f(); - - nvgpu_log(g, gpu_dbg_info | gpu_dbg_intr, - "mc_intr_0 = 0x%08x, eng_intr = 0x%08x", - mc_intr_0 & stall_intr, *eng_intr_pending); - - return (mc_intr_0 & (eng_intr_mask | stall_intr)) != 0U; -} diff --git a/drivers/gpu/nvgpu/gv100/mc_gv100.h b/drivers/gpu/nvgpu/gv100/mc_gv100.h deleted file mode 100644 index e9069258..00000000 --- a/drivers/gpu/nvgpu/gv100/mc_gv100.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef MC_GV100_H -#define MC_GV100_H -struct gk20a; - -void mc_gv100_intr_enable(struct gk20a *g); -bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0); -bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, - u32 *eng_intr_pending); -#endif diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 64b8084e..4632d3f8 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -59,7 +59,6 @@ #include "fifo_gv11b.h" #include "subctx_gv11b.h" #include "gr_gv11b.h" -#include "mc_gv11b.h" void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist) { diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index a27d9ab5..91122fba 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -40,12 +40,14 @@ #include "common/ltc/ltc_gv11b.h" #include "common/fuse/fuse_gm20b.h" #include "common/fuse/fuse_gp10b.h" +#include "common/mc/mc_gm20b.h" +#include "common/mc/mc_gp10b.h" +#include "common/mc/mc_gv11b.h" #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" #include "gk20a/fecs_trace_gk20a.h" #include "gk20a/css_gr_gk20a.h" -#include "gk20a/mc_gk20a.h" #include "gk20a/mm_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/flcn_gk20a.h" @@ -59,7 +61,6 @@ #include "gm20b/acr_gm20b.h" #include "gm20b/pmu_gm20b.h" -#include "gp10b/mc_gp10b.h" #include "gp10b/ce_gp10b.h" #include "gp10b/fifo_gp10b.h" #include "gp10b/fecs_trace_gp10b.h" @@ -76,7 +77,6 @@ #include "hal_gv11b.h" #include "css_gr_gv11b.h" #include "gr_gv11b.h" -#include "mc_gv11b.h" #include "gv11b.h" #include "ce_gv11b.h" #include "gr_ctx_gv11b.h" @@ -736,11 +736,10 @@ static const struct gpu_ops gv11b_ops = { .intr_nonstall = mc_gp10b_intr_nonstall, .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, - .isr_nonstall = mc_gk20a_isr_nonstall, - .enable = gk20a_mc_enable, - .disable = gk20a_mc_disable, - .reset = gk20a_mc_reset, - .boot_0 = gk20a_mc_boot_0, + .isr_nonstall = gm20b_mc_isr_nonstall, + .enable = gm20b_mc_enable, + .disable = gm20b_mc_disable, + .reset = gm20b_mc_reset, .is_intr1_pending = mc_gp10b_is_intr1_pending, .log_pending_intrs = mc_gp10b_log_pending_intrs, .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending, diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c deleted file mode 100644 index c8072d13..00000000 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * GV11B master - * - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -#include "gk20a/gk20a.h" - -#include "gp10b/mc_gp10b.h" - -#include "mc_gv11b.h" - -#include - -void mc_gv11b_intr_enable(struct gk20a *g) -{ - u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); - - gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), - 0xffffffffU); - gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), - 0xffffffffU); - - g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] = - mc_intr_pfifo_pending_f() | - mc_intr_hub_pending_f() | - mc_intr_priv_ring_pending_f() | - mc_intr_pbus_pending_f() | - mc_intr_ltc_pending_f() | - eng_intr_mask; - - g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = - mc_intr_pfifo_pending_f() - | eng_intr_mask; - - gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), - g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]); - - gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), - g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); - -} - -bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0) -{ - return (((mc_intr_0 & mc_intr_hub_pending_f()) != 0U) ? true : false); -} - -bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, - u32 *eng_intr_pending) -{ - u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); - u32 stall_intr, eng_intr_mask; - - eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id); - *eng_intr_pending = mc_intr_0 & eng_intr_mask; - - stall_intr = mc_intr_pfifo_pending_f() | - mc_intr_hub_pending_f() | - mc_intr_priv_ring_pending_f() | - mc_intr_pbus_pending_f() | - mc_intr_ltc_pending_f(); - - nvgpu_log(g, gpu_dbg_info | gpu_dbg_intr, - "mc_intr_0 = 0x%08x, eng_intr = 0x%08x", - mc_intr_0 & stall_intr, *eng_intr_pending); - - return (mc_intr_0 & (eng_intr_mask | stall_intr)) != 0U; -} diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.h b/drivers/gpu/nvgpu/gv11b/mc_gv11b.h deleted file mode 100644 index faa4d38d..00000000 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef MC_GV11B_H -#define MC_GV11B_H -struct gk20a; - -void mc_gv11b_intr_enable(struct gk20a *g); -bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0); -bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, - u32 *eng_intr_pending); -#endif diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index ceadc1c1..5d5aed94 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -32,7 +32,6 @@ #include "gk20a/mm_gk20a.h" #include "gp10b/mm_gp10b.h" -#include "gp10b/mc_gp10b.h" #include "mm_gv11b.h" #include "subctx_gv11b.h" diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 31ca1b45..56b14245 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -1166,7 +1166,6 @@ struct gpu_ops { void (*enable)(struct gk20a *g, u32 units); void (*disable)(struct gk20a *g, u32 units); void (*reset)(struct gk20a *g, u32 units); - u32 (*boot_0)(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev); bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit, u32 mc_intr_1); void (*log_pending_intrs)(struct gk20a *g); } mc; diff --git a/drivers/gpu/nvgpu/include/nvgpu/mc.h b/drivers/gpu/nvgpu/include/nvgpu/mc.h new file mode 100644 index 00000000..3c012f99 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/mc.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_MC_H +#define NVGPU_MC_H + +#include + +struct gk20a; + +#define NVGPU_MC_INTR_STALLING 0U +#define NVGPU_MC_INTR_NONSTALLING 1U + +u32 nvgpu_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev); + +#endif diff --git a/drivers/gpu/nvgpu/os/linux/intr.c b/drivers/gpu/nvgpu/os/linux/intr.c index 7ffc7e87..5ed6e35c 100644 --- a/drivers/gpu/nvgpu/os/linux/intr.c +++ b/drivers/gpu/nvgpu/os/linux/intr.c @@ -15,7 +15,6 @@ #include #include "gk20a/gk20a.h" -#include "gk20a/mc_gk20a.h" #include #include @@ -107,6 +106,21 @@ irqreturn_t nvgpu_intr_nonstall(struct gk20a *g) return IRQ_HANDLED; } +static void mc_gk20a_handle_intr_nonstall(struct gk20a *g, u32 ops) +{ + bool semaphore_wakeup, post_events; + + semaphore_wakeup = + (((ops & GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE) != 0U) ? + true : false); + post_events = (((ops & GK20A_NONSTALL_OPS_POST_EVENTS) != 0U) ? + true: false); + + if (semaphore_wakeup) { + g->ops.semaphore_wakeup(g, post_events); + } +} + void nvgpu_intr_nonstall_cb(struct work_struct *work) { struct nvgpu_os_linux *l = diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 58f595f4..a90d2d94 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c @@ -49,11 +49,9 @@ #include "vgpu_fuse_gp10b.h" #include "gk20a/flcn_gk20a.h" -#include "gk20a/mc_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/pmu_gk20a.h" -#include "gp10b/mc_gp10b.h" #include "gp10b/mm_gp10b.h" #include "gp10b/ce_gp10b.h" #include "gp10b/pmu_gp10b.h" @@ -484,7 +482,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { .enable = NULL, .disable = NULL, .reset = NULL, - .boot_0 = NULL, .is_intr1_pending = NULL, .log_pending_intrs = NULL, }, diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 9832a714..3a917bf3 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -54,7 +54,6 @@ #include "vgpu/gp10b/vgpu_gr_gp10b.h" #include -#include #include "gk20a/dbg_gpu_gk20a.h" #include @@ -66,7 +65,6 @@ #include #include -#include #include #include "gp10b/gr_gp10b.h" #include @@ -77,7 +75,6 @@ #include #include #include -#include #include #include #include @@ -553,7 +550,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { .enable = NULL, .disable = NULL, .reset = NULL, - .boot_0 = NULL, .is_intr1_pending = NULL, .is_intr_hub_pending = NULL, .log_pending_intrs = NULL , -- cgit v1.2.2