From 729403f545c5bc26ce208d38db65962596951e0a Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Thu, 7 Dec 2017 22:59:40 +0530 Subject: gpu: nvgpu: gv100: INIT WPR region using RPC - Created nv_pmu_rpc_struct_acr_init_wpr_region struct - Function gv100_pmu_init_acr() to create & execute INIT_WPR_REGION using RPC. - Updated gv100 HAL .init_wpr_region to point to gv100_pmu_init_acr() - Added code to handle INIT_WPR_REGION ack in RPC handler. Change-Id: I699fa945790689e5f24ad5d3de022efb458662e0 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1613290 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/common/pmu/pmu_ipc.c | 11 +++++- drivers/gpu/nvgpu/gv100/hal_gv100.c | 3 +- drivers/gpu/nvgpu/gv100/pmu_gv100.c | 45 ++++++++++++++++++++++ drivers/gpu/nvgpu/gv100/pmu_gv100.h | 32 +++++++++++++++ drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h | 23 ++++++++++- 6 files changed, 112 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/nvgpu/gv100/pmu_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/pmu_gv100.h (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 0ad630ff..680a9f4f 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -246,6 +246,7 @@ nvgpu-y += \ gv100/gr_gv100.o \ gv100/regops_gv100.o \ gv100/hal_gv100.o \ + gv100/pmu_gv100.o \ pstate/pstate.o \ clk/clk_vin.o \ clk/clk_fll.o \ diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c index 2811a4b0..77acbafc 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -993,6 +993,15 @@ static void pmu_rpc_handler(struct gk20a *g, struct pmu_msg *msg, } switch (msg->hdr.unit_id) { + case PMU_UNIT_ACR: + switch (rpc.function) { + case NV_PMU_RPC_ID_ACR_INIT_WPR_REGION: + nvgpu_pmu_dbg(g, + "reply NV_PMU_RPC_ID_ACR_INIT_WPR_REGION"); + g->pmu_lsf_pmu_wpr_init_done = 1; + break; + } + break; case PMU_UNIT_PERFMON_T18X: case PMU_UNIT_PERFMON: switch (rpc.function) { diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index f8302621..cf9ca9d8 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -103,6 +103,7 @@ #include "hal_gv100.h" #include "gv100/fb_gv100.h" #include "gv100/mm_gv100.h" +#include "gv100/pmu_gv100.h" #include #include @@ -572,7 +573,7 @@ static const struct gpu_ops gv100_ops = { .data032_r = pram_data032_r, }, .pmu = { - .init_wpr_region = gm20b_pmu_init_acr, + .init_wpr_region = gv100_pmu_init_acr, .load_lsfalcon_ucode = gp106_load_falcon_ucode, .is_lazy_bootstrap = gp106_is_lazy_bootstrap, .is_priv_load = gp106_is_priv_load, diff --git a/drivers/gpu/nvgpu/gv100/pmu_gv100.c b/drivers/gpu/nvgpu/gv100/pmu_gv100.c new file mode 100644 index 00000000..339df6af --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/pmu_gv100.c @@ -0,0 +1,45 @@ +/* + * GV100 PMU + * + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +#include "gk20a/gk20a.h" + +int gv100_pmu_init_acr(struct gk20a *g) +{ + struct nvgpu_pmu *pmu = &g->pmu; + struct nv_pmu_rpc_struct_acr_init_wpr_region rpc; + int status = 0; + + memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_acr_init_wpr_region)); + rpc.wpr_regionId = 0x1; + rpc.wpr_offset = 0x0; + PMU_RPC_EXECUTE(status, pmu, ACR, INIT_WPR_REGION, &rpc, 0); + if (status) { + nvgpu_err(g, "Failed to execute RPC status=0x%x", + status); + } + + return status; +} diff --git a/drivers/gpu/nvgpu/gv100/pmu_gv100.h b/drivers/gpu/nvgpu/gv100/pmu_gv100.h new file mode 100644 index 00000000..5ef34149 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/pmu_gv100.h @@ -0,0 +1,32 @@ +/* + * GV100 PMU + * + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __PMU_GV100_H_ +#define __PMU_GV100_H_ + +struct gk20a; + +int gv100_pmu_init_acr(struct gk20a *g); + +#endif /*__PMU_GV100_H_*/ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h index 2d31207f..bc3b1056 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -110,4 +110,25 @@ struct pmu_acr_msg { }; }; +/* ACR RPC */ +#define NV_PMU_RPC_ID_ACR_INIT_WPR_REGION 0x00 +#define NV_PMU_RPC_ID_ACR_WRITE_CBC_BASE 0x01 +#define NV_PMU_RPC_ID_ACR_BOOTSTRAP_FALCON 0x02 +#define NV_PMU_RPC_ID_ACR_BOOTSTRAP_GR_FALCONS 0x03 +#define NV_PMU_RPC_ID_ACR__COUNT 0x04 + +/* + * structure that holds data used + * to execute INIT_WPR_REGION RPC. + */ +struct nv_pmu_rpc_struct_acr_init_wpr_region { + /*[IN/OUT] Must be first field in RPC structure */ + struct nv_pmu_rpc_header hdr; + /*[IN] ACR region ID of WPR region */ + u32 wpr_regionId; + /* [IN] WPR offset from startAddress */ + u32 wpr_offset; + u32 scratch[1]; +}; + #endif /* _GPMUIFACR_H_ */ -- cgit v1.2.2