From 66ed536fb5e57ad73ffbaf24f9c02f0655e7d6cc Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Thu, 3 Nov 2016 17:42:59 +0530 Subject: gpu: nvgpu: rppg support Add defines and interface structures used for sending PMU messages to control RPPG. JIRA DNVGPU-71 Change-Id: Ibec975f3c976619542d8f088b24271796a03f03c Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1247487 (cherry picked from commit dd3826abca0a51d473d5d9cb25dc84cada9e7878) Reviewed-on: http://git-master/r/1270793 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gk20a/pmu_api.h | 7 ++- drivers/gpu/nvgpu/pmuif/gpmuif_pg_rppg.h | 101 +++++++++++++++++++++++++++++++ 2 files changed, 107 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/nvgpu/pmuif/gpmuif_pg_rppg.h (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/gk20a/pmu_api.h b/drivers/gpu/nvgpu/gk20a/pmu_api.h index d256f6d2..2fdd1333 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_api.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_api.h @@ -15,6 +15,7 @@ #define __PMU_API_H__ #include "pmu_common.h" +#include "pmuif/gpmuif_pg_rppg.h" /* PMU Command/Message Interfaces for Adaptive Power */ /* Macro to get Histogram index */ @@ -447,6 +448,7 @@ struct pmu_pg_msg { struct pmu_pg_msg_eng_buf_stat eng_buf_stat; /* TBD: other pg messages */ union pmu_ap_msg ap_msg; + struct nv_pmu_rppg_msg rppg_msg; }; }; @@ -478,7 +480,8 @@ enum { PMU_PG_CMD_ID_ZBC_TABLE_UPDATE, PMU_PG_CMD_ID_PWR_RAIL_GATE_DISABLE = 0x20, PMU_PG_CMD_ID_PWR_RAIL_GATE_ENABLE, - PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE + PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE, + PMU_PMU_PG_CMD_ID_RPPG = 0x24, }; struct pmu_pg_cmd_elpg_cmd { @@ -526,6 +529,7 @@ enum { #define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0) #define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED (1 << 2) +#define PMU_PG_FEATURE_GR_RPPG_ENABLED (1 << 3) struct pmu_pg_cmd_gr_init_param { u8 cmd_type; @@ -551,6 +555,7 @@ struct pmu_pg_cmd { struct pmu_pg_cmd_gr_init_param gr_init_param; /* TBD: other pg commands */ union pmu_ap_cmd ap_cmd; + struct nv_pmu_rppg_cmd rppg_cmd; }; }; diff --git a/drivers/gpu/nvgpu/pmuif/gpmuif_pg_rppg.h b/drivers/gpu/nvgpu/pmuif/gpmuif_pg_rppg.h new file mode 100644 index 00000000..7d5c8d41 --- /dev/null +++ b/drivers/gpu/nvgpu/pmuif/gpmuif_pg_rppg.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _GPMUIFRPPG_H_ +#define _GPMUIFRPPG_H_ + +#define NV_PMU_RPPG_CTRL_ID_GR (0x0000) +#define NV_PMU_RPPG_CTRL_ID_MS (0x0001) +#define NV_PMU_RPPG_CTRL_ID_DI (0x0002) +#define NV_PMU_RPPG_CTRL_ID_MAX (0x0003) + +#define NV_PMU_RPPG_CTRL_MASK_ENABLE_ALL (BIT(NV_PMU_RPPG_CTRL_ID_GR) |\ + BIT(NV_PMU_RPPG_CTRL_ID_MS) |\ + BIT(NV_PMU_RPPG_CTRL_ID_DI)) + +#define NV_PMU_RPPG_CTRL_MASK_DISABLE_ALL 0 + +enum { + NV_PMU_RPPG_DOMAIN_ID_GFX = 0x0, + NV_PMU_RPPG_DOMAIN_ID_NON_GFX, +}; + +struct nv_pmu_rppg_ctrl_stats { + u32 entry_count; + u32 exit_count; +}; + +struct nv_pmu_rppg_cmd_common { + u8 cmd_type; + u8 cmd_id; +}; + +struct nv_pmu_rppg_cmd_init { + u8 cmd_type; + u8 cmd_id; +}; + +struct nv_pmu_rppg_cmd_init_ctrl { + u8 cmd_type; + u8 cmd_id; + u8 ctrl_id; + u8 domain_id; +}; + +struct nv_pmu_rppg_cmd_stats_reset { + u8 cmd_type; + u8 cmd_id; + u8 ctrl_id; +}; + +struct nv_pmu_rppg_cmd { + union { + u8 cmd_type; + struct nv_pmu_rppg_cmd_common cmn; + struct nv_pmu_rppg_cmd_init init; + struct nv_pmu_rppg_cmd_init_ctrl init_ctrl; + struct nv_pmu_rppg_cmd_stats_reset stats_reset; + }; +}; + +enum { + NV_PMU_RPPG_CMD_ID_INIT = 0x0, + NV_PMU_RPPG_CMD_ID_INIT_CTRL, + NV_PMU_RPPG_CMD_ID_STATS_RESET, +}; + + +struct nv_pmu_rppg_msg_common { + u8 msg_type; + u8 msg_id; +}; + +struct nv_pmu_rppg_msg_init_ctrl_ack { + u8 msg_type; + u8 msg_id; + u8 ctrl_id; + u32 stats_dmem_offset; +}; + +struct nv_pmu_rppg_msg { + union { + u8 msg_type; + struct nv_pmu_rppg_msg_common cmn; + struct nv_pmu_rppg_msg_init_ctrl_ack init_ctrl_ack; + }; +}; + +enum { + NV_PMU_RPPG_MSG_ID_INIT_CTRL_ACK = 0x0, +}; + +#endif -- cgit v1.2.2