From 640cb6642fdb0ad5a4039aacf6c46e1ac30537a3 Mon Sep 17 00:00:00 2001 From: Supriya Date: Thu, 10 Dec 2015 12:56:59 +0530 Subject: gpu: nvgpu: LRF, TEX, LTC, DRAM override - Adding support for FECS mem overrides Bug 1699676 Change-Id: I6c9ddcd98d57b29059513ee508c6f92b194c4fc7 Signed-off-by: Supriya Reviewed-on: http://git-master/r/921253 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gk20a/gk20a.c | 16 ++++++------- drivers/gpu/nvgpu/gk20a/gk20a.h | 3 +++ drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 1 + drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 1 + drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 48 ++++++++++++++++++++++++++++++++++++- drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 6 ++++- drivers/gpu/nvgpu/gm20b/acr_gm20b.h | 7 +++++- drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 1 + drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 3 ++- 9 files changed, 74 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index d5f12f2b..54010a8e 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c @@ -1429,14 +1429,6 @@ static int gk20a_probe(struct platform_device *dev) if (IS_ENABLED(CONFIG_GK20A_DEVFREQ)) gk20a_scale_init(dev); - if (platform->late_probe) { - err = platform->late_probe(dev); - if (err) { - dev_err(&dev->dev, "late probe failed"); - return err; - } - } - /* Set DMA parameters to allow larger sgt lists */ dev->dev.dma_parms = &gk20a->dma_parms; dma_set_max_seg_size(&dev->dev, UINT_MAX); @@ -1475,6 +1467,14 @@ static int gk20a_probe(struct platform_device *dev) gk20a->pmu.aelpg_param[3] = APCTRL_POWER_BREAKEVEN_DEFAULT_US; gk20a->pmu.aelpg_param[4] = APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT; + if (platform->late_probe) { + err = platform->late_probe(dev); + if (err) { + dev_err(&dev->dev, "late probe failed"); + return err; + } + } + gk20a_create_sysfs(dev); #ifdef CONFIG_DEBUG_FS diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 01d1a167..340f358a 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -207,6 +207,7 @@ struct gpu_ops { int (*handle_tex_exception)(struct gk20a *g, u32 gpc, u32 tpc, bool *post_event); void (*create_gr_sysfs)(struct platform_device *dev); + u32 (*get_lrf_tex_ltc_dram_override)(struct gk20a *g); } gr; const char *name; struct { @@ -434,6 +435,8 @@ struct gpu_ops { u32 *gating_cnt); int (*pmu_pg_grinit_param)(struct gk20a *g, u8 grfeaturemask); + int (*send_lrf_tex_ltc_dram_overide_en_dis_cmd) + (struct gk20a *g, u32 mask); u32 lspmuwprinitdone; u32 lsfloadedfalconid; bool fecsbootstrapdone; diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 6c0e0539..187c9c0e 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -7637,4 +7637,5 @@ void gk20a_init_gr_ops(struct gpu_ops *gops) gops->gr.mask_hww_warp_esr = gk20a_mask_hww_warp_esr; gops->gr.handle_sm_exception = gr_gk20a_handle_sm_exception; gops->gr.handle_tex_exception = gr_gk20a_handle_tex_exception; + gops->gr.get_lrf_tex_ltc_dram_override = NULL; } diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index f73706a2..30592ee2 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c @@ -2771,6 +2771,7 @@ void gk20a_init_pmu_ops(struct gpu_ops *gops) gops->pmu.write_dmatrfbase = gk20a_write_dmatrfbase; gops->pmu.pmu_elpg_statistics = gk20a_pmu_elpg_statistics; gops->pmu.pmu_pg_grinit_param = NULL; + gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; } int gk20a_init_pmu_support(struct gk20a *g) diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index bf581b90..54d01947 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h @@ -50,7 +50,7 @@ #define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1) #define APP_VERSION_NC_1 20313802 -#define APP_VERSION_NC_0 20120791 +#define APP_VERSION_NC_0 20360931 #define APP_VERSION_GM20B_4 19008461 #define APP_VERSION_GM20B_3 18935575 #define APP_VERSION_GM20B_2 18694072 @@ -451,6 +451,8 @@ struct pmu_ucode_desc { #define PMU_UNIT_PERFMON_T18X (0x11) #define PMU_UNIT_PERFMON (0x12) #define PMU_UNIT_RC (0x1F) +#define PMU_UNIT_FECS_MEM_OVERRIDE (0x1E) + #define PMU_UNIT_END (0x23) #define PMU_UNIT_TEST_START (0xFE) @@ -814,6 +816,47 @@ struct pmu_acr_msg { #define PMU_DOMAIN_GROUP_GPC2CLK 1 #define PMU_DOMAIN_GROUP_NUM 2 +/* FECS mem override command*/ + +#define PMU_LRF_TEX_LTC_DRAM_CMD_ID_EN_DIS 0 + +/*! + * Enable/Disable FECS error feature + */ +struct pmu_cmd_lrf_tex_ltc_dram_en_dis { + /*Command type must be first*/ + u8 cmd_type; + /*unit bitmask*/ + u8 en_dis_mask; +}; + +struct pmu_lrf_tex_ltc_dram_cmd { + union { + u8 cmd_type; + struct pmu_cmd_lrf_tex_ltc_dram_en_dis en_dis; + }; +}; + +/* FECS mem override messages*/ +#define PMU_LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS 0 + +struct pmu_msg_lrf_tex_ltc_dram_en_dis { + /*! + * Must be at start + */ + u8 msg_type; + u8 en_fail_mask; + u8 dis_fail_mask; + u32 pmu_status; +}; + +struct pmu_lrf_tex_ltc_dram_msg { + union { + u8 msg_type; + struct pmu_msg_lrf_tex_ltc_dram_en_dis en_dis; + }; +}; + /* TBD: smart strategy */ #define PMU_PERFMON_PCT_TO_INC 58 #define PMU_PERFMON_PCT_TO_DEC 23 @@ -958,6 +1001,7 @@ struct pmu_cmd { struct pmu_pg_cmd pg; struct pmu_zbc_cmd zbc; struct pmu_acr_cmd acr; + struct pmu_lrf_tex_ltc_dram_cmd lrf_tex_ltc_dram; } cmd; }; @@ -969,6 +1013,7 @@ struct pmu_msg { struct pmu_pg_msg pg; struct pmu_rc_msg rc; struct pmu_acr_msg acr; + struct pmu_lrf_tex_ltc_dram_msg lrf_tex_ltc_dram; } msg; }; @@ -1318,6 +1363,7 @@ struct pmu_gk20a { u8 pmu_mode; /*Added for GM20b, and ACR*/ u32 falcon_id; u32 aelpg_param[5]; + u32 override_done; }; int gk20a_init_pmu_support(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index ee64b90f..9f137246 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -1300,6 +1300,8 @@ static int gm20b_init_pmu_setup_hw1(struct gk20a *g, pmu_enable_irq(pmu, false); pmu->isr_enabled = false; mutex_unlock(&pmu->isr_mutex); + /*Clearing mailbox register used to reflect capabilities*/ + gk20a_writel(g, pwr_falcon_mailbox1_r(), 0); err = bl_bootstrap(pmu, desc, bl_sz); if (err) return err; @@ -1436,6 +1438,8 @@ int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout) if (completion) gk20a_err(dev_from_gk20a(g), "ACR boot timed out"); else { + g->acr.capabilities = gk20a_readl(g, pwr_falcon_mailbox1_r()); + gm20b_dbg_pmu("ACR capabilities %x\n", g->acr.capabilities); data = gk20a_readl(g, pwr_falcon_mailbox0_r()); if (data) { gk20a_err(dev_from_gk20a(g), diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h index 58800c09..414e22b6 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h @@ -1,7 +1,7 @@ /* * GM20B ACR * - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -124,6 +124,10 @@ #define FLCN_NL_UCODE_HDR_OS_OVL_SIZE_IND(N) \ (FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 2) +enum acr_capabilities { + ACR_LRF_TEX_LTC_DRAM_PRIV_MASK_ENABLE_LS_OVERRIDE = (0x00000001), +}; + /*Externs*/ /*Structs*/ @@ -397,6 +401,7 @@ struct acr_gm20b { struct flcn_bl_dmem_desc bl_dmem_desc; const struct firmware *pmu_fw; const struct firmware *pmu_desc; + u32 capabilities; }; void gm20b_init_secure_pmu(struct gpu_ops *gops); diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 2a891647..67654cba 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -1232,4 +1232,5 @@ void gm20b_init_gr(struct gpu_ops *gops) gops->gr.mask_hww_warp_esr = gk20a_mask_hww_warp_esr; gops->gr.handle_sm_exception = gr_gk20a_handle_sm_exception; gops->gr.handle_tex_exception = gr_gk20a_handle_tex_exception; + gops->gr.get_lrf_tex_ltc_dram_override = NULL; } diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 4123e32a..ce3da2b6 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c @@ -1,7 +1,7 @@ /* * GM20B PMU * - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -308,4 +308,5 @@ void gm20b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.write_dmatrfbase = gm20b_write_dmatrfbase; gops->pmu.pmu_elpg_statistics = gk20a_pmu_elpg_statistics; gops->pmu.pmu_pg_grinit_param = NULL; + gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; } -- cgit v1.2.2