From 6194cfdef52afcb17aa2921685f370e4c5d27819 Mon Sep 17 00:00:00 2001 From: Supriya Date: Tue, 31 Oct 2017 11:54:53 +0530 Subject: gpu: nvgpu: split init_falcon_setup_hw This CL is as part of phased changes to support NO LSPMU Changes done are to add new pmu ops : - setup_apertures - update_lspmu_cmdline_args These would be called from pmu op init_falcon_setup_hw JIRA NVGPU-296 Change-Id: Idbcec5c93ca3150df5c9fb81d65b9fce778cecb8 Signed-off-by: Supriya Reviewed-on: https://git-master.nvidia.com/r/1589004 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gk20a.h | 2 ++ drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 45 ++++++++++++++++++++++++------------- drivers/gpu/nvgpu/gm20b/acr_gm20b.h | 2 ++ drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 3 +++ drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 3 +++ drivers/gpu/nvgpu/gv11b/acr_gv11b.c | 45 +++++++++++++++++-------------------- drivers/gpu/nvgpu/gv11b/acr_gv11b.h | 1 + drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 +++ 8 files changed, 63 insertions(+), 41 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 33d40cd5..e586913e 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -866,6 +866,8 @@ struct gpu_ops { void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid); void (*handle_ext_irq)(struct gk20a *g, u32 intr); void (*set_irqmask)(struct gk20a *g); + void (*update_lspmu_cmdline_args)(struct gk20a *g); + void (*setup_apertures)(struct gk20a *g); } pmu; struct { int (*init_debugfs)(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index 09908df3..62d3a8fa 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c @@ -1233,20 +1233,8 @@ int gm20b_init_nspmu_setup_hw1(struct gk20a *g) return err; } -int gm20b_init_pmu_setup_hw1(struct gk20a *g, - void *desc, u32 bl_sz) +void gm20b_setup_apertures(struct gk20a *g) { - - struct nvgpu_pmu *pmu = &g->pmu; - int err; - - gk20a_dbg_fn(""); - - nvgpu_mutex_acquire(&pmu->isr_mutex); - nvgpu_flcn_reset(pmu->flcn); - pmu->isr_enabled = true; - nvgpu_mutex_release(&pmu->isr_mutex); - /* setup apertures - virtual */ gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), pwr_fbif_transcfg_mem_type_physical_f() | @@ -1263,10 +1251,14 @@ int gm20b_init_pmu_setup_hw1(struct gk20a *g, gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), pwr_fbif_transcfg_mem_type_physical_f() | pwr_fbif_transcfg_target_noncoherent_sysmem_f()); +} +void gm20b_update_lspmu_cmdline_args(struct gk20a *g) +{ + struct nvgpu_pmu *pmu = &g->pmu; /*Copying pmu cmdline args*/ g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, - g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK)); + g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK)); g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1); g->ops.pmu_ver.set_pmu_cmdline_args_trace_size( pmu, GK20A_PMU_TRACE_BUFSIZE); @@ -1274,8 +1266,29 @@ int gm20b_init_pmu_setup_hw1(struct gk20a *g, g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx( pmu, GK20A_PMU_DMAIDX_VIRT); nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args, - (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), - g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); + (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), + g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); +} + +int gm20b_init_pmu_setup_hw1(struct gk20a *g, + void *desc, u32 bl_sz) +{ + + struct nvgpu_pmu *pmu = &g->pmu; + int err; + + gk20a_dbg_fn(""); + + nvgpu_mutex_acquire(&pmu->isr_mutex); + nvgpu_flcn_reset(pmu->flcn); + pmu->isr_enabled = true; + nvgpu_mutex_release(&pmu->isr_mutex); + + if (g->ops.pmu.setup_apertures) + g->ops.pmu.setup_apertures(g); + if (g->ops.pmu.update_lspmu_cmdline_args) + g->ops.pmu.update_lspmu_cmdline_args(g); + /*disable irqs for hs falcon booting as we will poll for halt*/ nvgpu_mutex_acquire(&pmu->isr_mutex); pmu_enable_irq(pmu, false); diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h index 9d261aae..e22da730 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h @@ -47,6 +47,8 @@ int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g, int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout_ms); int clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout); int gm20b_init_pmu_setup_hw1(struct gk20a *g, void *desc, u32 bl_sz); +void gm20b_update_lspmu_cmdline_args(struct gk20a *g); +void gm20b_setup_apertures(struct gk20a *g); int gm20b_pmu_setup_sw(struct gk20a *g); int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt); diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 779dde3d..920a3e9b 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -660,6 +660,9 @@ int gm20b_init_hal(struct gk20a *g) gops->pmu.falcon_clear_halt_interrupt_status = clear_halt_interrupt_status; gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1; + gops->pmu.update_lspmu_cmdline_args = + gm20b_update_lspmu_cmdline_args; + gops->pmu.setup_apertures = gm20b_setup_apertures; gops->pmu.init_wpr_region = gm20b_pmu_init_acr; gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode; diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 335eb465..f13c2735 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -689,6 +689,9 @@ int gp10b_init_hal(struct gk20a *g) gops->pmu.falcon_clear_halt_interrupt_status = clear_halt_interrupt_status, gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1, + gops->pmu.update_lspmu_cmdline_args = + gm20b_update_lspmu_cmdline_args; + gops->pmu.setup_apertures = gm20b_setup_apertures; gops->pmu.init_wpr_region = gm20b_pmu_init_acr; gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; diff --git a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c index b245dbc6..33a36596 100644 --- a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c @@ -237,20 +237,8 @@ static int bl_bootstrap(struct nvgpu_pmu *pmu, return 0; } -int gv11b_init_pmu_setup_hw1(struct gk20a *g, - void *desc, u32 bl_sz) +void gv11b_setup_apertures(struct gk20a *g) { - - struct nvgpu_pmu *pmu = &g->pmu; - int err; - - gk20a_dbg_fn(""); - - nvgpu_mutex_acquire(&pmu->isr_mutex); - nvgpu_flcn_reset(pmu->flcn); - pmu->isr_enabled = true; - nvgpu_mutex_release(&pmu->isr_mutex); - /* setup apertures - virtual */ gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), pwr_fbif_transcfg_mem_type_physical_f() | @@ -267,19 +255,26 @@ int gv11b_init_pmu_setup_hw1(struct gk20a *g, gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), pwr_fbif_transcfg_mem_type_physical_f() | pwr_fbif_transcfg_target_noncoherent_sysmem_f()); +} + +int gv11b_init_pmu_setup_hw1(struct gk20a *g, + void *desc, u32 bl_sz) +{ + struct nvgpu_pmu *pmu = &g->pmu; + int err; + + gk20a_dbg_fn(""); + + nvgpu_mutex_acquire(&pmu->isr_mutex); + nvgpu_flcn_reset(pmu->flcn); + pmu->isr_enabled = true; + nvgpu_mutex_release(&pmu->isr_mutex); + + if (g->ops.pmu.setup_apertures) + g->ops.pmu.setup_apertures(g); + if (g->ops.pmu.update_lspmu_cmdline_args) + g->ops.pmu.update_lspmu_cmdline_args(g); - /*Copying pmu cmdline args*/ - g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, - g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK)); - g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1); - g->ops.pmu_ver.set_pmu_cmdline_args_trace_size( - pmu, GK20A_PMU_TRACE_BUFSIZE); - g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu); - g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx( - pmu, GK20A_PMU_DMAIDX_VIRT); - nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args, - (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), - g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); /*disable irqs for hs falcon booting as we will poll for halt*/ nvgpu_mutex_acquire(&pmu->isr_mutex); pmu_enable_irq(pmu, false); diff --git a/drivers/gpu/nvgpu/gv11b/acr_gv11b.h b/drivers/gpu/nvgpu/gv11b/acr_gv11b.h index 72b3ec35..5fbe45e2 100644 --- a/drivers/gpu/nvgpu/gv11b/acr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/acr_gv11b.h @@ -27,4 +27,5 @@ int gv11b_bootstrap_hs_flcn(struct gk20a *g); int gv11b_init_pmu_setup_hw1(struct gk20a *g, void *desc, u32 bl_sz); +void gv11b_setup_apertures(struct gk20a *g); #endif /*__PMU_GP106_H_*/ diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 8278d4e5..5649d758 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -747,6 +747,9 @@ int gv11b_init_hal(struct gk20a *g) gops->pmu.falcon_clear_halt_interrupt_status = clear_halt_interrupt_status, gops->pmu.init_falcon_setup_hw = gv11b_init_pmu_setup_hw1, + gops->pmu.update_lspmu_cmdline_args = + gm20b_update_lspmu_cmdline_args; + gops->pmu.setup_apertures = gv11b_setup_apertures; gops->pmu.init_wpr_region = gm20b_pmu_init_acr; gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; -- cgit v1.2.2